SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 1991 REVISED JULY 1994
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1 State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 305; Exceeds 200 V Using Machine Model (C = 200 pf, R = 0) Latch-Up Performance Exceeds 500 ma Per JEDEC Standard JESD-7 Typical V OLP (Output Ground Bounce) < V at V CC = 5 V, T A = 25 C High-Drive Outputs ( 32-mA I OH, 64-mA I OL ) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs description These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure illustrates the four fundamental bus-management functions that can be performed with the ABT646. Output-enable () and direction-control () inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 SN54ABT JT PACKAGE SN74ABT DB, DW, NT, OR PW PACKAGE (TOP VIEW) A A2 A3 NC A4 A5 A6 CLKAB SAB A A2 A3 A4 A5 A6 A7 A8 GND SN54ABT FK PACKAGE (TOP VIEW) SAB CLKAB NC NC B8 V CC B7 B A A8 GND CLKBA SBA NC No internal connection V CC CLKBA SBA B B2 B3 B4 B5 B6 B7 B8 The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control () determines which bus will receive data when is low. In the isolation mode ( high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. To ensure the high-impedance state during power up or power down, should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT646 is available in TI s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54ABT646 is characterized for operation over the full military temperature range of 55 C to 25 C. The SN74ABT646 is characterized for operation from 40 C to 85 C. B B2 NC B3 B4 B5 EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 994, Texas Instruments Incorporated POST OFFICE BO DALLAS, TEAS
2 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY L 3 L CLKAB 23 CLKBA 2 SAB 22 SBA L 2 L 3 H CLKAB 23 CLKBA 2 SAB L 22 SBA REAL-TIME TRANSFER BUS B TO BUS A REAL-TIME TRANSFER BUS A TO BUS B BUS A BUS B BUS A BUS B BUS A BUS B BUS A BUS B 2 H 3 CLKAB 23 CLKBA STORAGE FROM A, B, OR A AND B 2 SAB 22 SBA 2 L 3 L CLKAB 23 CLKBA L 2 SAB 22 SBA H L H L H TRANSFER STORED DATA TO A AND/OR B Pin numbers shown are for DB, DW, JT, NT, and PW packages. Figure. Bus-Management Functions 2 2 POST OFFICE BO DALLAS, TEAS 75265
3 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 FUNCTION TABLE INPUTS DATA I/Os OPERATION OR FUNCTION CLKAB CLKBA SAB SBA A THRU A8 B THRU B8 Input Unspecified Store A, B unspecified Unspecified Input Store B, A unspecified H Input Input Store A and B data H H or L H or L Input disabled Input disabled Isolation, hold storage L L L Output Input Real-time B data to A bus L L H or L H Output Input Stored B data to A bus L H L Input Output Real-time A data to B bus L H H or L H Input Output Stored A data to B bus The data output functions may be enabled or disabled by various signals at the and inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs. logic symbol CLKBA SBA CLKAB SAB A A2 A3 A4 A5 A6 A7 A8 2 3 G3 3 EN [BA] 23 3 EN2 [AB] C4 22 G5 C6 2 G D B 5 6D B2 6 8 B3 7 7 B4 8 6 B5 9 5 B6 0 4 B7 3 B8 This symbol is in accordance with ANSI/IEEE Std and IEC Publication Pin numbers shown are for the DB, DW, JT, NT, and PW packages. POST OFFICE BO DALLAS, TEAS
4 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 logic diagram (positive logic) 2 CLKBA SBA CLKAB SAB One of Eight Channels D C A 4 D 20 B C Pin numbers shown are for the DB, DW, JT, NT, and PW packages. To Seven Other Channels 2 4 POST OFFICE BO DALLAS, TEAS 75265
5 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (except I/O ports) (see Note ) V to 7 V Voltage range applied to any output in the high state or power-off state, V O V to 5.5 V Current into any output in the low state, I O : SN54ABT ma SN74ABT ma Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0) ma Maximum power dissipation at T A = 55 C (in still air) (see Note 2): DB package W DW package W NT package W PW package W Storage temperature range C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 50 C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the 994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 3) SN54ABT646 SN74ABT646 UNIT MIN MA MIN MA VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V VI Input voltage 0 VCC 0 VCC V IOH High-level output current ma IOL Low-level output current ma t/ v Input transition rise or fall rate 5 5 ns / V TA Operating free-air temperature C NOTE 3: Unused or floating pins (input or I/O) must be held high or low. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BO DALLAS, TEAS
6 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25 C SN54ABT646 SN74ABT646 MIN TYP MA MIN MA MIN MA VIK VCC = 4.5 V, II = 8 ma V VOH VCC = 4.5 V, IOH = 3 ma VCC = 5 V, IOH = 3 ma VCC =45V 4.5 VOL VCC =45V 4.5 II IOH = 24 ma 2 2 IOH = 32 ma 2* 2 IOL = 48 ma IOL = 64 ma 0.55* 0.55 VCC = 5.5 V, Control inputs ± ± ± VI = VCC or GND A or B ports ±00 ±00 ±00 IOZH VCC = 5.5 V, VO = 2.7 V µa IOZL VCC = 5.5 V, VO = 0.5 V µa Ioff VCC = 0, VI or VO 4.5 V ±00 ±00 µa ICE VCC = 5.5 V, VO = 5.5 V Outputs high µa IO VCC = 5.5 V, VO = 2.5 V ma ICC VCC = V, IO = 0, VI =VCC or GND ICC # VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND UNIT Outputs high µa Outputs low ma Outputs disabled µa V V µa ma Ci VI = 2.5 V or 0.5 V Control inputs 7 pf Cio VO = 2.5 V or 0.5 V A or B ports 2 pf * On products compliant to MIL-STD-883, Class B, this parameter does not apply. All typical values are at VCC = 5 V. The parameters IOZH and IOZL include the input leakage current. This data sheet limit may vary among suppliers. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) VCC = 5 V, TA = 25 C SN54ABT646 SN74ABT646 MIN MA MIN MA MIN MA fclock Clock frequency MHz tw Pulse duration, CLK high or low ns tsu Setup time, A or B before CLKAB or CLKBA High Low th Hold time, A or B after CLKAB or CLKBA ns UNIT ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2 6 POST OFFICE BO DALLAS, TEAS 75265
7 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C L = 50 pf (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25 C SN54ABT646 SN74ABT646 MIN TYP MA MIN MA MIN MA fmax MHz tplh CLKBA or CLKAB A or B tphl tplh AorB BorA tphl tplh SAB or SBA BorA tphl tpzh AorB tpzl tphz AorB tplz tpzh AorB tpzl tphz AorB tplz These parameters are measured with the internal output state of the storage register opposite to that of the bus input. UNIT ns ns ns ns ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BO DALLAS, TEAS
8 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 PARAMETER MEASUREMENT INFORMATION 7 V From Output Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S Open GND TEST tplh/tphl tplz/tpzl tphz/tpzh S Open 7 V Open LOAD CIRCUIT FOR OUTPUTS Timing Input.5 V 3 V 0 V Input tw.5 V.5 V 3 V 0 V Data Input tsu th.5 V.5 V 3 V 0 V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input (see Note B) Output Output tplh tphl.5 V.5 V.5 V.5 V tphl.5 V tplh.5 V 3 V 0 V VOH VOL VOH VOL Output Control Output Waveform S at 7 V (see Note C) Output Waveform 2 S at Open (see Note C) tpzl tpzh.5 V tplz.5 V tphz.5 V.5 V VOL V VOH 0.3 V 3 V 0 V 3.5 V VOL VOH 0 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. B. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR 0 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. C. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 2 8 POST OFFICE BO DALLAS, TEAS 75265
9 PACKAGE OPTION ADDENDUM 28-May-2007 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) SN74ABT646DBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI SN74ABT646DBR ACTIVE SSOP DB Green (RoHS & SN74ABT646DBRE4 ACTIVE SSOP DB Green (RoHS & SN74ABT646DBRG4 ACTIVE SSOP DB Green (RoHS & SN74ABT646DGVR ACTIVE TVSOP DGV Green (RoHS & SN74ABT646DGVRE4 ACTIVE TVSOP DGV Green (RoHS & SN74ABT646DGVRG4 ACTIVE TVSOP DGV Green (RoHS & SN74ABT646DW ACTIVE SOIC DW Green (RoHS & SN74ABT646DWE4 ACTIVE SOIC DW Green (RoHS & SN74ABT646DWG4 ACTIVE SOIC DW Green (RoHS & SN74ABT646DWR ACTIVE SOIC DW Green (RoHS & SN74ABT646DWRE4 ACTIVE SOIC DW Green (RoHS & SN74ABT646DWRG4 ACTIVE SOIC DW Green (RoHS & SN74ABT646NT ACTIVE PDIP NT 24 5 Pb-Free (RoHS) SN74ABT646NTE4 ACTIVE PDIP NT 24 5 Pb-Free (RoHS) SN74ABT646PW ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWE4 ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWG4 ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWLE OBSOLETE TSSOP PW 24 TBD Call TI Call TI SN74ABT646PWR ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWRE4 ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWRG4 ACTIVE TSSOP PW Green (RoHS & N / A for Pkg Type N / A for Pkg Type () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page
10 PACKAGE OPTION ADDENDUM 28-May-2007 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
11 PACKAGE MATERIALS INFORMATION 4-Oct-2007 TAPE AND REEL BO INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant SN74ABT646DBR DB 24 SITE Q SN74ABT646DGVR DGV 24 SITE Q SN74ABT646PWR PW 24 SITE Q Pack Materials-Page
12 PACKAGE MATERIALS INFORMATION 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74ABT646DBR DB 24 SITE SN74ABT646DGVR DGV 24 SITE SN74ABT646PWR PW 24 SITE Pack Materials-Page 2
13 MECHANICAL DATA MPDI004 OCTOBER 994 NT (R-PDIP-T**) 24 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE A DIM PINS ** A MA.260 (32,04).425 (36,20) (7,) (6,35) A MIN.230 (3,24).385 (35,8) B MA 0.30 (7,87) 0.35 (8,00) (,78) MA 2 B MIN (7,37) (7,49) (0,5) MIN B (5,08) MA Seating Plane 0.25 (3,8) MIN 0.02 (0,53) 0.05 (0,38) 0.00 (0,25) 0.00 (2,54) M 0.00 (0,25) NOM / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. POST OFFICE BO DALLAS, TEAS 75265
14 MECHANICAL DATA MPDS006C FEBRUARY 996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,3 0,07 M ,6 NOM 4,50 4,30 6,60 6,20 Gage Plane 2 A 0 8 0,25 0,75 0,50,20 MA 0,5 0,05 Seating Plane 0,08 DIM PINS ** A MA 3,70 3,70 5,0 5,0 7,90 9,80,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60, /E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,5 per side. D. Falls within JEDEC: 24/48 Pins MO-53 4/6/20/56 Pins MO-94 POST OFFICE BO DALLAS, TEAS 75265
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16 MECHANICAL DATA MSSO002E JANUARY 995 REVISED DECEMBER 200 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,5 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane 4 0,25 A 0 8 0,95 0,55 2,00 MA 0,05 MIN Seating Plane 0,0 DIM PINS ** A MA 6,50 6,50 7,50 8,50 0,50 0,50 2,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 2, /E 2/0 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-50 POST OFFICE BO DALLAS, TEAS 75265
17 MECHANICAL DATA MTSS00C JANUARY 995 REVISED FEBRUARY 999 PW (R-PDSO-G**) 4 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,0 M 0, ,50 4,30 6,60 6,20 0,5 NOM Gage Plane A ,25 0,75 0,50,20 MA 0,5 0,05 Seating Plane 0,0 DIM PINS ** A MA 3,0 5,0 5,0 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 0/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53 POST OFFICE BO DALLAS, TEAS 75265
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Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
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Member of the Texas Instruments Widebus Family Max t pd of 5.8 ns at 3.3 ±24-mA Drive at 3.3 Latch-Up Performance Exceeds 250 ma Per JESD 17 description/ordering information This 16-bit (dual-octal) noninverting
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