SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 1991 REVISED JULY 1994

Size: px
Start display at page:

Download "SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 1991 REVISED JULY 1994"

Transcription

1 State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 305; Exceeds 200 V Using Machine Model (C = 200 pf, R = 0) Latch-Up Performance Exceeds 500 ma Per JEDEC Standard JESD-7 Typical V OLP (Output Ground Bounce) < V at V CC = 5 V, T A = 25 C High-Drive Outputs ( 32-mA I OH, 64-mA I OL ) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs description These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure illustrates the four fundamental bus-management functions that can be performed with the ABT646. Output-enable () and direction-control () inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 SN54ABT JT PACKAGE SN74ABT DB, DW, NT, OR PW PACKAGE (TOP VIEW) A A2 A3 NC A4 A5 A6 CLKAB SAB A A2 A3 A4 A5 A6 A7 A8 GND SN54ABT FK PACKAGE (TOP VIEW) SAB CLKAB NC NC B8 V CC B7 B A A8 GND CLKBA SBA NC No internal connection V CC CLKBA SBA B B2 B3 B4 B5 B6 B7 B8 The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control () determines which bus will receive data when is low. In the isolation mode ( high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. To ensure the high-impedance state during power up or power down, should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74ABT646 is available in TI s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54ABT646 is characterized for operation over the full military temperature range of 55 C to 25 C. The SN74ABT646 is characterized for operation from 40 C to 85 C. B B2 NC B3 B4 B5 EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 994, Texas Instruments Incorporated POST OFFICE BO DALLAS, TEAS

2 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY L 3 L CLKAB 23 CLKBA 2 SAB 22 SBA L 2 L 3 H CLKAB 23 CLKBA 2 SAB L 22 SBA REAL-TIME TRANSFER BUS B TO BUS A REAL-TIME TRANSFER BUS A TO BUS B BUS A BUS B BUS A BUS B BUS A BUS B BUS A BUS B 2 H 3 CLKAB 23 CLKBA STORAGE FROM A, B, OR A AND B 2 SAB 22 SBA 2 L 3 L CLKAB 23 CLKBA L 2 SAB 22 SBA H L H L H TRANSFER STORED DATA TO A AND/OR B Pin numbers shown are for DB, DW, JT, NT, and PW packages. Figure. Bus-Management Functions 2 2 POST OFFICE BO DALLAS, TEAS 75265

3 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 FUNCTION TABLE INPUTS DATA I/Os OPERATION OR FUNCTION CLKAB CLKBA SAB SBA A THRU A8 B THRU B8 Input Unspecified Store A, B unspecified Unspecified Input Store B, A unspecified H Input Input Store A and B data H H or L H or L Input disabled Input disabled Isolation, hold storage L L L Output Input Real-time B data to A bus L L H or L H Output Input Stored B data to A bus L H L Input Output Real-time A data to B bus L H H or L H Input Output Stored A data to B bus The data output functions may be enabled or disabled by various signals at the and inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs. logic symbol CLKBA SBA CLKAB SAB A A2 A3 A4 A5 A6 A7 A8 2 3 G3 3 EN [BA] 23 3 EN2 [AB] C4 22 G5 C6 2 G D B 5 6D B2 6 8 B3 7 7 B4 8 6 B5 9 5 B6 0 4 B7 3 B8 This symbol is in accordance with ANSI/IEEE Std and IEC Publication Pin numbers shown are for the DB, DW, JT, NT, and PW packages. POST OFFICE BO DALLAS, TEAS

4 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 logic diagram (positive logic) 2 CLKBA SBA CLKAB SAB One of Eight Channels D C A 4 D 20 B C Pin numbers shown are for the DB, DW, JT, NT, and PW packages. To Seven Other Channels 2 4 POST OFFICE BO DALLAS, TEAS 75265

5 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (except I/O ports) (see Note ) V to 7 V Voltage range applied to any output in the high state or power-off state, V O V to 5.5 V Current into any output in the low state, I O : SN54ABT ma SN74ABT ma Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0) ma Maximum power dissipation at T A = 55 C (in still air) (see Note 2): DB package W DW package W NT package W PW package W Storage temperature range C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 50 C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the 994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 3) SN54ABT646 SN74ABT646 UNIT MIN MA MIN MA VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V VI Input voltage 0 VCC 0 VCC V IOH High-level output current ma IOL Low-level output current ma t/ v Input transition rise or fall rate 5 5 ns / V TA Operating free-air temperature C NOTE 3: Unused or floating pins (input or I/O) must be held high or low. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BO DALLAS, TEAS

6 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25 C SN54ABT646 SN74ABT646 MIN TYP MA MIN MA MIN MA VIK VCC = 4.5 V, II = 8 ma V VOH VCC = 4.5 V, IOH = 3 ma VCC = 5 V, IOH = 3 ma VCC =45V 4.5 VOL VCC =45V 4.5 II IOH = 24 ma 2 2 IOH = 32 ma 2* 2 IOL = 48 ma IOL = 64 ma 0.55* 0.55 VCC = 5.5 V, Control inputs ± ± ± VI = VCC or GND A or B ports ±00 ±00 ±00 IOZH VCC = 5.5 V, VO = 2.7 V µa IOZL VCC = 5.5 V, VO = 0.5 V µa Ioff VCC = 0, VI or VO 4.5 V ±00 ±00 µa ICE VCC = 5.5 V, VO = 5.5 V Outputs high µa IO VCC = 5.5 V, VO = 2.5 V ma ICC VCC = V, IO = 0, VI =VCC or GND ICC # VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND UNIT Outputs high µa Outputs low ma Outputs disabled µa V V µa ma Ci VI = 2.5 V or 0.5 V Control inputs 7 pf Cio VO = 2.5 V or 0.5 V A or B ports 2 pf * On products compliant to MIL-STD-883, Class B, this parameter does not apply. All typical values are at VCC = 5 V. The parameters IOZH and IOZL include the input leakage current. This data sheet limit may vary among suppliers. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) VCC = 5 V, TA = 25 C SN54ABT646 SN74ABT646 MIN MA MIN MA MIN MA fclock Clock frequency MHz tw Pulse duration, CLK high or low ns tsu Setup time, A or B before CLKAB or CLKBA High Low th Hold time, A or B after CLKAB or CLKBA ns UNIT ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2 6 POST OFFICE BO DALLAS, TEAS 75265

7 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C L = 50 pf (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25 C SN54ABT646 SN74ABT646 MIN TYP MA MIN MA MIN MA fmax MHz tplh CLKBA or CLKAB A or B tphl tplh AorB BorA tphl tplh SAB or SBA BorA tphl tpzh AorB tpzl tphz AorB tplz tpzh AorB tpzl tphz AorB tplz These parameters are measured with the internal output state of the storage register opposite to that of the bus input. UNIT ns ns ns ns ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BO DALLAS, TEAS

8 SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 99 REVISED JULY 994 PARAMETER MEASUREMENT INFORMATION 7 V From Output Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S Open GND TEST tplh/tphl tplz/tpzl tphz/tpzh S Open 7 V Open LOAD CIRCUIT FOR OUTPUTS Timing Input.5 V 3 V 0 V Input tw.5 V.5 V 3 V 0 V Data Input tsu th.5 V.5 V 3 V 0 V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input (see Note B) Output Output tplh tphl.5 V.5 V.5 V.5 V tphl.5 V tplh.5 V 3 V 0 V VOH VOL VOH VOL Output Control Output Waveform S at 7 V (see Note C) Output Waveform 2 S at Open (see Note C) tpzl tpzh.5 V tplz.5 V tphz.5 V.5 V VOL V VOH 0.3 V 3 V 0 V 3.5 V VOL VOH 0 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. B. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR 0 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. C. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms 2 8 POST OFFICE BO DALLAS, TEAS 75265

9 PACKAGE OPTION ADDENDUM 28-May-2007 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) SN74ABT646DBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI SN74ABT646DBR ACTIVE SSOP DB Green (RoHS & SN74ABT646DBRE4 ACTIVE SSOP DB Green (RoHS & SN74ABT646DBRG4 ACTIVE SSOP DB Green (RoHS & SN74ABT646DGVR ACTIVE TVSOP DGV Green (RoHS & SN74ABT646DGVRE4 ACTIVE TVSOP DGV Green (RoHS & SN74ABT646DGVRG4 ACTIVE TVSOP DGV Green (RoHS & SN74ABT646DW ACTIVE SOIC DW Green (RoHS & SN74ABT646DWE4 ACTIVE SOIC DW Green (RoHS & SN74ABT646DWG4 ACTIVE SOIC DW Green (RoHS & SN74ABT646DWR ACTIVE SOIC DW Green (RoHS & SN74ABT646DWRE4 ACTIVE SOIC DW Green (RoHS & SN74ABT646DWRG4 ACTIVE SOIC DW Green (RoHS & SN74ABT646NT ACTIVE PDIP NT 24 5 Pb-Free (RoHS) SN74ABT646NTE4 ACTIVE PDIP NT 24 5 Pb-Free (RoHS) SN74ABT646PW ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWE4 ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWG4 ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWLE OBSOLETE TSSOP PW 24 TBD Call TI Call TI SN74ABT646PWR ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWRE4 ACTIVE TSSOP PW Green (RoHS & SN74ABT646PWRG4 ACTIVE TSSOP PW Green (RoHS & N / A for Pkg Type N / A for Pkg Type () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page

10 PACKAGE OPTION ADDENDUM 28-May-2007 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

11 PACKAGE MATERIALS INFORMATION 4-Oct-2007 TAPE AND REEL BO INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant SN74ABT646DBR DB 24 SITE Q SN74ABT646DGVR DGV 24 SITE Q SN74ABT646PWR PW 24 SITE Q Pack Materials-Page

12 PACKAGE MATERIALS INFORMATION 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74ABT646DBR DB 24 SITE SN74ABT646DGVR DGV 24 SITE SN74ABT646PWR PW 24 SITE Pack Materials-Page 2

13 MECHANICAL DATA MPDI004 OCTOBER 994 NT (R-PDIP-T**) 24 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE A DIM PINS ** A MA.260 (32,04).425 (36,20) (7,) (6,35) A MIN.230 (3,24).385 (35,8) B MA 0.30 (7,87) 0.35 (8,00) (,78) MA 2 B MIN (7,37) (7,49) (0,5) MIN B (5,08) MA Seating Plane 0.25 (3,8) MIN 0.02 (0,53) 0.05 (0,38) 0.00 (0,25) 0.00 (2,54) M 0.00 (0,25) NOM / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. POST OFFICE BO DALLAS, TEAS 75265

14 MECHANICAL DATA MPDS006C FEBRUARY 996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,3 0,07 M ,6 NOM 4,50 4,30 6,60 6,20 Gage Plane 2 A 0 8 0,25 0,75 0,50,20 MA 0,5 0,05 Seating Plane 0,08 DIM PINS ** A MA 3,70 3,70 5,0 5,0 7,90 9,80,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60, /E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,5 per side. D. Falls within JEDEC: 24/48 Pins MO-53 4/6/20/56 Pins MO-94 POST OFFICE BO DALLAS, TEAS 75265

15

16 MECHANICAL DATA MSSO002E JANUARY 995 REVISED DECEMBER 200 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,5 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane 4 0,25 A 0 8 0,95 0,55 2,00 MA 0,05 MIN Seating Plane 0,0 DIM PINS ** A MA 6,50 6,50 7,50 8,50 0,50 0,50 2,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 2, /E 2/0 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-50 POST OFFICE BO DALLAS, TEAS 75265

17 MECHANICAL DATA MTSS00C JANUARY 995 REVISED FEBRUARY 999 PW (R-PDSO-G**) 4 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,0 M 0, ,50 4,30 6,60 6,20 0,5 NOM Gage Plane A ,25 0,75 0,50,20 MA 0,5 0,05 Seating Plane 0,0 DIM PINS ** A MA 3,0 5,0 5,0 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 0/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53 POST OFFICE BO DALLAS, TEAS 75265

18 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 6949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security RFID Telephony Low Power Video & Imaging Wireless Wireless Mailing Address: Texas Instruments, Post Office Box , Dallas, Texas Copyright 2007, Texas Instruments Incorporated

SN54ALS05A, SN74ALS05A HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS

SN54ALS05A, SN74ALS05A HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS SN54ALS05A, SN74ALS05A HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS SDAS190A APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard

More information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE SN74CBT16214 12-BIT 1-OF-3 FET MULTIPLEXER/DEMULTIPLEXER SCDS008L MAY 1993 REVISED NOVEMBER 2001 Member of the Texas Instruments Widebus Family 5-Ω Switch Connection Between Two Ports TTL-Compatible Input

More information

SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 1991 REVISED JULY 1994

SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E JULY 1991 REVISED JULY 1994 State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 305; Exceeds 200 V Using Machine Model (C = 200 pf, R = 0) Latch-Up

More information

CD54AC08, CD74AC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES

CD54AC08, CD74AC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES CD54AC08, CD74AC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly

More information

SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS

SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS SN54ALS804A, SN54AS804B, SN74ALS804A, SN74AS804B HEX 2-INPUT NAND DRIVERS SDAS022C DECEMBER 1982 REVISED JANUARY 1995 High Capacitive-Drive Capability ALS804A Has Typical Delay Time of 4 ns (C L = 50 pf)

More information

54ACT16827, 74ACT BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

54ACT16827, 74ACT BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS Members of the Texas Instruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines Directly Flow-Through Architecture Optimizes PCB Layout Distributed V CC and Pin Configuration

More information

CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS

CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same-Frequency

More information

SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN54ACT573, SN74ACT573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS 4.5-V to 5.5-V V CC Operation Inputs Accept Voltages to 5.5 V Max t pd of 9.5 ns at 5 V Inputs Are TTL-Voltage Compatible description/ordering information These 8-bit latches feature 3-state outputs designed

More information

SN54ALS1035, SN74ALS1035 HEX NONINVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS

SN54ALS1035, SN74ALS1035 HEX NONINVERTING BUFFERS WITH OPEN-COLLECTOR OUTPUTS Noninverting Buffers With Open-Collector Outputs description These devices contain six independent noninverting buffers. They perform the Boolean function Y = A. The open-collector outputs require pullup

More information

SN74LVC2244ADWR OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS. description/ordering information

SN74LVC2244ADWR OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS. description/ordering information Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max t pd of 5.5 ns at 3.3 V Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Typical V OLP (Output

More information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE Operates From.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max t pd of 4.8 ns at 3.3 V Typical V OLP (Output Ground Bounce) 2

More information

1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE

1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE SN74CBTLV326 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS03H DECEMBER 997 REVISED APRIL 2003 Standard 26-Type Pinout 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions Latch-up Performance

More information

description/ordering information

description/ordering information SCDS040I DECEMBER 1997 REVISED OCTOBER 2003 5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports I off Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds

More information

SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D-Type Flip-Flops in a Single Package With 3-State Bus Driving True Outputs Full Parallel Access for Loading Buffered Control Inputs Package Options Include Plastic Small-Outline (DW) Packages, Ceramic

More information

ua9636ac DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE

ua9636ac DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE SLLSB OCTOBER 9 REVISED MAY 995 Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-3-B and -3-E and ITU Recommendations V. and V. Output Slew Rate Control Output Short-Circuit-Current Limiting

More information

74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and

More information

SN54HCT14, SN74HCT14 HEX SCHMITT-TRIGGER INVERTERS

SN54HCT14, SN74HCT14 HEX SCHMITT-TRIGGER INVERTERS SN54HCT14, SN74HCT14 HEX SCHMITT-TRIGGER INVERTERS SCLS225E JULY 1995 REVISED JULY 2003 Operating Voltage Range of 4.5 V to 5.5 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 20-µA Max

More information

74ACT11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

74ACT11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS 74ACT11245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCAS031C JULY 1987 REVISED APRIL 1996 3-State Outputs Drive Bus Lines Directly Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes

More information

TIB82S105BC FIELD-PROGRAMMABLE LOGIC SEQUENCER WITH 3-STATE OUTPUTS OR PRESET

TIB82S105BC FIELD-PROGRAMMABLE LOGIC SEQUENCER WITH 3-STATE OUTPUTS OR PRESET 50-MHz Clock Rate Power-On Preset of All Flip-Flops -Bit Internal State Register With -Bit Output Register Power Dissipation... 00 mw Typical Programmable Asynchronous Preset or Output Control Functionally

More information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry

More information

SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SN54ALS541, SN74ALS540, SN74ALS541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SDAS025D APRIL 1982 REVISED MARCH 2002 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs

More information

SN54HC541, SN74HC541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54HC541, SN74HC541 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max I CC Typical t pd = 10 ns ±6-mA Output Drive at

More information

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181E DECEMBER 1982 REVISED AUGUST 2003 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption,

More information

description/ordering information

description/ordering information Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input

More information

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline

More information

SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES

SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SDAS113B APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers

More information

The ULN2003AI has a 2.7-kΩ series base resistor for each Darlington pair for operation directly with TTL or 5-V CMOS devices. ORDERING INFORMATION

The ULN2003AI has a 2.7-kΩ series base resistor for each Darlington pair for operation directly with TTL or 5-V CMOS devices. ORDERING INFORMATION www.ti.com FEATURES 5-mA-Rated Collector Current (Single Output) High-Voltage Outputs... 5 V Output Clamp Diodes Inputs Compatible With Various Types of Logic Relay-Driver Applications DESCRIPTION/ORDERING

More information

MSP53C391, MSP53C392 SLAVE SPEECH SYNTHESIZERS

MSP53C391, MSP53C392 SLAVE SPEECH SYNTHESIZERS Slave Speech Synthesizers, LPC, MELP, CELP Two Channel FM Synthesis, PCM 8-Bit Microprocessor With 61 instructions 3.3V to 6.5V CMOS Technology for Low Power Dissipation Direct Speaker Drive Capability

More information

SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =

More information

CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES

CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES 4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and

More information

SN74ALVCH BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com FEATURES Member of the Texas Instruments Widebus Family Operates From 1.65 to 3.6 V Max t pd of 4.2 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External

More information

SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages,

More information

CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER

CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER 4.5-V to 5.5-V V CC Operation Input Latches for BCD Code Storage Blanking Capability Phase Input for Complementing s Fanout (Over Temperature Range) Standard s 10 LSTTL Loads Balanced Propagation Delay

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Member of the Texas Instruments Widebus Family Operates From 1.65 V to 3.6

More information

SN74AUC1G07 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT

SN74AUC1G07 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT www.ti.com FEATURES SN74AUC1G07 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT SCES373O SEPTEMBER 2001 REVISED FEBRUARY 2007 Available in the Texas Instruments Low Power Consumption, 10-µA Max I CC NanoFree

More information

SN74CB3Q BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH

SN74CB3Q BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH www.ti.com SN74CB3Q3257 4-BIT 1-OF-2 FET MULTIPLEXER/DEMULTIPLEXER 2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH SCDS135A SEPTEMBER 2003 REVISED MARCH 2005 FEATURES Data and Control Inputs Provide

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. 500-mA Rated Collector Current (Single Output) High-Voltage Outputs...50

More information

description/ordering information

description/ordering information Member of the Texas Instruments Widebus Family Max t pd of 5.8 ns at 3.3 ±24-mA Drive at 3.3 Latch-Up Performance Exceeds 250 ma Per JESD 17 description/ordering information This 16-bit (dual-octal) noninverting

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Inputs Are TTL-Voltage Compatible Latch-Up Performance Exceeds 250 ma Per

More information

OUTPUT INPUT ADJUSTMENT INPUT INPUT ADJUSTMENT INPUT

OUTPUT INPUT ADJUSTMENT INPUT INPUT ADJUSTMENT INPUT www.ti.com FEATURES LM237, LM337 3-TERMINAL ADJUSTABLE REGULATORS SLVS047I NOVEMBER 1981 REVISED OCTOBER 2006 Output Voltage Range Adjustable From Peak Output Current Constant Over 1.2 V to 37 V Temperature

More information

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Data sheet acquired from Harris Semiconductor SCHS189C January 1998 - Revised July 2004 High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State

More information

The ULN2003AI has a 2.7-kΩ series base resistor for each Darlington pair for operation directly with TTL or 5-V CMOS devices. ORDERING INFORMATION

The ULN2003AI has a 2.7-kΩ series base resistor for each Darlington pair for operation directly with TTL or 5-V CMOS devices. ORDERING INFORMATION 查询 ULN23AI 供应商 www.ti.com FEATURES 5-mA-Rated Collector Current (Single Output) High-Voltage Outputs... 5 V Output Clamp Diodes Inputs Compatible With Various Types of Logic Relay-Driver Applications DESCRIPTION/ORDERING

More information

SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =

More information

SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR

SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asynchronous Load for Modulo-N Count Lengths Asynchronous Clear Package Options Include Plastic Small-Outline (D)

More information

SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR ALS174 and AS174 Contain Six Flip-Flops With Single-Rail Outputs ALS175 and AS175B Contain Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct-Clear Inputs SN54ALS174, SN54ALS175, SN54AS174,

More information

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER

SN75160B OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER Meets IEEE Standard 488-978 (GPIB) 8-Channel Bidirectional Transceiver Power-Up/Power-Down Protection (Glitch Free) High-Speed, Low-Power Schottky Circuitry Low Power Dissipation...7 mw Max Per Channel

More information

74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS 74ACT62 Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching

More information

ORDERING INFORMATION TOP-SIDE

ORDERING INFORMATION TOP-SIDE SCES JULY Control Inputs V IH /V IL Levels are Referenced to V CCA Voltage V CC Isolation Feature If Either V CC Input Is at, Both Ports Are in the High-Impedance State Overvoltage-Tolerant Inputs/Outputs

More information

SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE

More information

SN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in

More information

SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SN54HC126, SN74HC126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SN54HC26, SN74HC26 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS03E MARCH 94 REVISED JULY 2003 Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Interface Directly With System

More information

SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995

SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995 Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance

More information

SN75176A DIFFERENTIAL BUS TRANSCEIVER

SN75176A DIFFERENTIAL BUS TRANSCEIVER SN7576A Bidirectional Transceiver Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-4-B and ITU Recommendation V. Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments

More information

SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 ma Per JEDEC Standard JESD-17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015;

More information

SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT)

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to 5.5-V V CC 3-State s Drive Bus Lines Directly Latch-Up

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. www.ti.com FEATURES SN74LVC8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH

More information

CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET s Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process

More information

SN54ABT273, SN74ABT273 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR

SN54ABT273, SN74ABT273 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 ma Per JEDEC Standard JESD-17 Typical V OLP (Output Ground Bounce) < 1 V at V CC = 5 V,

More information

2 C Accurate Digital Temperature Sensor with SPI Interface

2 C Accurate Digital Temperature Sensor with SPI Interface TMP125 2 C Accurate Digital Temperature Sensor with SPI Interface FEATURES DIGITAL OUTPUT: SPI-Compatible Interface RELUTION: 10-Bit, 0.25 C ACCURACY: ±2.0 C (max) from 25 C to +85 C ±2.5 C (max) from

More information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has

More information

SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS AUGUST 99 REVISED MAY 99 Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin

More information

54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture

More information

SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)

More information

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997

SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997 Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline

More information

SN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

SN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE Eight Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic

More information

ORDERING INFORMATION. 40 C to 85 C TSSOP DGG Tape and reel SN74LVCH16245ADGGR LVCH16245A TVSOP DGV Tape and reel SN74LVCH16245ADGVR LDH245A

ORDERING INFORMATION. 40 C to 85 C TSSOP DGG Tape and reel SN74LVCH16245ADGGR LVCH16245A TVSOP DGV Tape and reel SN74LVCH16245ADGVR LDH245A www.ti.com FEATURES Member of the Texas Instruments Widebus Family Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max t pd of 4 ns at 3.3 V Typical V OLP (Output Ground Bounce) < 0.8 V at

More information

SN54LV4052A, SN74LV4052A DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS

SN54LV4052A, SN74LV4052A DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS 2-V to 5.5-V V CC Operation Support Mixed-Mode Voltage Operation on All Ports Fast Switching High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Extremely Low Input Current Latch-Up Performance

More information

AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER

AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. www.ti.com FEATURES Operate From 1.65 V to 3.6 V Inputs Accept Voltages

More information

POSITIVE-VOLTAGE REGULATORS

POSITIVE-VOLTAGE REGULATORS www.ti.com FEATURES µa78m00 SERIES POSITIVE-VOLTAGE REGULATORS SLVS059P JUNE 1976 REVISED OCTOBER 2005 3-Terminal Regulators High Power-Dissipation Capability Output Current up to 500 ma Internal Short-Circuit

More information

SN54ABT373, SN74ABT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54ABT373, SN74ABT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 ma Per JEDEC Standard JESD-17 Typical V OLP (Output Ground Bounce) < 1 V at V CC = 5 V,

More information

SN54ABT273, SN74ABT273 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR

SN54ABT273, SN74ABT273 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly educes Power Dissipation Latch-Up Performance Exceeds 500 ma Per JEDEC Standard JESD-17 Typical V OLP (Output Ground Bounce) < 1 V at V CC = 5 V, T

More information

SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Optio Include Plastic Small-Outline

More information

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

More information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Bus Hold on Data

More information

SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS

SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS Typical V OLP ( Ground Bounce) 2 V at V CC = 3.3 V, T A = 25 C s Accept Voltages to 5.5 V Latch-Up Performance Exceeds 100 ma Per JESD

More information

SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR Contain Four Flip-Flops With Double-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline

More information

PRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description

PRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink

More information

description U/D RCO CLK A B C D ENT ENP GND LOAD CLK U/D V CC Q A Q B A B C D Q C Q D GND ENT RCO ENP LOAD

description U/D RCO CLK A B C D ENT ENP GND LOAD CLK U/D V CC Q A Q B A B C D Q C Q D GND ENT RCO ENP LOAD SDAS125B MARCH 1984 REVISED DECEMBER 1994 Fully Synchronous Operation for Counting and Programming Internal Carry Look-Ahead Circuitry for Fast Counting Carry Output for n-bit Cascading Fully Independent

More information

SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997

SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997 High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Bus-Structured Pinout Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and

More information

74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS 74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio

More information

CD74FCT843A BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

CD74FCT843A BiCMOS 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS BiCMOS Technology With Low Quiescent Power Buffered Inputs Noninverted Outputs Input/Output Isolation From V CC Controlled Output Edge Rates 48-mA Output Sink Current Output Voltage Swing Limited to 3.7

More information

SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS

SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SN54HC164, SN74HC164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS SCLS115D DECEMBER 1982 REVISED AUGUST 2003 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption,

More information

PAH PACKAGE (TOP VIEW) AGND FBIN AGND A VCC GND 3Y1 2Y3

PAH PACKAGE (TOP VIEW) AGND FBIN AGND A VCC GND 3Y1 2Y3 Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs Two Select Inputs Configure Up to Nine

More information

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR 2-V to 5.5-V V CC Operation Typical V OLP (Output Ground Bounce) 2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage

More information

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR Inputs Are TTL-Voltage Compatible Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators Latch-Up Performance Exceeds 250 ma Per JESD

More information

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators

More information

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. www.ti.com FEATURES SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS

More information

SN54LVC157A, SN74LVC157A QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS

SN54LVC157A, SN74LVC157A QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS www.ti.com SN54LVC157A, SN74LVC157A QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS SCAS292O JANUARY 1993 REVISED MAY 2005 FEATURES Typical V OHV (Output V OH Undershoot) Operate From 1.65 V to

More information

ORDERING INFORMATION SOT (SOT-23) DBV SOT (SC-70) DCK

ORDERING INFORMATION SOT (SOT-23) DBV SOT (SC-70) DCK www.ti.com FEATURES Available in the Texas Instruments NanoStar and NanoFree Packages Supports 5-V V CC Operation Inputs Accept Voltages to 5.5 V Max t pd of 4.1 ns at 3.3 V Low Power Consumption, 10-µA

More information

SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS Operating Range 2-V to 5.5-V V CC 3-State s Directly Drive Bus Lines Latch-Up Performance Exceeds 250 ma Per JESD 17 description The AHC573 devices are octal traparent D-type latches designed for 2-V to

More information

SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS

SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE

More information

CD74FCT541 BiCMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

CD74FCT541 BiCMOS OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS BiCMOS Technology With Low Quiescent Power Buffered Inputs Noninverted Outputs Input/Output Isolation From V CC Controlled Output Edge Rates 64-mA Output Sink Current Output Voltage Swing Limited to 3.7

More information

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels Designed to Be Used in Level-Shifting Applications description/ordering information The SN74CBTD3861 provides ten bits of high-speed

More information

description/ordering information

description/ordering information Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V CC ) Supports Unregulated Battery Operation Down to 2.7 V Typical V OLP (Output Ground Bounce)

More information

SN74CBT3861DWR 10-BIT FET BUS SWITCH. description. logic diagram (positive logic)

SN74CBT3861DWR 10-BIT FET BUS SWITCH. description. logic diagram (positive logic) SN74CBT3861 10-BIT FET BUS SWITCH SCDS061D APRIL 1998 REVISED OCTOBER 2000 5-Ω Switch Connection Between Two Ports TTL-Compatible Input Levels Latch-Up Performance Exceeds 250 ma Per JESD 17 description

More information

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995

SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995 3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

More information

54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS

54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS032A JUL 187 REVISED APRIL 13 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed

More information

description/ordering information

description/ordering information The SN74LS16 is obsolete and is no longer supplied. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Input Clamping Diodes Simplify System Design Open-Collector Driver for Indicator

More information