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2 FEATURES SN74LVC8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES584A JUNE 2005 REVISED AUGUST 2005 Control Inputs V IH /V IL Levels Are Referenced Latch-Up Performance Exceeds 100 ma Per to V CCA Voltage JESD 78, Class II V CC Isolation Feature If Either V CC Input Is at ESD Protection Exceeds JESD 22 GND, All Are in the High-Impedance State 4000-V Human-Body Model (A114-A) Fully Configurable Dual-Rail Design Allows 200-V Machine Model (A115-A) Each Port to Operate Over the Full 1.65-V to 1000-V Charged-Device Model (C101) 5.5-V Power-Supply Range DB, DBQ, DGV, OR PW PACKAGE (TOP VIEW) RHL PACKAGE (TOP VIEW) V CCA DIR A1 A2 A3 A4 A5 A6 A7 A8 GND GND V CCB V CCB OE B1 B2 B3 B4 B5 B6 B7 B8 GND DIR A1 A2 A3 A4 A5 A6 A7 A8 GND VCCA GND V GND CCB V CCB OE B1 B2 B3 B4 B5 B6 B7 B8 DESCRIPTION/ORDERING INFORMATION This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245 is optimized to operate with V CCA and V CCB set at 1.65 V to 5.5 V. The A port is designed to track V CCA. V CCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track V CCB. V CCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes. 40 C to 85 C ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING QFN RHL Tape and reel SN74LVC8T245RHLR NH245 SSOP DBR Tape and reel SN74LVC8T245DBR NH245 SSOP (QSOP) DBQ Tape and reel SN74LVC8T245DBQR NH245 TSSOP PW Tube Tape and reel SN74LVC8T245PW SN74LVC8T245PWR NH245 TVSOP DGV Tape and reel SN74LVC8T245DGVR NH245 (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2005, Texas Instruments Incorporated

3 SN74LVC8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES584A JUNE 2005 REVISED AUGUST DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74LVC8T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess I CC and I CCZ. The SN74LVC8T245 is designed so that the control pins (DIR and OE) are supplied by V CCA. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The V CC isolation feature ensures that if either V CC input is at GND, all outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. CONTROL INPUTS FUNCTION TABLE (1) (EACH 8-BIT SECTION) OUTPUT CIRCUITS OE DIR A PORT B PORT OPERATION L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation (1) Input circuits of the data I/Os are always active. LOGIC DIAGRAM (POSITIVE LOGIC) DIR 2 22 OE A B1 To Seven Other Channels 2

4 SN74LVC8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) SCES584A JUNE 2005 REVISED AUGUST 2005 MIN MAX UNIT V CCA Supply voltage range V V CCB I/O ports (A port) V I Input voltage range (2) I/O ports (B port) V V O Control inputs Voltage range applied to any output A port in the high-impedance or power-off state (2) B port A port 0.5 V CCA V O Voltage range applied to any output in the high or low state (2)(3) V B port 0.5 V CCB I IK Input clamp current V I < 0 50 ma I OK Output clamp current V O < 0 50 ma I O Continuous output current ±50 ma Continuous current through each V CCA, V CCB, and GND ±100 ma DB package 63 DBQ package 61 θ JA Package thermal impedance (4) DGV package 86 C/W PW package 88 RHL package 43 T stg Storage temperature range C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed. (4) The package thermal impedance is calculated in accordance with JESD V 3

5 SN74LVC8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES584A JUNE 2005 REVISED AUGUST 2005 Recommended Operating Conditions (1)(2)(3)(4) V CCI V CCO MIN MAX UNIT V CCA Supply voltage V CCB V to 1.95 V V CCI 0.65 High-level 2.3 V to 2.7 V 1.7 V IH Data inputs (5) V input voltage 3 V to 3.6 V V to 5.5 V V CCI V to 1.95 V V CCI 0.35 Low-level 2.3 V to 2.7 V 0.7 V IL Data inputs (5) V input voltage 3 V to 3.6 V 0.8 V IH V IL 4.5 V to 5.5 V V CCI V to 1.95 V V CCA 0.65 High-level Control inputs 2.3 V to 2.7 V 1.7 input voltage (referenced to V CCA ) (6) 3 V to 3.6 V V to 5.5 V V CCA V to 1.95 V V CCA 0.35 Low-level Control inputs 2.3 V to 2.7 V 0.7 input voltage (referenced to V CCA ) (6) 3 V to 3.6 V V to 5.5 V V CCA 0.3 V I Input voltage Control inputs V Input/output Active state 0 V CCO V V I/O voltage 3-State V 1.65 V to 1.95 V V to 2.7 V 8 I OH High-level output current ma 3 V to 3.6 V V to 5.5 V V to 1.95 V V to 2.7 V 8 I OL Low-level output current ma 3 V to 3.6 V V to 5.5 V V to 1.95 V 20 Input transition 2.3 V to 2.7 V 20 t/ v Data inputs ns/v rise or fall rate 3 V to 3.6 V V to 5.5 V 5 T A Operating free-air temperature C (1) V CCI is the V CC associated with the data input port. (2) V CCO is the V CC associated with the output port. (3) All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably V CCI or GND) to ensure proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. (4) All unused control inputs must be held at V CCA or GND to ensure proper device operation and minimize power comsumption. (5) For V CCI values not specified in the data sheet, V IH min = V CCI 0.7 V, V IL max = V CCI 0.3 V. (6) For V CCA values not specified in the data sheet, V IH min = V CCA 0.7 V, V IL max = V CCA 0.3 V. V V V 4

6 SN74LVC8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS Electrical Characteristics (1)(2) over recommended operating free-air temperature range (unless otherwise noted) SCES584A JUNE 2005 REVISED AUGUST 2005 PARAMETER TEST CONDITIONS V CCA V CCB MIN TYP MAX MIN MAX UNIT I OH = 100 µa, V I = V IH 1.65 V to 4.5 V 1.65 V to 4.5 V V CCO 0.1 I OH = 4 ma, V I = V IH 1.65 V 1.65 V 1.2 V OH I OH = 8 ma, V I = V IH 2.3 V 2.3 V 1.9 V I OH = 24 ma, V I = V IH 3 V 3 V 2.4 I OH = 32 ma, V I = V IH 4.5 V 4.5 V 3.8 I OL = 100 µa, V I = V IL 1.65 V to 4.5 V 1.65 V to 4.5 V 0.1 I OL = 4 ma, V I = V IL 1.65 V 1.65 V 0.45 V OL I OL = 8 ma, V I = V IL 2.3 V 2.3 V 0.3 V I OL = 24 ma, V I = V IL 3 V 3 V 0.55 I OL = 32 ma, V I = V IL 4.5 V 4.5 V 0.55 I I DIR V I = V CCA or GND 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 µa A or B 0 V 0 to 5.5 V ±1 ±2 I off V I or V O = 0 to 5.5 V µa port 0 to 5.5 V 0 V ±1 ±2 I OZ A or B port V O = V CCO or GND, OE = V IH 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 µa 1.65 V to 5.5 V 1.65 V to 5.5 V 15 I CCA V I = V CCI or GND, I O = 0 5 V 0 V 15 µa 0 V 5 V V to 5.5 V 1.65 V to 5.5 V 15 I CCB V I = V CCI or GND, I O = 0 5 V 0 V 2 µa 0 V 5 V 15 I CCA + I CCB V I = V CCI or GND, I O = V to 5.5 V 1.65 V to 5.5 V 25 µa A port One A port at V CCA 0.6 V, DIR at V CCA, B port = open 50 I CCA DIR at V CCA 0.6 V, 3 V to 5.5 V 3 V to 5.5 V µa DIR B port = open, 50 A port at V CCA or GND One B port at V CCB 0.6 V, I CCB B port 3 V to 5.5 V 3 V to 5.5 V 50 µa DIR at GND, A port = open Control C i V I = V CCA or GND 3.3 V 3.3 V 4 5 pf inputs A or B C io V O = V CCA/B or GND 3.3 V 3.3 V pf port (1) V CCO is the V CC associated with the output port. (2) V CCI is the V CC associated with the input port. 5

7 SN74LVC8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES584A JUNE 2005 REVISED AUGUST Switching Characteristics over recommended operating free-air temperature range, V CCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 1) PARAMETER V CCB = 1.8 V V CCB = 2.5 V V CCB = 3.3 V V CCB = 5 V FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX t PLH A B ns t PHL UNIT t PLH B A ns t PHL t PHZ OE A ns t PLZ t PHZ OE B ns t PLZ t PZH OE A ns t PZL t PZH OE B ns t PZL Switching Characteristics over recommended operating free-air temperature range, V CCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) V CCB = 1.8 V V CCB = 2.5 V V CCB = 3.3 V V CCB = 5 V FROM TO PARAMETER ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX UNIT t PLH A B ns t PHL t PLH B A ns t PHL t PHZ OE A ns t PLZ t PHZ OE B ns t PLZ t PZH OE A ns t PZL t PZH OE B ns t PZL 6

8 SN74LVC8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES584A JUNE 2005 REVISED AUGUST 2005 Switching Characteristics over recommended operating free-air temperature range, V CCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER V CCB = 1.8 V V CCB = 2.5 V V CCB = 3.3 V V CCB = 5 V FROM TO ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX t PLH A B ns t PHL UNIT t PLH B A ns t PHL t PHZ OE A ns t PLZ t PHZ OE B ns t PLZ t PZH OE A ns t PZL t PZH OE B ns t PZL Switching Characteristics over recommended operating free-air temperature range, V CCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) V CC = 1.8 V V CC = 2.5 V V CC = 3.3 V V CC = 5 V FROM TO PARAMETER ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX MIN MAX UNIT t PLH A B ns t PHL t PLH B A ns t PHL t PHZ OE A ns t PLZ t PHZ OE B ns t PLZ t PZH OE A ns t PZL t PZH OE B ns t PZL Operating Characteristics T A = 25 C C pda (1) C pdb (1) PARAMETER V CCA = V CCA = V CCA = V CCA = TEST V CCB = 1.8 V V CCB = 2.5 V V CCB = 3.3 V V CCB = 5 V CONDITIONS TYP TYP TYP TYP A-port input, B-port output B-port input, A-port output C L = 0, f = 10 MHz, A-port input, B-port output t r = t f = 1 ns B-port input, A-port output UNIT pf (1) Power dissipation capacitance per transceiver 7

9 SN74LVC8T245 8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS SCES584A JUNE 2005 REVISED AUGUST PARAMETER MEASUREMENT INFORMATION From Output Under Test C L (see Note A) R L R L S1 2 V CCO Open GND TEST t pd t PLZ /t PZL t PHZ /t PZH S1 Open 2 V CCO GND LOAD CIRCUIT t w V CCI Input V CCI /2 V CCI /2 V CCO C L R L V TP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pf 15 pf 15 pf 15 pf 2 kω 2 kω 2 kω 2 kω 0.15 V 0.15 V 0.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATION 0 V Output Control (low-level enabling) V CCA /2 V CCA /2 V CCA 0 V t PZL t PLZ Input Output t PLH V CCI /2 V CCI /2 t PHL V CCI 0 V V OH V CCO /2 V CCO /2 V OL Output Waveform 1 S1 at 2 V CCO (see Note B) Output Waveform 2 S1 at GND (see Note B) t PZH V CCO /2 V CCO /2 V OL + V TP t PHZ V OH V TP V CCO V OL V OH 0 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50 Ω, dv/dt 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. t PLZ and t PHZ are the same as t dis. F. t PZL and t PZH are the same as t en. G. t PLH and t PHL are the same as t pd. H. V CCI is the V CC associated with the input port. I. V CCO is the V CC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8

10 PACKAGE OPTION ADDENDUM 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type 74LVC8T245DBQRG4 ACTIVE SSOP/ QSOP Package Drawing Pins Package Qty DBQ Green (RoHS & 74LVC8T245RHLRG4 ACTIVE QFN RHL Green (RoHS & SN74LVC8T245DBQR ACTIVE SSOP/ QSOP DBQ Green (RoHS & SN74LVC8T245DBR ACTIVE SSOP DB Green (RoHS & SN74LVC8T245DBRE4 ACTIVE SSOP DB Green (RoHS & SN74LVC8T245DBRG4 ACTIVE SSOP DB Green (RoHS & SN74LVC8T245DGVR ACTIVE TVSOP DGV Green (RoHS & SN74LVC8T245DGVRG4 ACTIVE TVSOP DGV Green (RoHS & SN74LVC8T245DWR ACTIVE SOIC DW Green (RoHS & SN74LVC8T245DWRG4 ACTIVE SOIC DW Green (RoHS & SN74LVC8T245NSR ACTIVE SO NS Green (RoHS & SN74LVC8T245NSRG4 ACTIVE SO NS Green (RoHS & SN74LVC8T245PW ACTIVE TSSOP PW Green (RoHS & SN74LVC8T245PWE4 ACTIVE TSSOP PW Green (RoHS & SN74LVC8T245PWG4 ACTIVE TSSOP PW Green (RoHS & SN74LVC8T245PWR ACTIVE TSSOP PW Green (RoHS & SN74LVC8T245PWRE4 ACTIVE TSSOP PW Green (RoHS & SN74LVC8T245PWRG4 ACTIVE TSSOP PW Green (RoHS & SN74LVC8T245RHLR ACTIVE QFN RHL Green (RoHS & Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered Addendum-Page 1

11 PACKAGE OPTION ADDENDUM 4-Jun-2007 at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

12 PACKAGE MATERIALS INFORMATION 16-Jul-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1

13 PACKAGE MATERIALS INFORMATION 16-Jul-2007 Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74LVC8T245DBQR DBQ 24 MLA Q1 SN74LVC8T245DBR DB 24 MLA Q1 SN74LVC8T245DGVR DGV 24 MLA Q1 SN74LVC8T245DWR DW 24 TAI Q1 SN74LVC8T245NSR NS 24 MLA Q1 SN74LVC8T245PWR PW 24 MLA Q1 SN74LVC8T245RHLR RHL 24 MLA Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74LVC8T245DBQR DBQ 24 MLA SN74LVC8T245DBR DB 24 MLA SN74LVC8T245DGVR DGV 24 MLA SN74LVC8T245DWR DW 24 TAI SN74LVC8T245NSR NS 24 MLA SN74LVC8T245PWR PW 24 MLA SN74LVC8T245RHLR RHL 24 MLA Pack Materials-Page 2

14 PACKAGE MATERIALS INFORMATION 16-Jul-2007 Pack Materials-Page 3

15 MECHANICAL DATA MPDS006C FEBRUARY 1996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,13 0,07 M ,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 1 12 A 0 8 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,08 DIM PINS ** A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11, /E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins MO /16/20/56 Pins MO-194 POST OFFICE BOX DALLAS, TEXAS 75265

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22 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

23 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

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