CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574

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CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Data sheet acquired from Harris Semiconductor SCHS183C February 1998 - Revised May 2004 Features High-Speed CMOS Logic Octal D-Type Flip-Flop,

1 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Data sheet acquired from Harris Semiconductor SCHS183C February Revised May 2004 Features High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered Description [ /Title (CD74 HC374, CD74 HCT37 4, CD74 HC574, CD74 HCT57 Buffered Inputs Common Three-State Output Enable Control Three-State Outputs Bus Line Driving Capability Typical Propagation Delay (Clock to Q) = 15ns at = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2-V to 6-V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types V to 5.5-V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH The HC374, HCT374, HC574, and HCT574 are octal D-type flip-flops with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the LOW to HIGH transition of clock (CP). The output enable (OE) controls the 3-state outputs and is independent of the register operation. When OE is HIGH, the outputs are in the high-impedance state. The 374 and 574 are identical in function and differ only in their pinout arrangements. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC374F3A -55 to Ld CERDIP CD54HC574F3A -55 to Ld CERDIP CD54HCT374F3A -55 to Ld CERDIP CD54HCT574F3A -55 to Ld CERDIP CD74HC374E -55 to Ld PDIP CD74HC374M -55 to Ld SOIC CD74HC374M96-55 to Ld SOIC CD74HC574E -55 to Ld PDIP CD74HC574M -55 to Ld SOIC CD74HC574M96-55 to Ld SOIC CD74HCT374E -55 to Ld PDIP CD74HCT374M -55 to Ld SOIC CD74HCT374M96-55 to Ld SOIC CD74HCT574E -55 to Ld PDIP CD74HCT574M -55 to Ld SOIC CD74HCT574M96-55 to Ld SOIC CD74HCT574PWR -55 to Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2004, Texas Instruments Incorporated 1

2 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Pinouts CD54HC374, CD54HCT374 (CERDIP) CD74HC374, CD74HCT374 (PDIP, SOIC) TOP VIEW CD54HC574, CD54HCT574 (CERDIP) CD74HC574 (PDIP, SOIC) CD74HCT574 (PDIP, SOIC, TSSOP) TOP VIEW OE 1 20 OE 1 20 Q Q7 D Q0 D D7 D Q1 D D6 D Q2 Q Q6 D Q3 Q Q5 D Q4 D D5 D Q5 D D4 D Q6 Q Q4 D Q CP CP Functional Diagram D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP OE Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 TRUTH TABLE INPUTS OE CP Dn Qn L H H L L L L L X Q0 H X X Z H = High Level (Steady State) L = Low Level (Steady State) X= Don t Care = Transition from Low to High Level Q0= The level of Q before the indicated steady-state input conditions were established Z = High Impedance State 2

3 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Drain Current, per Output, I O For -0.5V < V O < + 0.5V ±35mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground Current, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 1) θ JA ( o C/W) E (PDIP) Package M (SOIC) Package PW (TSSOP) Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating, and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current SYMBOL TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V IH or V IL V V V UNITS V V V V OL V IH or V IL V V V I I or V V V ±0.1 - ±1 - ±1 µa 3

4 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 DC Electrical Specifications (Continued) PARAMETER Quiescent Device Current Three- State Leakage Current HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current Three- State Leakage Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load SYMBOL I CC V IL or V IH or V O = or V IH to 5.5 V IL to µa ±0.5 - ±5.0 - ±10 µa V V V OH V IH or V IL V V V OL V IH or V IL V I I I CC V IL or V IH I CC (Note 2) TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX and or V O = or V ±0.1 - ±1 - ±1 µa µa ±0.5 - ±5.0 - ±10 µa to 5.5 NOTE: 2. For dual-supply systems, theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table UNIT LOADS UNITS µa INPUT HCT374 HCT574 D0 - D CP OE NOTE: Unit Load is I CC limit specific in DC Electrical Specifications Table, e.g., 360µA max. at 25 o C. 4

5 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Prerequisite for Switching Specifications 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS HC TYPES Maximum Clock Frequency f MAX MHz MHz MHz Clock Pulse Width t W ns ns ns Setup Time Data to Clock t SU ns ns ns Hold Time Data to Clock t H ns ns ns HCT TYPES Maximum Clock Frequency f MAX MHz Clock Pulse Width t W ns Setup Time Data to Clock Hold Time Data to Clock t SU ns t H ns Switching Specifications C L = 50pF, Input t r, t f = 6ns PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay t PLH, t PHL C L = 50pF Clock to Output ns ns C L = 15pF ns C L = 50pF ns Output Disable to Q t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns 5

6 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Switching Specifications C L = 50pF, Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS Output Enable to Q t PZL,t PZH C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Maximum Clock Frequency f MAX C L = 15pF MHz Output Transition Time t THL, t TLH C L = 50pF ns ns ns Input Capacitance C I C L = 50pF pf Three-State Output Capacitance Power Dissipation Capacitance (Notes 3, 4) C O pf C PD C L = 15pF pf HCT TYPES Propagation Delay t PHL, t PLH Clock to Output C L = 50pF ns C L = 15pF ns Output Disable to Q t PLZ,t PHZ C L = 50pF ns C L = 15pF ns Output Enable to Q t PZL,t PZH C L = 50pF ns C L = 15pF ns Maximum Clock Frequency f MAX C L = 15pF MHz Output Transition Time t TLH, t THL C L = 50pF ns Input Capacitance C I C L = 50pF pf Three-State Output Capacitance Power Dissipation Capacitance (Notes 3, 4) C O pf C PD C L = 15pF pf NOTES: 3. C PD is used to determine the dynamic power consumption, per package. 4. P D =C PD V 2 CC fi + V 2 CC fo C L where f i = Input Frequency, f O = Output Frequency, C L = Output Load Capacitance, = Supply. 6

7 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Test Circuits and Waveforms t r C L CLOCK t f C L I t WL + t WH = fcl 50% 50% 50% t r C L = 6ns CLOCK t f C L = 6ns I t WL + t WH = fcl 3V 2.7V 0.3V 0.3V t WL t WH t WL t WH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT 50% INPUT 2.7V 0.3V 3V t THL t TLH t THL t TLH INVERTING t PHL t PLH 50% INVERTING t PHL t PLH FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC CLOCK INPUT t r C L t f C L 50% CLOCK INPUT t r C L 2.7V 0.3V t f C L 3V t H(H) t H(L) t H(H) t H(L) DATA INPUT t SU(H) t SU(L) 50% DATA INPUT t SU(H) t SU(L) 3V t TLH t THL 50% t TLH t THL t PLH t PHL t PLH t PHL t REM SET, RESET 50% OR PRESET t REM 3V SET, RESET OR PRESET IC C L 50pF IC C L 50pF FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7

8 CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Test Circuits and Waveforms (Continued) 6ns DISABLE 50% 6ns t r DISABLE 6ns t f ns 3V tplz t PZL t PLZ t PZL LOW TO OFF 50% LOW TO OFF HIGH TO OFF t PHZ t PZH 50% HIGH TO OFF t PHZ t PZH S ENABLED S DISABLED S ENABLED S ENABLED S DISABLED S ENABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 8. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW DISABLE IC WITH THREE- STATE R L = 1kΩ C L 50pF FOR t PLZ AND t PZL FOR t PHZ AND t PZH NOTE: Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is Output R L =1kΩ to, C L = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8

9 PACKAGE OPTION ADDENDUM 28-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HC374F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HC574F ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HC574F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HCT374F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HCT574F ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HCT574F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD74HC374E ACTIVE PDIP N Pb-Free CD74HC374M ACTIVE SOIC DW Pb-Free CD74HC374M96 ACTIVE SOIC DW Pb-Free CD74HC574E ACTIVE PDIP N Pb-Free CD74HC574M ACTIVE SOIC DW Pb-Free CD74HC574M96 ACTIVE SOIC DW Pb-Free CD74HCT374E ACTIVE PDIP N Pb-Free CD74HCT374M ACTIVE SOIC DW Pb-Free CD74HCT374M96 ACTIVE SOIC DW Pb-Free CD74HCT574E ACTIVE PDIP N Pb-Free CD74HCT574M ACTIVE SOIC DW Pb-Free CD74HCT574M96 ACTIVE SOIC DW Pb-Free CD74HCT574PWR ACTIVE TSSOP PW Pb-Free Level-NC-NC-NC Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-NC-NC-NC Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-1-250C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free : TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. Addendum-Page 1

10 PACKAGE OPTION ADDENDUM 28-Feb-2005 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

14 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

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16 This datasheet has been download from: Datasheets for electronics components.

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Data sheet acquired from Harris Semiconductor SCHS189C January 1998 - Revised July 2004 High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State