CD54HC4538, CD74HC4538, CD74HCT4538

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Data sheet acquired from Harris Semiconductor SCHS123 June 1998 CD54HC4538, CD74HC4538, CD74HCT4538 High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator Features Description [

1 Data sheet acquired from Harris Semiconductor SCHS123 June 1998 CD54HC4538, CD74HC4538, CD74HCT4538 High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator Features Description [ /Title (CD54 HC453 8, CD74 HC453 8, CD74 HCT45 38) /Subject (High Speed CMOS Logic Retriggerable/Resettable Capability Trigger and Reset Propagation Delays Independent of R X, C X Triggering from the Leading or Trailing Edge Q and Q Buffered Outputs Available Separate Resets Wide Range of Output-Pulse Widths Schmitt Trigger Input on A and B Inputs Retrigger Time is Independent of C X Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Pinout CD54HC4538, CD74HC4538, CD74HCT4538 (PDIP, SOIC, CERDIP) TOP VIEW 1C X 1R X C X 1R 1A 1B 1Q 1Q C X 14 2R X C X 13 2R 12 2A 11 2B 10 2Q 9 2Q The Harris CD54HC4538, CD74HC4538 and CD74HCT4538 are dual retriggerable/resettable monostable precision multivibrators for fixed voltage timing applications. An external resistor (R X ) and an external capacitor (C X ) control the timing and the accuracy for the circuit. Adjustment of R X and C X provides a wide range of output pulse widths from the Q and Q terminals. The propagation delay from trigger input-to-output transition and the propagation delay from reset input-to-output transition are independent of R X and C X. Leading-edge triggering (A) and trailing edge triggering (B) inputs are provided for triggering from either edge of the input pulse. An unused A input should be tied to and an unused B should be tied to. On power up the IC is reset. Unused resets and sections must be terminated. In normal operation the circuit retriggers on the application of each new trigger pulse. To operate in the non-triggerable mode Q is connected to B when leading edge triggering (A) is used or Q is connected to A when trailing edge triggering (B) is used. The period (τ) can be calculated from τ = (0.7) R X, C X ; R MIN is 5kΩ. C MIN is 0pF. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CD54HC4538F -55 to Ld CERDIP F16.3 CD74HC4538E -55 to Ld PDIP E16.3 CD74HCT4538E -55 to Ld PDIP E16.3 CD74HC4538M -55 to Ld SOIC M16.15 CD74HCT4538M -55 to Ld SOIC M16.15 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation File Number

2 Functional Diagram 1A 1B 1R 1Cx 1Rx 1 2 1Cx 1RxCx MONO Q 1Q 2R 13 2A Q 2B 11 MONO 2 9 2Q 2Cx 2RxCx = 8 = 16 2Cx 2Rx TRUTH TABLE INPUTS OUTPUTS R A B Q Q R1 R2 Q L X X L H X H X L H X X L L H H L H H D p n p n p n Q R1 NOTE: H = High Level, L = Low Level, = Transition from Low to High, = Transition from High to Low, One High Level Pulse, One Low Level Pulse, X = Irrelevant. FIGURE 1. FF DETAIL 2

3 16 R X 2(14) R1 + COMP II 6(10) C X 1(15) - Q R2 8 7(9) HIGH Z Q 3(13) R 4(12) A 5(11) D R1 R2 FF Q Q B FIGURE 2. LOGIC DIAGRAM (1 MONO) FUNCTIONAL TERMINAL CONNECTIONS TO TERMINAL NUMBER TO TERMINAL NUMBER INPUT PULSE TO TERMINAL NUMBER OTHER CONNECTIONS FUNCTION Leading-Edge Trigger/Retriggerable Leading-Edge Trigger/Non-Retriggerable Trailing-Edge Trigger/Retriggerable Trailing-Edge Trigger/Non-Retriggerable MONO 1 MONO 2 MONO 1 MONO 2 MONO 1 MONO 2 MONO 1 MONO 2 3, 5 11, NOTES: 3. A retriggerable one-shot multivibrator has an output pulse width which is extended one full time period (T) after application of the last trigger pulse. 4. A non-triggerable one-shot multivibrator has a time period (T) referenced from the application of the first trigger pulse. FIGURE 3. INPUT PULSE TRAIN FIGURE 4. RETRIGGERABLE MODE PULSE WIDTH (A MODE) T T FIGURE 5. NON-RETRIGGERABLE MODE PULSE WIDTH (A MODE) 3

4 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground Current, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 7) θ JA ( o C/W) θ J C ( o C/W) PDIP Package N/A SOIC Package N/A CERDIP Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, (Note 5) HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Times, t r, t f Reset Input: 2V ns (Max) 4.5V ns (Max) 6V ns (Max) Trigger Inputs A or B: 2V Unlimited (Max) 4.5V Unlimited (Max) 6V Unlimited (Max) External Timing Resistor, R X (Note 6) kΩ (Min) External Timing Capacitor, C X (Note 6) (Min) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 5. Unless otherwise specified, all voltages are referenced to ground. 6. The maximum allowable values of R X and C X are a function of leakage of capacitor C X, the leakage of the HC4538, and leakage due to board layout and surface resistance. Values of R X and C X should be chosen so that the maximum current into pin 2 or pin 14 is 30mA. Susceptibility to externally induced noise signals may occur for R X > 1MΩ. 7. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads SYMBOL TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o CTO125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V UNITS V V V IL V V V V OH V IH or V IL V V V V V V 4

5 DC Electrical Specifications (Continued) Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current A, B, R Input Leakage Current R X C X (Note 9) Quiescent Device Current Active Device Current Q = High & Pins 2, 14 at /4 HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Input Leakage Current R X C X (Note 9) Quiescent Device Current Active Device Current Q = High & Pins 2, 14 at /4 Additional Quiescent Device Current Per Input Pin: 1 Unit Load NOTES: PARAMETER SYMBOL V OL V IH or V IL V I I I CC I CC or or or V IH to 5.5 V IL to V V V V V ±0.1 - ±1 - ±1 µa ± ±0.5 - ±0.5 µa µa ma V V V OH V IH or V IL V V V OL V IH or V IL V I I I CC I CC I CC (Note 8) TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o CTO125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX and or or V ±0.1 - ±1 - ±1 µa ± ±0.5 - ±0.5 µa µa ma to For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA µa 9. When testing I IL the Q output must be high. If Q is low (device not triggered) the pull-up P device will be ON and the low resistance path from V DD to the test pin will cause a current far exceeding the specification. UNITS 5

6 HCT Input Loading Table INPUT UNIT LOADS All 0.5 NOTE: Unit Load is I CC limit specified in DC Electrical Table, e.g. 360µA max at 25 o C. Prerequisite for Switching Specifications 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL (V) HC TYPES MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Input Pulse Widths t WH, t WL A, B ns ns ns R t WL ns ns ns Reset Recovery Time t REC ns ns ns Retrigger Time (Figure 11) t rr ns HCT TYPES Input Pulse Widths t WH, t WL A, B ns R t WL ns Reset Recovery Time t REC ns Retrigger Time (Figure 11) t rr ns 6

7 Switching Specifications C L = 50pF, Input t r, t f = 6ns, R X = 10KΩ, C X = 0 PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay t PLH C L = 50pF A, B to Q ns ns C L = 15pF ns C L = 50pF ns A, B to Q t PHL C L = 50pF ns ns C L = 15pF ns C L = 50pF ns R to Q t PHL C L = 50pF ns ns C L = 15pF ns C L = 50pF ns R to Q t PLH C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Output Transition Time t TLH, t THL C L = 50pF ns ns ns Output Pulse Width R X = 10k, C X = 0.1µF τ C L = 50pF ms ms Output Pulse Width Match, Same Package ± % Power Dissipation Capacitance C PD C L = 15pF pf Input Capacitance C I C L = 50pF pf HCT TYPES Propagation Delay t PLH A, B to Q C L = 50pF ns C L = 15pF ns A, B to Q t PHL C L = 50pF ns C L = 15pF ns R to Q t PHL C L = 50pF ns C L = 15pF ns 7

8 Switching Specifications C L = 50pF, Input t r, t f = 6ns, R X = 10KΩ, C X = 0 (Continued) PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS R to Q t PLH C L = 50pF ns C L = 15pF ns Output Transition Time t TLH, t THL C L = 50pF ns Output Pulse Width R X = 10k, C X = 0.1µF τ C L = 50pF ms Output Pulse Width Match, Same Package ± % Power Dissipation Capacitance C PD C L = 15pF pf Input Capacitance C I C L = 50pF pf NOTES: 10. C PD is used to determine the dynamic power consumption, per one shot. 11. P D =(C PD +C X )V 2 CC fi (C L V 2 CC fo ) where f i = input frequency, f O = output frequency, C L = output load capacitance, C X = external capacitance = supply voltage assuming f i «I - τ Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT 90% 50% 10% INPUT 2.7V 1.3V 0.3V 3V t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH 90% 50% 10% INVERTING OUTPUT t PHL t PLH 90% 1.3V 10% FIGURE 6. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 8

9 Typical Performance Curves CD54HC4538, CD74HC4538, CD74HCT HC TA11646C T A = 25 o C 0.70 HCT TA13646C T A = 25 o C 10kΩ, 10nF K FACTOR kΩ, 100nF 100kΩ, 100nF 100kΩ, 10nF K FACTOR kΩ, 10nF 10kΩ, 100nF 100kΩ, 100nF 100kΩ, 10nF , DC SUPPLY VOLTAGE (V), DC SUPPLY VOLTAGE (V) FIGURE 8. K FACTOR vs DC SUPPLY VOLTAGE ( ) - V FIGURE 9. K FACTOR vs DC SUPPLY VOLTAGE ( ) - V K FACTOR HC/HCT4538 = 5V, T A = 25 o C 2kΩ 10kΩ 100kΩ t rr, TYP MIN RETRIGGER TIME (ns) = 4.5V = 5V T A = 25 o C R X = 10kΩ C X, TIMING CAPACITANCE (pf) C X, TIMING CAPACITANCE (pf) FIGURE 10. K FACTOR vs C X FIGURE 11. MINIMUM RETRIGGER TIME vs TIMING CAPACITANCE 9

10 Power-Down Mode During a rapid power-down condition, as would occur with a power-supply short circuit with a poorly filtered power supply, the energy stored in C X could discharge into Pin 2 or 14. To aviod possible device damage in this mode, when C X is 0.5µF, a protection diode with a 1 ampere or higher rating (1N5395 or equivalent) and a separate ground return for C X should be provided as shown in Figure 12. An alternate protection method is shown in Figure 13, where a51ωcurrent-limiting resistor is inserted in series with C X. Note that a small pulse width decrease will occur however, and R X must be appropriately increased to obtain the originally desired pulse width. IN5395 OR EQUIVALENT R X 2(14) 16 R X 2(14) 16 C X 0.5µF + 1(15) 8 51Ω C X 0.5µF 1(15) 8 FIGURE 12. RAPID POWER-DOWN PROTECTION CIRCUIT FIGURE 13. ALTERNATE RAPID POWER-DOWN PROTECTION CIRCUIT 10

11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated

12 This datasheet has been downloaded from: Datasheets for electronic components.

13 Texas Instruments This file is the datasheet for the following electronic components: 74HC

CD74HC123, CD74HCT123, CD74HC423, CD74HCT423

CD74HC123, CD74HCT123, CD74HC423, CD74HCT423 Data sheet acquired from Harris Semiconductor SCHS1 September 1997 CD7HC13, CD7HCT13, CD7HC3, CD7HCT3 High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets Features Description