CD74AC86, CD54/74ACT86

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Data sheet acquired from Harris Semiconductor SCHSA September 998 - Revised May 000 CD7AC86, CD/7ACT86 Quad -Input Exclusive-OR Gate [ /Title (CD7 AC86, CD7 ACT86 ) /Subject Quad -Input xclu- ive- R

1 Data sheet acquired from Harris Semiconductor SCHSA September Revised May 000 CD7AC86, CD/7ACT86 Quad -Input Exclusive-OR Gate [ /Title (CD7 AC86, CD7 ACT86 ) /Subject Quad -Input xclu- ive- R ate) /Autho () /Keyords Haris emionuctor, dvan ed MOS Harris emionuctor, dvan ed TL) /Cretor () /DOCI FO df- Features Buffered Inputs Typical Propagation Delay -.ns at = V, T A = o C, C L = 0pF Exceeds kv ESD Protection MIL-STD-88, Method 0 SCR-Latchup-Resistant CMOS Process and Circuit Design Speed of Bipolar FAST /AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays AC Types Feature.V to.v Operation and Balanced Noise Immunity at 0% of the Supply ±ma Output Drive Current - Fanout to FAST ICs - Drives 0Ω Transmission Lines Pinout A B CDACT86 (CERDIP) CD7AC86, CD7ACT86 (PDIP, SOIC) TOP VIEW Y A B Y B A Y B A Y Description The CD7AC86 and ACT86 are quad -input Exclusive-OR gates that utilize Advanced CMOS Logic technology Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD7AC86E 0 to 70 o C, -0 to 8, - to Ld PDIP CD7AC86M 0 to 70 o C, -0 to 8, - to Functional Diagram Ld SOIC CDACT86FA - to Ld CERDIP CD7ACT86E 0 to 70 o C, -0 to 8, Ld PDIP - to CD7ACT86M 0 to 70 o C, -0 to 8, - to Ld SOIC. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. A B Y A B Y 6 7 TRUTH TABLE INPUTS na nb ny L L L H H L H L H L H H B A Y B A Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST is a Trademark of Fairchild Semiconductor. Copyright 000, Texas Instruments Incorporated

2 CD7AC86, CD/7ACT86 Absolute Maximum Ratings DC Supply Voltage, V to 6V DC Input Diode Current, I IK For V I < -0.V or V I > + 0.V ±0mA DC Output Diode Current, I OK For V O < -0.V or V O > + 0.V ±0mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.V or V O < + 0.V ±0mA DC or Ground Current, I CC or I (Note ) ±00mA Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) PDIP Package SOIC Package Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 0 o C Maximum Lead Temperature (Soldering 0s) o C Operating Conditions Temperature Range, T A o C to o C Supply Voltage Range, (Note ) V to.v DC Input or Output Voltage, V I, V O V to Input Rise and Fall Slew Rate, dt/dv.v to.v ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.. For up to outputs per device, add ±ma for each additional output.. Unless otherwise specified, all voltages are referenced to ground.. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS o C -0 o C TO 8 o C - o C TO o C PARAMETER SYMBOL V I (V) I O (ma) (V) MIN MAX MIN MAX MIN MAX AC TYPES High Level Input Voltage V IH V V V Low Level Input Voltage V IL V V V High Level Output Voltage V OH V IH or V IL V V V V V V V Low Level Output Voltage V OL V IH or V IL V V V V V V V

3 CD7AC86, CD/7ACT86 DC Electrical Specifications (Continued) PARAMETER Input Leakage Current I I or Quiescent Supply Current, FF ACT TYPES I CC or -. - ±0. - ± - ± µa µa High Level Input Voltage V IH - -. to V. Low Level Input Voltage V IL - -. to V. High Level Output Voltage V OH V IH or V IL V V V V Low Level Output Voltage V OL V IH or V IL V V V V Input Leakage Current I I or -. - ±0. - ± - ± µa Quiescent Supply Current, FF Additional Supply Current per Input Pin TTL Inputs High Unit Load I CC I CC or µa -. to ma 6. Test one output at a time for a -second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 0Ω transmission-line-drive capability at 8 o C, 7Ω at o C. ACT Input Load Table SYMBOL TEST CONDITIONS o C -0 o C TO 8 o C - o C TO o C V I (V) I O (ma) (V) MIN MAX MIN MAX MIN MAX INPUT UNIT LOAD All 0.8 NOTE: Unit load is I CC limit specified in DC Electrical Specifications Table, e.g.,.ma max at o C. Switching Specifications Input t r, t f = ns, C L = 0pF (Worst Case) -0 o C TO 8 o C - o C TO o C AC TYPES PARAMETER SYMBOL (V) MIN TYP MAX MIN TYP MAX Propagation Delay, Input to Output t PHL, t PLH ns. (Note 9) ns (Note 0) ns

4 CD7AC86, CD/7ACT86 Switching Specifications Input t r, t f = ns, C L = 0pF (Worst Case) (Continued) -0 o C TO 8 o C - o C TO o C PARAMETER SYMBOL (V) MIN TYP MAX MIN TYP MAX Input Capacitance C I pf Power Dissipation Capacitance ACT TYPES C PD (Note ) pf Propagation Delay, Input to Output t PHL, t PLH (Note 0) ns Input Capacitance C I pf Power Dissipation Capacitance C PD (Note ) pf 8. Limits tested at 00%. 9..V Min at.6v, Max at V. 0. V Min at.v, Max at.v.. C PD is used to determine the dynamic power consumption per gate. AC: P D = V CC f i (C PD + C L ) ACT: P D = V CC f i (C PD + C L ) + I CC where f i = input frequency, C L = output load capacitance, = supply voltage. R L (NOTE) 00Ω DUT na OR nb t r = ns t f = ns 90% V S 0% LOAD C L 0pF NOTE: For AC Series Only: When =.V, R L = kω. ny t PLH t PHL V S AC ACT Input Level V Input Switching Voltage, V S 0..V FIGURE. Output Switching Voltage, V S FIGURE. PROPAGATION DELAY TIMES

5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 000, Texas Instruments Incorporated

CD54/74AC245, CD54/74ACT245

CD54/74AC245, CD54/74ACT245 Data sheet acquired from Harris Semiconductor SCHS245B September 1998 - Revised October 2000 Octal-Bus Transceiver, Three-State, Non-Inverting Features Description [ /Title