CD54/74AC245, CD54/74ACT245

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CD54/74AC245, CD54/74ACT245 Data sheet acquired from Harris Semiconductor SCHS245B September 1998 - Revised October 2000 Octal-Bus Transceiver, Three-State, Non-Inverting Features Description [

1 CD54/74AC245, CD54/74ACT245 Data sheet acquired from Harris Semiconductor SCHS245B September Revised October 2000 Octal-Bus Transceiver, Three-State, Non-Inverting Features Description [ /Title (CD74 AC245, CD74 ACT24 5) /Subject (Octal- Bus Transceiver, Three- State, Non- Inverting) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS, Harris Semicon- Buffered Inputs Typical Propagation Delay - 4ns at V CC = 5V, T A =, C L = 50pF Exceeds 2kV ESD Protection per MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process and Circuit Design Speed of Bipolar FAST /AS/S with Significantly Reduced Power Consumption Balanced Propagation Delays AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply ±24mA Output Drive Current - Fanout to 15 FAST ICs - Drives 50Ω Transmission Lines Pinout CD54AC245, CD54ACT245 (CERDIP) CD74AC245, CD74ACT245 (PDIP, SOIC, SSOP) TOP VIEW DIR A0 A1 A2 A3 A4 A5 A6 A The AC245 and ACT245 are octal-bus transceivers that utilize Advanced CMOS Logic technology. They are noninverting three-state bidirectional transceiver-buffers intended for two-way transmission from A bus to B bus or B bus to A. The logic level present on the direction input (DIR) determines the data direction. When the output enable input (OE) is HIGH, the outputs are in the high-impedance state. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54AC245F3A -55 to Ld CERDIP CD74AC245E -55 to Ld PDIP CD74AC245M -55 to Ld SOIC CD74AC245SM -55 to Ld SSOP CD54ACT245F3A -55 to Ld CERDIP CD74ACT245E -55 to Ld PDIP CD74ACT245M -55 to Ld SOIC CD74ACT245SM -55 to Ld SSOP 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information V CC OE 18 B0 17 B1 16 B B3 B4 B5 12 B6 11 B7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST is a Trademark of Fairchild Semiconductor. 1 Copyright 2000, Texas Instruments Incorporated

2 Functional Diagram A B0 A B1 A B2 A B3 A B4 A B5 A B6 A B7 DIR OE 1 19 CONTROL INPUTS TRUTH TABLE OE DIR OPERATION L L B Data to A Bus L H A Data to B Bus H X Isolation H = High Level, L = Low Level, X = Irrelevant To prevent excess currents in the High-Z (isolation) modes, all I/O terminals should be terminated with 10kΩ to 1MΩ resistors. 2

3 Absolute Maximum Ratings DC Supply Voltage, V CC V to 6V DC Input Diode Current, I IK For V I < -0.5V or V I > V CC + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > V CC + 0.5V ±50mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < V CC + 0.5V ±50mA DC V CC or Ground Current, I CC or I (Note 3) ±100mA Thermal Information Thermal Resistance (Typical, Note 5) θ JA ( o C/W) E Package M Package SM Package Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C Operating Conditions Temperature Range, T A o C to 1 Supply Voltage Range, V CC (Note 4) AC Types V to 5.5V ACT Types V to 5.5V DC Input or Output Voltage, V I, V O V to V CC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V ns (Max) AC Types, 3.6V to 5.5V ns (Max) ACT Types, 4.5V to 5.5V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 3. For up to 4 outputs per device, add ±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications TEST CONDITIONS V CC -40 o C TO 85 o C -55 o C TO 1 PARAMETER SYMBOL V I (V) I O (ma) (V) MIN MAX MIN MAX MIN MAX UNITS AC TYPES High Level Input Voltage V IH V V V Low Level Input Voltage V IL V V V High Level Output Voltage V OH V IH or V IL V V V V V V V 3

4 DC Electrical Specifications (Continued) PARAMETER Low Level Output Voltage V OL V IH or V IL V V V V V V Input Leakage Current I I V CC or Three-State Leakage Current Quiescent Supply Current MSI I OZ I CC V IH or V IL V O =V CC or V CC or 50 ACT TYPES High Level Input Voltage V IH to 5.5 Low Level Input Voltage V IL to V ±0.1 - ±1 - ±1 µa ±0.5 - ±5 - ±10 µa µa V V High Level Output Voltage V OH V IH or V IL V V V V Low Level Output Voltage V OL V IH or V IL V V V Input Leakage Current I I V CC or Three-State or Leakage Current Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load SYMBOL I OZ I CC I CC TEST CONDITIONS V CC -40 o C TO 85 o C -55 o C TO 1 V I (V) I O (ma) (V) MIN MAX MIN MAX MIN MAX V IH or V IL V O =V CC or V CC or V CC V ±0.1 - ±1 - ±1 µa ±0.5 - ±5 - ±10 µa µa to ma 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85 o C, 75Ω at 1. UNITS 4

5 ACT Input Load Table INPUT UNIT LOAD An, Bn 0.83 OE 0.64 DIR 0.25 NOTE: Unit load is I CC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at. Switching Specifications Input t r, t f = 3ns, C L = 50pF (Worst Case) -40 o C TO 85 o C -55 o C TO 1 AC TYPES PARAMETER SYMBOL V CC (V) MIN TYP MAX MIN TYP MAX UNITS Data to Output t PLH, t PHL ns 3.3 (Note 9) ns 5 (Note 10) ns Output Disable to Output t PLZ, t PHZ ns ns ns Output Enable to Output t PZL, t PZH ns ns ns Minimum (Valley) V OH During Switching of Other Outputs (Output Under Test Not Switching) V OHV See Figure at at - V Maximum (Peak) V OL During Switching of Other Outputs (Output Under Test Not Switching) V OLP See Figure at at - V Three-State Output Capacitance C O pf Input Capacitance C I pf Power Dissipation Capacitance ACT TYPES C PD (Note 11) pf Data to Output t PLH, t PHL 5 (Note 10) ns Output Disable to Output Output Enable to Output t PLZ, t PHZ ns t PZL, t PZH ns Minimum (Valley) V OH During Switching of Other Outputs (Output Under Test Not Switching) V OHV See Figure at at - V Maximum (Peak) V OL During Switching of Other Outputs (Output Under Test Not Switching) V OLP See Figure at at - V 5

6 Switching Specifications Input t r, t f = 3ns, C L = 50pF (Worst Case) (Continued) -40 o C TO 85 o C -55 o C TO 1 PARAMETER SYMBOL V CC (V) MIN TYP MAX MIN TYP MAX UNITS Three-State Output Capacitance C O pf Input Capacitance C I pf Power Dissipation Capacitance C PD (Note 11) pf 8. Limits tested 100% V Min is at 3.6V, Max is at 3V V Min is at 5.5V, Max is at 4.5V. 11. C PD is used to determine the dynamic power consumption per channel. AC: P D = V 2 CC f i (C PD + C L ) ACT: P D = V 2 CC f i (C PD + C L ) + V CC I CC where f i = input frequency, C L = output load capacitance, V CC = supply voltage. OTHER S V OH V OL UNDER TEST V OH V OHV V OLP V OL 12. Input pulses have the following characteristics: PRR 1MHz, t r = 3ns, SKEW 1ns. 13. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and probes require 700MHz bandwidth. FIGURE 1. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS 6

7 S DISABLED t f = 3ns t PLZ t r = 3ns t PZL INPUT LEVEL 90% 10% : LOW TO OFF TO LOW 0.2 V CC VOL ( V CC ) t PHZ t PZH : HIGH TO OFF TO HIGH S ENABLED S DISABLED 0.8 V CC S ENABLED OTHER INPUTS TIED HIGH OR LOW DISABLE DUT WITH THREE- STATE C L 50pF R L 500Ω (t PHZ, t PZH ) OPEN (t PHL, t PLH ) 2 V CC (t PLZ, t PZL ) (OPEN DRAIN) OUT R L 500Ω (NOTE 14) NOTE: 14. For AC Series only: When V CC = 1.5V, R L = 1kΩ. FIGURE 2. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT t r = 3ns t f = 3ns INPUT LEVEL An Bn t PLH 90% 10% t PHL FIGURE 3. PROPAGATION DELAY TIMES R L (NOTE) 500Ω DUT LOAD C L 50pF NOTE: For AC Series Only: When V CC = 1.5V, R L = 1kΩ. AC ACT Input Level V CC 3V Input Switching Voltage, 0.5 V CC 1.5V Output Switching Voltage, 0.5 V CC 0.5 V CC FIGURE 4. PROPAGATION DELAY TIMES 7

8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated

CD74AC86, CD54/74ACT86

CD74AC86, CD54/74ACT86 Data sheet acquired from Harris Semiconductor SCHSA September 998 - Revised May 000 CD7AC86, CD/7ACT86 Quad -Input Exclusive-OR Gate [ /Title (CD7 AC86, CD7 ACT86 ) /Subject Quad -Input xclu- ive- R ate)