CD74HC73, CD74HCT73. Dual J-K Flip-Flop with Reset Negative-Edge Trigger. Features. Description. Ordering Information. Pinout

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Data sheet acquired from Harris Semiconductor SCHS134 February 1998 CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC73, CD74 HCT73 ) /Subject Dual -K liplop

1 Data sheet acquired from Harris Semiconductor SCHS134 February 1998 CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC73, CD74 HCT73 ) /Subject Dual -K liplop Features Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times Asynchronous Reset Complementary Outputs Buffered Inputs Typical f MAX = 60MHz at = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Description The Harris CD74HC73 and CD74HCT73 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These flip-flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric limits. The 74HCT logic family is functionally as well as pin compatible with the standard 74LS logic family. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CD74HC73E -55 to Ld PDIP E14.3 CD74HCT73E -55 to Ld PDIP E14.3 CD74HC73M -55 to Ld SOIC M14.15 NOTES: 6. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 7. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout CD74HC73, CD74HCT73 (PDIP, SOIC) TOP VIEW 1CP J 1R Q 1K Q CP K 2R 6 9 2Q 2J 7 8 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation File Number

2 Functional Diagram 1J 1K 1CP FF Q 13 1Q 1R 2 2J 2K 2CP FF Q 2Q 2R 6 = 11 = 4 TRUTH TABLE S OUTPUTS R CP J K Q Q L X X X L H H L L No Change H H L H L H L H L H H H H Toggle H H X X No Change NOTE: H =High Level (Steady State) L =Low Level (Steady State) X = Irrelevant = High-to-Low Transition Logic Diagram J K 14 (7) 3(10) J K 12 (9) Q CP 1 (5) na CL CL R 13 (8) Q R 2 (6) 2

3 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Drain Current, per Output, I O For -0.5V < V O < + 0.5V ±25mA DC Output Diode Current, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground Current, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 3) θ JA ( o C/W) PDIP Package SOIC Package Maximum Junction Temperature (Hermetic Package or Die) o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range (T A ) o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 8. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications HC TYPES V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX High Level Input V IH V V V Low Level Input V IL V V High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads V OH V OL V V IH or V V IL V V V V V V IH or V V IL V V V V V Input Leakage Current I I or ±0.1 - ±1 - ±1 µa 3

4 DC Electrical Specifications (Continued) Quiescent Device Current HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load I CC or V IH to 5.5 V IL to 5.5 V OH V OL I I I CC I CC V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX µa V V V IH or V V IL V V IH or V V IL and or V ±0.1 - ±1 - ±1 µa µa to 5.5 NOTE: 9. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA µa HCT Input Loading Table UNIT LOADS All 0.3 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25 o C. Prerequisite For Switching Specifications HC TYPES HCT TYPES Input Level V S NOTE: Transition times and propagation delay times. (V) MIN TYP MAX MIN MAX MIN MAX HC TYPES CP Pulse Width t w -C L = 50pF ns ns ns R Pulse Width t w -C L = 50pF ns ns ns 4

5 Prerequisite For Switching Specifications (Continued) (V) MIN TYP MAX MIN MAX MIN MAX Setup Time, J, K to CP t SU C L = 50pF ns ns ns Hold Time, J, K to CP t H C L = 50pF ns ns ns Removal Time t REM -C L = 50pF ns ns ns CP Frequency f MAX C L = 50pF MHz MHz C L = 15pF MHz C L = 50pF MHz HCT TYPES CP Pulse Width t w C L = 50pF ns R Pulse Width t w CL = 50pF ns Setup Time, J, K to CP t SU CL = 50pF ns Hold Time, J, K to CP t H CL = 50pF ns Removal Time t REM CL = 50pF ns CP Frequency f MAX CL = 50pF MHz CL = 15pF MHz Switching Specifications Input t r, t f = 6ns HC TYPES CP to Q CP to Q (V) MIN TYP MAX MIN MAX MIN MAX t PLH, t PHL C L = 50pF ns ns CL = 15pF ns C L = 50pF ns t PLH, t PHL C L = 50pF ns ns C L = 15pF ns C L = 50pF ns t PLH, t PHL C L = 50pF ns R to Q, Q ns C L = 15pF ns C L = 50pF ns Output Transition Time t TLH, t THL C L = 50pF ns ns ns 5

6 Switching Specifications Input t r, t f = 6ns (Continued) Input Capacitance C I pf Power Dissipation Capacitance C PD pf (Notes 5, 6) HCT TYPES CP to Q CP to Q R to Q, Q (V) MIN TYP MAX MIN MAX MIN MAX t PLH, t PHL C L = 50pF ns t PLH, t PHL CL = 50pF ns t PLH, t PHL CL = 50pF ns Output Transition Time t TLH, t THL C L = 50pF ns Input Capacitance C I pf Power Dissipation Capacitance (Notes 5, 6) C PD pf NOTES: 10. C PD is used to determine the dynamic power consumption, per flip-flop. 11. P D =C PD V 2 CC fi + Σ C L V 2 CC fo where f i = input frequency, f o = output frequency, C L = output load capacitance, = supply voltage. Test Circuits and Waveforms t r C L CLOCK t f C L I t WL + t WH = fcl t r C L = 6ns CLOCK t f C L = 6ns I t WL + t WH = fcl 2.7V t WL t WH t WL t WH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH t r = 6ns t f = 6ns t r = 6ns t f = 6ns 2.7V 0. t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH INVERTING OUTPUT t PHL t PLH FIGURE 4. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6

7 Test Circuits and Waveforms (Continued) CLOCK t r C L t f C L CLOCK t r C L 2.7V 0. t f C L t H(H) t H(L) t H(H) t H(L) DATA t SU(H) t SU(L) DATA t SU(H) t SU(L) OUTPUT t TLH t THL OUTPUT t TLH t THL t PLH t PHL t PLH t PHL t REM SET, RESET OR PRESET t REM SET, RESET OR PRESET IC C L 50pF IC C L 50pF FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7

8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated

CD54/74HC74, CD54/74HCT74

CD54/74HC74, CD54/74HCT74 Data sheet acquired from Harris Semiconductor SCHS124A January 1998 - Revised May 2000 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger Features Description [ /Title