CD54/74HC297, CD74HCT297

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C5/7HC297, C7HCT297 ata sheet acquired from Harris Semiconductor SCHS177A November 1997 - evised May 2000 High-Speed CMOS Logic igital Phase-Locked-Loop [ /Title (C7 HC297, C7 HCT29 7) /Subject

1 C5/7HC297, C7HCT297 ata sheet acquired from Harris Semiconductor SCHS177A November evised May 2000 High-Speed CMOS Logic igital Phase-Locked-Loop [ /Title (C7 HC297, C7 HCT29 7) /Subject Highpeed MOS ogic igial haseocked Features igital esign Avoids Analog Compensation Errors Easily Cascadable for Higher Order Loops Useful Frequency ange - K-Clock C to 55MHz (Typ) - I/-Clock C to 35MHz (Typ) ynamically Variable Bandwidth Very Narrow Bandwidth Attainable Power-On eset Output Capability - Standard XOP OUT, ECP OUT - Bus river I/ OUT Fanout (Over Temperature ange) - Standard Outputs LSTTL Loads - Bus river Outputs LSTTL Loads Balanced Propagation elay and Transition Times Significant Power eduction Compared to LSTTL Logic ICs HC297 Types - Operation to 6V - High Noise Immunity N IL = 30%, N IH = 30% of V CC at 5V C7HCT297 Types - Operation to 5.5V - irect LSTTL Input Logic Compatibility V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility I I 1µA at V OL, V OH Pinout C5HC297 (CEIP) C7HC297, C7HCT29 (PIP) TOP VIEW B A EN CT /U I/ OUT GN V CC 15 C 1 13 φa 2 12 ECP OUT 11 XOP OUT 10 φb 9 φa 1 escription The HC297 and C7HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL). These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-n counter, to build first-order phase-locked-loops. Both EXCLUSIVE-O (XOP) and edge-controlled phase detectors (ECP) are provided for maximum flexibility. The input signals for the EXCLUSIVE-O phase detector must have a 50% duty factor to obtain the maximum lock-range. Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops. The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and all LOW, the K-counter is disabled. With A HIGH and B, C and LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. eal-time control of loop bandwidth by manipulating the A to inputs can maximize the overall performance of the digital phase-locked-loop. The HC297 and C7HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (PLL) is not affected by V CC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays. Ordering Information PAT NUMBE TEMP. ANGE ( o C) PACKAGE C5HC297F3A -55 to Ld CEIP C7HC297E -55 to Ld PIP C7HCT297E -55 to Ld PIP NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2000, Texas Instruments Incorporated 1

2 C5/7HC297, C7HCT297 The phase detector generates an error signal waveform that, at zero phase error, is a 50% duty factor square wave. At the limits of linear operation, the phase detector output will be either HIGH or LOW all of the time depending on the direction of the phase error (φin - φout). Within these limits the phase detector output varies linearly with the input phase error according to the gain K d, which is expressed in terms of phase detector output per cycle or phase error. The phase detector output can be defined to vary between ±1 according to the relation: phase detector output = %HIGH - %LOW The output of the phase detector will be K d φ e, where the phase error φ e = φin - φout. EXCLUSIVE-O phase detectors (XOP) and edge-controlled phase detectors (ECP) are commonly used digital types. The ECP is more complex than the XOP logic function but can be described generally as a circuit that changes states on one of the transitions of its inputs. The gain (K d ) for an XOP is because its output remains HIGH (XOP OUT = 1) for a phase error of one quarter cycle. Similarly, K d for the ECP is 2 since its output remains HIGH for a phase error of one half cycle. The type of phase detector will determine the zero-phase-error point, i.e., the phase separation of the phase detector inputs for a φe defined to be zero. For the basic PLL system of Figure 3, φe = 0 when the phase detector output is a square wave. The XOP inputs are one quarter cycle out-of-phase for zero phase error. For the ECP, φe = 0 when the inputs are one half cycle out of phase. The phase detector output controls the up/down input to the K-counter. The counter is clocked by input frequency Mf c which is a multiple M of the loop center frequency f c. When the K-counter recycles up, it generates a carry pulse. ecycling while counting down generates a borrow pulse. If the carry and the borrow outputs are conceptually combined into one output that is positive for a carry and negative for a borrow, and if the K-counter is considered as a frequency divider with the ratio Mf c /K, the output of the K-counter will equal the input frequency multiplied by the division ratio. Thus the output from the K-counter is (K d φ e Mf c )/K. The carry and borrow pulses go to the increment/decrement (I/) circuit which, in the absence of any carry or borrow pulses has an output that is one half of the input clock ( ). The input clock is just a multiple, 2N, of the loop center frequency. In response to a carry of borrow pulse, the I/ circuit will either add or delete a pulse at I/ OUT. Thus the output of the I/ circuit will be Nf c + (K d φ e Mf c )/2K. The output of the N-counter (or the output of the phaselocked-loop) is thus: f o = f c + (K d φ e Mf c )/2KN. If this result is compared to the equation for a first-order analog phase-locked-loop, the digital equivalent of the gain of the VCO is just Mf c /2KN or f c /K for M = 2N. Thus, the simple first-order phase-locked-loop with an adjustable K-counter is the equivalent of an analog phase-lockedloop with a programmable VCO gain. Functional iagram /U EN CT φa 1 φb φa C B A MOULO-K COUNTE CAY BOOW I/ CKT J F/F K FUNCTION TABLE EXCLUSIVE-O PHASE ETECTO φa 1 φb XOP OUT L L L L H H H L H H H L FUNCTION TABLE EGE-CONTOLLE PHASE ETECTO φa 2 φb ECP OUT H or L H H or L L H or L No Change H or L No Change H = Steady-State High Level, L = Steady-State Low Level, = LOW to HIGH φ Transition, = HIGH to LOW φ Transition K-COUNTE FUNCTION TABLE (IGITAL CONTOL) C B A MOULO (K) L L L L Inhibited L L L H 2 3 L L H L 2 L L H H 2 5 L H L L 2 6 L H L H 2 7 L H H L 2 8 L H H H 2 9 H L L L 2 10 H L L H 2 11 H L H L 2 12 H L H H 2 13 H H L L 2 1 H H L H 2 15 H H H L 2 16 H H H H I/ OUT 11 XOP OUT 12 ECP OUT 2

3 C5/7HC297, C7HCT297 Absolute Maximum atings C Supply, V CC V to 7V C Input iode Current, I IK For V I < -0.5V or V I > V CC + 0.5V ±20mA C Output iode Current, I OK For V O < -0.5V or V O > V CC + 0.5V ±20mA C rain Current, per Output, I O For -0.5V < V O < V CC + 0.5V ±25mA C Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < V CC + 0.5V ±25mA C V CC or Ground Current, I CC ±50mA Thermal Information Thermal esistance (Typical, Note 2) θ JA ( o C/W) PIP Package Maximum Junction Temperature o C Maximum Storage Temperature ange o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C Operating Conditions Temperature ange, T A o C to 125 o C Supply ange, V CC HC Types V to 6V HCT Types V to 5.5V C Input or Output, V I, V O V to V CC Input ise and Fall Time 2V ns (Max).5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum atings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θ JA is measured with the component mounted on an evaluation PC board in free air. C Electrical Specifications TEST CONITIONS 25 o C -0 o C TO 85 o C -55 o C TO 125 o C PAAMETE HC TYPES SYMBOL V I (V) I O (ma) V CC (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input V IH V V V Low Level Input V IL V V High Level Output CMOS Loads V OH V V IH or V V IL V V High Level Output TTL Loads -6 (Note ) -7.8 (Note ) V V Low Level Output CMOS Loads V OL V IH or V V IL V V Low Level Output TTL Loads (Note ) 5.2 (Note ) V V 3

4 C5/7HC297, C7HCT297 C Electrical Specifications (Continued) PAAMETE Input Leakage Current uiescent evice Current HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current uiescent evice Current Additional uiescent evice Current Per Input Pin: 1 Unit Load (Note 3) SYMBOL I I I CC V CC or GN V CC or GN V IH to 5.5 V IL to 5.5 V OH V OL I I I CC I CC TEST CONITIONS 25 o C -0 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) V CC (V) MIN TYP MAX MIN MAX MIN MAX ±0.1 - ±1 - ±1 µa µa V V V IH or V V IL V V IH or V V IL V CC to GN V CC or GN V CC V ±0.1 - ±1 - ±1 µa µa -.5 to 5.5 NOTE:. For dual-supply systems theoretical worst case (V I = 2.V, V CC = 5.5V) specification is 1.8mA. 5. XOP, ECP UNITS µa HCT Input Loading Table INPUT UNIT LOAS EN CT, /U 0.3 A, B, C,,, φa 2 0.6, φa 1, φb 1.5 NOTE: Unit Load is I CC limit specified in C Electrical Specifications table, e.g., 360µA max at 25 o C.

5 C5/7HC297, C7HCT297 Prerequisite For Switching Function 25 o C -0 o C TO 85 o C -55 o C TO 125 o C PAAMETE SYMBOL V CC (V) MIN MAX MIN MAX MIN MAX UNITS HC TYPES Maximum Clock Frequency f MAX MHz MHz MHz Maximum Clock Frequency f MAX MHz MHz MHz Clock Pulse Width t w ns ns ns Clock Pulse Width t W ns ns ns Set-up Time t SU ns /U, EN CT to ns ns Hold Time t H ns /U, EN CT to ns ns HCT TYPES Maximum Clock Frequency f MAX MHz Maximum Clock Frequency f MAX MHz Clock Pulse Width t w ns Clock Pulse Width t w ns Set-up Time t SU ns /U, EN CT to Hold Time t H ns /U, EN CT to Switching Specifications Input t r, t f = 6ns PAAMETE SYMBOL TEST CONITIONS V CC (V) 25 o C -0 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX UNITS HC TYPES Propagation elay, t PLH, t PHL C L = 50pF ns to I/ OUT ns ns 5

6 C5/7HC297, C7HCT297 Switching Specifications Input t r, t f = 6ns (Continued) PAAMETE SYMBOL TEST CONITIONS V CC (V) 25 o C -0 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX UNITS Propagation elay, t PLH, t PHL C L = 50pF ns φa 1, φb to XOP OUT ns ns Propagation elay, t PHL, t PHL C L = 50pF ns φb, φa 2 to ECP OUT ns ns Output Transition Time XOP OUT ECP OUT t TLH C L = 50pF ns ns ns Output Transition Time t TLH C L = 50pF ns I/ OUT ns ns Input Capacitance C I pf HCT TYPES Propagation elay, t PLH, t PHL C L = 50pF ns to I/ OUT Propagation elay, t PLH, t PHL C L = 50pF ns φa 1, φb to XOP OUT Propagation elay, t PHL, t PHL C L = 50pF ns φb, φa 2 to ECP OUT Output Transition Time t TLH C L = 50pF ns XOP OUT Output Transition Time t TLH C L = 50pF ns ECP OUT Input Capacitance C I pf 6

7 C5/7HC297, C7HCT297 Logic iagram A B C MOULO-K COUNTE CONTOL CICUIT TO MOE CONTOLS 12-2 (11 STAGES NOT SHOWN) /U 6 1 M 13 M 1 M EN CT 3 POWE ON ESET M 1 M T FF13 M 1 1 = 1 1 BOOW CAY 5 INCEMENT/ECEMENT CICUIT 7 I/ OUT J K φa φb EXCLUSIVE-O PHASE ETECTO 11 XOP OUT 13 φa 2 S FF S FF EGE-CONTOLLE PHASE ETECTO 12 ECP OUT 7

8 C5/7HC297, C7HCT297 Mf C CAY /U EN CT IVIE-BY-K COUNTE BOOW XOP OUT φa 1 f OUT φ OUT φb I/ CICUIT 2Nf C ECP OUT J J f IN φ IN φa 2 ECP K FF I/ OUT IVIE-BY-N COUNTE FIGUE 1. PLL USING BOTH PHASE ETECTOS IN A IPPLE-CANCELLATION SCHEME Mf C CAY /U IVIE-BY-K COUNTE BOOW f OUT φ IN XOP OUT φa 1 φb I/ CICUIT 2Nf C I/ OUT f OUT φ OUT IVIE-BY-N COUNTE FIGUE 2. PLL USING EXCLUSIVE-O PHASE ETECTION CAY PULSE (INTENAL SIGNAL) BOOW PULSE (INTENAL SIGNAL) INPUT I/ OUT OUTPUT FIGUE 3. TIMING IAGAM: I/ OUT IN-LOCK CONITION 8

9 C5/7HC297, C7HCT297 øb INPUT øa 2 INPUT ECP OUT OUTPUT FIGUE. TIMING IAGAM: EGE CONTOLLE PHASE COMPAATO WAVEFOMS øb INPUT øa 1 INPUT XOP OUT OUTPUT FIGUE 5. TIMING IAGAM: EXCLUSIVE O PHASE ETECTO WAVEFOMS t W I/f MAX t PLH I/ OUT t PHL t TLH t THL FIGUE 6. WAVEFOMS SHOWING THE CLOCK ( ) TO OUTPUT (I/ OUT ) POPAGATION ELAYS, CLOCK PULSE WITH, OUTPUT TANSITION TIMES AN MAXIMUM CLOCK PULSE FEUENCY øb INPUT øa 1 INPUT XOP OUT OUTPUT t PLH t PLH t TLH t PLH t THL t PHL FIGUE 7. WAVEFOMS SHOWING THE PHASE INPUT (øb, øa 1 ) TO OUTPUT (XOP OUT ) POPAGATION ELAYS AN OUTPUT TANSITION TIMES 9

10 C5/7HC297, C7HCT297 øb INPUT øa 2 INPUT ECP OUT OUTPUT t PHL t PLH t TLH t THL FIGUE 8. WAVEFOMS SHOWING THE PHASE INPUT (øb, øa 2 ) TO OUTPUT (ECP OUT ) POPAGATION ELAYS AN OUTPUT TANSITION TIMES t H t H /U, EN CT INPUT t SU t SU INPUT t W 1/f MAX NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. FIGUE 9. WAVEFOMS SHOWING THE CLOCK ( ) PULSE WITH AN MAXIMUM CLOCK PULSE FEUENCY, AN THE INPUT (/U, EN CT ) TO CLOCK ( ) SETUP AN HOL TIMES 10

11 IMPOTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated

CD54HC297, CD74HC297, CD74HCT297

CD54HC297, CD74HC297, CD74HCT297 C54HC297, C74HC297, C74HCT297 ata sheet acquired from Harris Semiconductor SCHS177B November 1997 - Revised May 2003 High-Speed CMOS Logic igital Phase-Locked Loop [ /Title (C74 HC297, C74 HCT29 7) /Subject