CD54HC297, CD74HC297, CD74HCT297

Transcription

1 C54HC297, C74HC297, C74HCT297 ata sheet acquired from Harris Semiconductor SCHS177B November Revised May 2003 High-Speed CMOS Logic igital Phase-Locked Loop [ /Title (C74 HC297, C74 HCT29 7) /Subject (High- Speed CMOS Logic igital Phase- Locked Features igital esign Avoids Analog Compensation Errors Easily Cascadable for Higher Order Loops Useful Frequency Range - K-Clock C to 55MHz (Typ) - I/-Clock C to 35MHz (Typ) ynamically Variable Bandwidth Very Narrow Bandwidth Attainable Power-On Reset Output Capability - Standard XORP OUT, ECP OUT - Bus river I/ OUT Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus river Outputs LSTTL Loads Balanced Propagation elay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC297 Types - Operation to 6V - High Noise Immunity N IL = 30%, N IH = 30% of V CC at 5V C74HCT297 Types - Operation to 5.5V - irect LSTTL Input Logic Compatibility V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility I I 1µA at V OL, V OH Pinout C54HC297 (CERIP) C74HC297, C74HCT29 (PIP) TOP VIEW B A EN CTR I/ CP /U I/ OUT GN V CC 15 C φa 2 12 ECP OUT 11 XORP OUT 10 φb 9 φa 1 escription The HC297 and C74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL). These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-n counter, to build first-order phase-locked-loops. Both EXCLUSIVE-OR (XORP) and edge-controlled phase detectors (ECP) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range. Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops. The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and all LOW, the K-counter is disabled. With A HIGH and B, C and LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to inputs can maximize the overall performance of the digital phase-locked-loop. The HC297 and C74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (PLL) is not affected by V CC and temperature variations but depends solely on accuracies of the K-clock and loop propagation delays. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE C54HC297F3A -55 to Ld CERIP C74HC297E -55 to Ld PIP C74HCT297E -55 to Ld PIP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2003, Texas Instruments Incorporated 1

2 C54HC297, C74HC297, C74HCT297 The phase detector generates an error signal waveform that, at zero phase error, is a 50% duty factor square wave. At the limits of linear operation, the phase detector output will be either HIGH or LOW all of the time depending on the direction of the phase error (φin - φout). Within these limits the phase detector output varies linearly with the input phase error according to the gain K d, which is expressed in terms of phase detector output per cycle or phase error. The phase detector output can be defined to vary between ±1 according to the relation: phase detector output = %HIGH - %LOW The output of the phase detector will be K d φ e, where the phase error φ e = φin - φout. EXCLUSIVE-OR phase detectors (XORP) and edge-controlled phase detectors (ECP) are commonly used digital types. The ECP is more complex than the XORP logic function but can be described generally as a circuit that changes states on one of the transitions of its inputs. The gain (K d ) for an XORP is 4 because its output remains HIGH (XORP OUT = 1) for a phase error of one quarter cycle. Similarly, K d for the ECP is 2 since its output remains HIGH for a phase error of one half cycle. The type of phase detector will determine the zero-phase-error point, i.e., the phase separation of the phase detector inputs for a φe defined to be zero. For the basic PLL system of Figure 3, φe = 0 when the phase detector output is a square wave. The XORP inputs are one quarter cycle out-of-phase for zero phase error. For the ECP, φe = 0 when the inputs are one half cycle out of phase. The phase detector output controls the up/down input to the K-counter. The counter is clocked by input frequency Mf c which is a multiple M of the loop center frequency f c. When the K-counter recycles up, it generates a carry pulse. Recycling while counting down generates a borrow pulse. If the carry and the borrow outputs are conceptually combined into one output that is positive for a carry and negative for a borrow, and if the K-counter is considered as a frequency divider with the ratio Mf c /K, the output of the K-counter will equal the input frequency multiplied by the division ratio. Thus the output from the K-counter is (K d φ e Mf c )/K. The carry and borrow pulses go to the increment/decrement (I/) circuit which, in the absence of any carry or borrow pulses has an output that is one half of the input clock (I/ CP ). The input clock is just a multiple, 2N, of the loop center frequency. In response to a carry of borrow pulse, the I/ circuit will either add or delete a pulse at I/ OUT. Thus the output of the I/ circuit will be Nf c + (K d φ e Mf c )/2K. The output of the N-counter (or the output of the phaselocked-loop) is thus: f o = f c + (K d φ e Mf c )/2KN. If this result is compared to the equation for a first-order analog phase-locked-loop, the digital equivalent of the gain of the VCO is just Mf c /2KN or f c /K for M = 2N. Thus, the simple first-order phase-locked-loop with an adjustable K-counter is the equivalent of an analog phase-lockedloop with a programmable VCO gain. Functional iagram /U EN CTR I/ CP φa 1 φb φa C B A MOULO-K COUNTER CARRY BORROW I/ CKT J F/F K FUNCTION TABLE EXCLUSIVE-OR PHASE ETECTOR φa 1 φb XORP OUT L L L L H H H L H H H L FUNCTION TABLE EGE-CONTROLLE PHASE ETECTOR φa 2 φb ECP OUT H or L H H or L L H or L No Change H or L No Change H = Steady-State High Level, L = Steady-State Low Level, = LOW to HIGH φ Transition, = HIGH to LOW φ Transition K-COUNTER FUNCTION TABLE (IGITAL CONTROL) C B A MOULO (K) L L L L Inhibited L L L H 2 3 L L H L 2 4 L L H H 2 5 L H L L 2 6 L H L H 2 7 L H H L 2 8 L H H H 2 9 H L L L 2 10 H L L H 2 11 H L H L 2 12 H L H H 2 13 H H L L 2 14 H H L H 2 15 H H H L 2 16 H H H H I/ OUT 11 XORP OUT 12 ECP OUT 2

3 C54HC297, C74HC297, C74HCT297 Absolute Maximum Ratings C Supply, V CC V to 7V C Input iode Current, I IK For V I < -0.5V or V I > V CC + 0.5V ±20mA C Output iode Current, I OK For V O < -0.5V or V O > V CC + 0.5V ±20mA C rain Current, per Output, I O For -0.5V < V O < V CC + 0.5V ±25mA C Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < V CC + 0.5V ±25mA C V CC or Ground Current, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 1) θ JA ( o C/W) E (PIP) Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, V CC HC Types V to 6V HCT Types V to 5.5V C Input or Output, V I, V O V to V CC Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JES C Electrical Specifications TEST CONITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER HC TYPES SYMBOL V I (V) I O (ma) V CC (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input V IH V V V Low Level Input V IL V V High Level Output CMOS Loads V OH V V IH or V V IL V V High Level Output TTL Loads -6 (Note 2) -7.8 (Note 2) V V Low Level Output CMOS Loads V OL V IH or V V IL V V Low Level Output TTL Loads 4 (Note 2) 5.2 (Note 2) V V 3

4 C54HC297, C74HC297, C74HCT297 C Electrical Specifications (Continued) PARAMETER Input Leakage Current uiescent evice Current HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current uiescent evice Current Additional uiescent evice Current Per Input Pin: 1 Unit Load SYMBOL I I I CC V CC or GN V CC or GN V IH to 5.5 V IL to 5.5 V OH V OL I I I CC I CC (Note 2) TEST CONITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) V CC (V) MIN TYP MAX MIN MAX MIN MAX ±0.1 - ±1 - ±1 µa µa V V V IH or V V IL V V IH or V V IL V CC to GN V CC or GN V CC V ±0.1 - ±1 - ±1 µa µa to 5.5 NOTE: 2. For dual-supply systems theoretical worst case (V I = 2.4V, V CC = 5.5V) specification is 1.8mA. UNITS µa HCT Input Loading Table INPUT UNIT LOAS EN CTR, /U 0.3 A, B, C,,, φa I/ CP, φa 1, φb 1.5 NOTE: Unit Load is I CC limit specified in C Electrical Specifications table, e.g., 360µA max at 25 o C. 4

5 C54HC297, C74HC297, C74HCT297 Prerequisite For Switching Function 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL V CC (V) MIN MAX MIN MAX MIN MAX UNITS HC TYPES Maximum Clock Frequency f MAX MHz MHz MHz Maximum Clock Frequency f MAX MHz I/ CP MHz MHz Clock Pulse Width t w ns ns ns Clock Pulse Width t W ns I/ CP ns ns Set-up Time t SU ns /U, EN CTR to ns ns Hold Time t H ns /U, EN CTR to ns ns HCT TYPES Maximum Clock Frequency f MAX MHz Maximum Clock Frequency f MAX MHz I/ CP Clock Pulse Width t w ns Clock Pulse Width t w ns I/ CP Set-up Time t SU ns /U, EN CTR to Hold Time t H ns /U, EN CTR to Switching Specifications Input t r, t f = 6ns PARAMETER SYMBOL TEST CONITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX UNITS HC TYPES Propagation elay, t PLH, t PHL C L = 50pF ns I/ CP to I/ OUT ns ns 5

6 C54HC297, C74HC297, C74HCT297 Switching Specifications Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX UNITS Propagation elay, t PLH, t PHL C L = 50pF ns φa 1, φb to XORP OUT ns ns Propagation elay, t PHL, t PHL C L = 50pF ns φb, φa 2 to ECP OUT ns ns Output Transition Time XORP OUT ECP OUT t TLH C L = 50pF ns ns ns Output Transition Time t TLH C L = 50pF ns I/ OUT ns ns Input Capacitance C I pf HCT TYPES Propagation elay, t PLH, t PHL C L = 50pF ns I/ CP to I/ OUT Propagation elay, t PLH, t PHL C L = 50pF ns φa 1, φb to XORP OUT Propagation elay, t PHL, t PHL C L = 50pF ns φb, φa 2 to ECP OUT Output Transition Time t TLH C L = 50pF ns XORP OUT Output Transition Time t TLH C L = 50pF ns ECP OUT Input Capacitance C I pf 6

7 C54HC297, C74HC297, C74HCT297 Logic iagram A B C MOULO-K COUNTER CONTROL CIRCUIT TO MOE CONTROLS 12-2 (11 STAGES NOT SHOWN) 4 /U 6 R T FF R T FF R T FF14 M R T FF13 M R T FF1 M R T FF EN CTR 3 POWER ON RESET T FF R T FF R M T FF14 R M T FF13 R M T FF1 R T FF R 1 = 1 1 BORROW CARRY I/ CP 5 INCREMENT/ECREMENT CIRCUIT 7 I/ OUT J K φa φb EXCLUSIVE-OR PHASE ETECTOR 11 XORP OUT 13 φa 2 S FF R S FF R EGE-CONTROLLE PHASE ETECTOR 12 ECP OUT 7

8 C54HC297, C74HC297, C74HCT297 Mf C CARRY /U EN CTR IVIE-BY-K COUNTER BORROW XORP OUT φa 1 f OUT φ OUT φb I/ CIRCUIT I/ CP 2Nf C ECP OUT J J f IN φ IN φa 2 ECP K FF I/ OUT IVIE-BY-N COUNTER FIGURE 1. PLL USING BOTH PHASE ETECTORS IN A RIPPLE-CANCELLATION SCHEME Mf C CARRY /U IVIE-BY-K COUNTER BORROW f OUT φ IN XORP OUT φa 1 φb I/ CIRCUIT I/ CP 2Nf C I/ OUT f OUT φ OUT IVIE-BY-N COUNTER FIGURE 2. PLL USING EXCLUSIVE-OR PHASE ETECTION CARRY PULSE (INTERNAL SIGNAL) BORROW PULSE (INTERNAL SIGNAL) I/ CP INPUT I/ OUT OUTPUT FIGURE 3. TIMING IAGRAM: I/ OUT IN-LOCK CONITION 8

9 C54HC297, C74HC297, C74HCT297 øb INPUT øa 2 INPUT ECP OUT OUTPUT FIGURE 4. TIMING IAGRAM: EGE CONTROLLE PHASE COMPARATOR WAVEFORMS øb INPUT øa 1 INPUT XORP OUT OUTPUT FIGURE 5. TIMING IAGRAM: EXCLUSIVE OR PHASE ETECTOR WAVEFORMS t W I/f MAX I/ CP t PLH I/ OUT t PHL t TLH t THL FIGURE 6. WAVEFORMS SHOWING THE CLOCK (I/ CP ) TO OUTPUT (I/ OUT ) PROPAGATION ELAYS, CLOCK PULSE WITH, OUTPUT TRANSITION TIMES AN MAXIMUM CLOCK PULSE FREUENCY øb INPUT øa 1 INPUT XORP OUT OUTPUT t PLH t PLH t TLH t PLH t THL t PHL FIGURE 7. WAVEFORMS SHOWING THE PHASE INPUT (øb, øa 1 ) TO OUTPUT (XORP OUT ) PROPAGATION ELAYS AN OUTPUT TRANSITION TIMES 9

10 C54HC297, C74HC297, C74HCT297 øb INPUT øa 2 INPUT ECP OUT OUTPUT t PHL t PLH t TLH t THL FIGURE 8. WAVEFORMS SHOWING THE PHASE INPUT (øb, øa 2 ) TO OUTPUT (ECP OUT ) PROPAGATION ELAYS AN OUTPUT TRANSITION TIMES t H t H /U, EN CTR INPUT t SU t SU INPUT t W 1/f MAX NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. FIGURE 9. WAVEFORMS SHOWING THE CLOCK ( ) PULSE WITH AN MAXIMUM CLOCK PULSE FREUENCY, AN THE INPUT (/U, EN CTR ) TO CLOCK ( ) SETUP AN HOL TIMES 10

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12 MPI002C JANUARY 1995 REVISE ECEMBER N (R-PIP-T**) 16 PINS SHOWN PLASTIC UAL-IN-LINE PACKAGE IM PINS ** A A MAX (19,69) (19,69) (23,37) (26,92) 16 9 A MIN (18,92) (18,92) (21,59) (23,88) (6,60) (6,10) C MS-100 VARIATION AA BB AC A (1,78) (1,14) (1,14) (0,76) (0,51) MIN (8,26) (7,62) (0,38) (5,08) MAX Gauge Plane Seating Plane (3,18) MIN (0,25) NOM (0,53) (0,38) (0,25) (2,54) M (10,92) MAX 14/18 PIN ONLY 20 pin vendor option /E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEEC MS-001, except 18 and 20 pin minimum body lrngth (im A).. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX ALLAS, TEXAS

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