INTEGRATED CIRCUITS. 74ALS161B/74ALS163B 4-bit binary counter. Product specification 1991 Feb 08 IC05 Data Handbook

Transcription

1 INTEGRATE CIRCUITS 11 Feb 08 IC05 ata Handbook

2 4ALS161B 4ALS163B, asynchronous reset, synchronous reset FEATURES Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Asynchronous reset (4ALS161B) Synchronous reset (4ALS163B) High speed synchronous expaion Typical count rate of 140MHz TY TYPICAL f MAX SUPPLY CURRENT TYPICAL (TOTAL) 4ALS161B 140MHz ma 4ALS163B 140MHz ma ORERING INFORMATION ESCRIPTION ORER COE COMMERCIAL RANGE V CC = 5V ±%, T amb = 0 C to +0 C RAWING NUMBER 16-pin plastic IP 4ALS161BN, 4ALS163BN SOT pin plastic SO 4ALS161B, 4ALS163B SOT-1 16-pin plastic SSOP Type II 4ALS161BB, 4ALS163BB SOT338-1 ESCRIPTION Synchronous presettable s (4ALS161B, 4ALS163B) feature an internal carry look-ahead and can be used for high speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the parallel enable () input disables the counting action and causes the data at the 0 3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for are met). Preset takes place regardless of the levels at count enable (, ) inputs. A Low level at the master reset (MR) input sets all the four outputs of the flip-flops (0 3) in 4ALS161B to Low levels, regardless of the levels at,, and inputs (thus providing an asynchronous clear function). For the 4ALS163B the clear function is synchronous. A Low level at the synchronous reset (SR) input sets all four outputs of the flip-flops (0 3) to Low levels after the next positive-going traition on the clock () input ( provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at,, and inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAN gate (see Figure 1). The carry look-ahead simplifies serial cascading of the counters. Both count enable ( and ) inputs must be High to count. The input is fed forward to enable the output. The output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of 0. This pulse can be used to enable the next cascaded stage (see Figure ). The output is subjected to decoding spikes due to internal race conditio, Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters. INPUT AN OUTPUT LOAING AN FAN-OUT TABLE NOTE: PINS ESCRIPTION 4ALS (U.L.) HIGH/LOW LOA VALUE HIGH/LOW 0 3 ata inputs 1.0/1.0 0µA/0.1mA Count enable parallel input (active-low) 1.0/1.0 0µA/0.1mA Count enable trickle input (active-low) 1.0/1.0 0µA/0.1mA Clock input (active rising edge) 1.0/1.0 0µA/0.1mA Parallel enable input (active-low) 1.0/1.0 0µA/0.1mA MR Asynchronous master reset input (active-low) for 4ALS161B 1.0/1.0 0µA/0.1mA SR Asynchronous reset input (active-low) for 4ALS163B 1.0/1.0 0µA/0.1mA 0 3 Flip-flop outputs 0/80 0.4mA/8mA Terminal count output (active-low) 0/80 0.4mA/8mA One (1.0) ALS unit load is defined as: 0µA in the High state and 0.1mA in the Low state. 11 Feb

3 STATE IAGRAM SF00664 APPLICATIONS V CC CLOCK ALS163B SR SC00086 Figure 1. Maximum Count Modifying Scheme Terminal Count = 6 H H = Enable count or L L = isable count ALS163B SR ALS163B 4ALS163B 4ALS163B 4ALS163B SR SR SR SR SC0008 Figure. Synchronous Multistage Counting Scheme 11 Feb 08 3

4 PIN CONFIGURATION 4ALS161B PIN CONFIGURATION 4ALS163B MR 1 16 V CC SR 1 16 V CC GN 8 GN 8 SF00656 SF0065 LOGIC SYMBOL 4ALS161B LOGIC SYMBOL 4ALS163B MR SR V CC = Pin 16 GN = Pin SF00658 V CC = Pin 16 GN = Pin SF0065 IEC/IEEE SYMBOL 4ALS161B IEC/IEEE SYMBOL 4ALS163B 1 CTR IV 16 R M1 G3 G4 C /1,3,4+ 1 CTR IV 16 R M1 G3 G4 C /1,3,4+ 3 1, , CT= CT=15 15 SF00660 SF Feb 08 4

5 LOGIC IAGRAM 4ALS161B MR R R R R V CC = Pin 16 GN = Pin 8 SF0066 MOE SELECTION FUNCTION TABLE 4ALS161B INPUTS OUTPUTS MR n n ORATING MOE L X X X X X L L Reset (clear) H X X l l L L H X X l h H (a) Parallel load H h h h X count (a) Count h X l X h X qn (a) h X X l h X qn L Hold (do nothing) H = High-voltage level h = High state must be present one setup time before the Low-to-High clock traition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock traition qn = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock traition X = on t care (a) = The output is High when is High and the counter is at terminal count (HHHH) = Low-to-High clock traition 11 Feb 08 5

6 LOGIC IAGRAM 4ALS163B SR V CC = Pin 16 GN = Pin 8 SF00663 MOE SELECTION FUNCTION TABLE 4ALS163B INPUTS OUTPUTS SR n n ORATING MOE l X X X X L L Reset (clear) h X X l l L L h X X l h H (a) Parallel load h h h h X count (a) Count h X l X h X qn (a) h X X l h X qn L Hold (do nothing) H = High-voltage level h = High state must be present one setup time before the Low-to-High clock traition L = Low-voltage level l = Low state must be present one setup time before the Low-to-High clock traition qn = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock traition X = on t care (a) = The output is High when is High and the counter is at terminal count (HHHH) = Low-to-High clock traition 11 Feb 08 6

7 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage 0.5 to +.0 V V IN Input voltage 0.5 to +.0 V I IN Input current 30 to +5 ma V OUT Voltage applied to output in High output state 0.5 to V CC V I OUT Current applied to output in Low output state 16 ma T amb Operating free-air temperature range 0 to +0 C T stg Storage temperature range 65 to +150 C RECOMMENE ORATING CONITIONS SYMBOL PARAMETER LIMITS MIN NOM MAX V CC Supply voltage V V IH High-level input voltage.0 V V IL Low-level input voltage 0.8 V I IK Input clamp current 18 ma I OH High-level output current 0.4 ma I OL Low-level output current 8 ma T amb Operating free-air temperature range 0 +0 C UNIT C ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONITIONS 1 MIN TYP MAX UNIT V = ±%, V = MAX, V OH High-level output voltage CC, IL V IH = MIN I OH = 0.4mA 04mA V CC V V = MIN, V = MAX, I OL = 4mA V V OL Low-level output voltage CC IL V IH = MIN I OL = 8mA V V IK Input clamp voltage V CC = MIN, I I = I IK V I I Input current at minimum input voltage V CC = MAX, V I =.0V 0.1 ma I IH High-level input current V CC = MAX, V I =.V 0 µa I IL Low-level input current V CC = MAX, V I = 0.4V 0.1 ma I O Output current 3 V CC = MAX, V O =.5V ma I CC Supply current (total) V CC = MAX 1 ma NOTES: 1. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type.. All typical values are at V CC = 5V, T amb = 5 C. 3. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I OS. 11 Feb 08

8 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONITION LIMITS T amb = 0 C to +0 C V CC = +5.0V ± % C L = 50pF, R L = 500Ω f MAX Maximum clock frequency Waveform 1 0 MHz t PLH t PLH t PLH Propagation delay to n Propagation delay to Propagation delay to Propagation delay MR to n Propagation delay MR to AC ELECTRICAL CHARACTERISTICS Waveform 1 Waveform 1 Waveform SYMBOL PARAMETER TEST CONITION t su (H) t su (L) t h (H) t h (L) t su (H) t su (L) t h (H) t h (L) t su (H) t su (L) t h (H) t h (L) t w (H) t w (L) t w (H) t w (L) Setup time, High or Low n to Hold time, High or Low n to Setup time, High or Low or SR to Hold time, High or Low or SR to Setup time, High or Low or to Hold time, High or Low or to Pulse width (load), High or Low Pulse width (count), High or Low MIN MAX ALS161B Waveform ALS163B Waveform Waveform 6 Waveform 6 Waveform 5 or 6 Waveform 6 Waveform 4 Waveform 4 Waveform 1 Waveform 1 LIMITS T amb = 0 C to +0 C V CC = +5.0V ± % C L = 50pF, R L = 500Ω t w (L) MR or SR Pulse width, Low Waveform t REC Recovery time, CR or SR to Waveform 3.0 MIN MAX UNIT UNIT 11 Feb 08 8

9 AC WAVEFORMS For all waveforms, = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/f MAX t w (H) t PLH t w (L) t PLH n, SC00088 Waveform 1. Propagation elay for Clock Input to Output, Clock PUlse Width, and Maximum Clock Frequency Waveform. Propagation elay for to Output SF00668 t w (L) MR t REC t su (H) t h (H) t su (L) t h (L) n, SF0066 SC0008 Waveform 3. Master Reset Pulse Width, Master Reset to Output elay, and Master Reset to Clock Recovery Time Waveform 4. and Setup and Hold Times n SR t su t h t su (L) t h (L) t su (H) t h (H) t su (L) t h (L) t su (H) t h (H) SC0000 SC0001 Waveform 5. Synchronous Reset Setup and Hold Times Waveform 6. ata and Parallel Enable Setup and Hold Times 11 Feb 08

10 TEST CIRCUIT AN WAVEFORMS PULSE GENERATOR V IN V CC.U.T. V OUT NEGATIVE PULSE 0% % t THL ( t ff) t w t TLH ( t r ) % 0% AMP (V) 0.3V R T C L R L Test Circuit for Totem-pole Outputs POSITIVE PULSE % 0% t TLH ( t r ) t w t THL ( t f ) 0% % AMP (V) 0.3V EFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to Z OUT of pulse generators. Family 4ALS Input Pulse efinition INPUT PULSE REUIREMENTS Amplitude 3.5V 1.3V Rep.Rate t w t TLH t THL 1MHz SC Feb 08

11 4ALS161B 4ALS163B IP16: plastic dual in-line package; 16 leads (300 mil) SOT Feb 08 11

12 4ALS161B 4ALS163B SO16: plastic small outline package; 16 leads; body width 3. mm SOT-1 11 Feb 08 1

13 4ALS161B 4ALS163B SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT Feb 08 13

14 4ALS161B 4ALS163B EFINITIONS ata Sheet Identification Product Status efinition Objective Specification Preliminary Specification Product Specification Formative or in esign Preproduction Product Full Production This data sheet contai the design target or goal specificatio for product development. Specificatio may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contai Final Specificatio. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 340 Sunnyvale, California Telephone Copyright Philips Electronics North America Corporation 1 All rights reserved. Printed in U.S.A. 11 Feb 08 14