CD74HC221, CD74HCT221

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Data sheet acquired from Harris Semiconductor SCHS66A November 997 - Revised April 999 CD74HC22, CD74HCT22 High Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description [ /Title

1 Data sheet acquired from Harris Semiconductor SCHS66A November Revised April 999 CD74HC22, CD74HCT22 High Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description [ /Title (CD74 HC22, CD74 HCT22 ) /Subject High peed MOS ogic ual onos able ulti- Overriding RESET Terminates Output Pulse Triggering from the Leading or Trailing Edge and Buffered Outputs Separate Resets Wide Range of Output-Pulse Widths Schmitt Trigger on B Inputs Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 25 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l µa at V OL, V OH The CD74HC22, and CH74HCT22 are dual monostable multivibrators with reset. An external resistor (R X ) and an external capacitor (C X ) control the timing and the accuracy for the circuit. Adjustment of R X and C X provides a wide range of output pulse widths from the and terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. Once triggered, the outputs are independent of further trigger inputs on A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing Edge triggering (A) and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. The minimum value of external resistance, R X, is typically 500Ω. The minimum value of external capacitance, C X, is 0pF. The calculation for the pulse width is t W = 0.7 R X C X at = 4.5V. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CD74HC22E -55 to 25 6 Ld PDIP E6.3 CD74HCT22E -55 to 25 6 Ld PDIP E6.3 CD74HC22M -55 to 25 6 Ld SOIC M6.5 CD74HCT22M -55 to 25 6 Ld SOIC M6.5 NOTES:. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer or die are available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinout CD74HC22, CD74HCT22 (PDIP, SOIC) TOP VIEW A 6 B 2 5 C X R X R 3 4 C X C X 6 2R 2C X R X 7 2B 8 9 2A CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation 997 File Number 670.

2 Functional Diagram C X R X 4 5 A B 2 C X C X R X MONO 3 4 R 3 2R 2A B MONO C X 2C X R X 6 7 2C X 2R X TRUTH TABLE INPUTS OUTPUTS A B R H X H L H X L H L H L H H H X X L L H L H (Note 3) (Note 3) NOTE: H = High Level, L = Low Level, X = Irrelevant, = Transition from Low to High Level, = Transition from High to Low Level, = One High Level Pulse, = One Low Level Pulse 3. For this combination the reset input must be low and the following sequence must be used: pin (or 9) must be set high or pin 2 (or ) set low; then pin (or 9) must be low and pin 2 (or ) set high. Now the reset input goes from low-to-high and the device will be triggered. 2

3 Logic Diagram C P 6 N R X A (9) B 2 () R 3 () P RESET FF R D C P OP AMP + - R2 5 (7) S R C R X C X M M PP MIRROR VOLTAGE R3 C X MASK FF S R MAIN FF R R4 N PULLDOWN FF D C N 4 (6) C X 8 4 (2) (3) 5 C R + - OP AMP 3

4 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Drain Current, per Output, I O For -0.5V < V O < + 0.5V ±25mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground Current, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 4) θ JA ( o C/W) θ JC ( o C/W) PDIP Package N/A SOIC Package N/A Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 50 o C Maximum Lead Temperature (Soldering s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 25 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Time, t r, t f on Inputs A and R 2V ns (Max) 4.5V ns (Max) 6V ns (Max) Input Rise and Fall Time, t r, t f on Input B 2V Unlimited ns (Max) 4.5V Unlimited ns (Max) 6V Unlimited ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads SYMBOL TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o CTO25 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V IH or V IL V V V UNITS V V V V OL V IH or V IL V V V V V V 4

5 DC Electrical Specifications (Continued) PARAMETER Input Leakage Current uiescent Device Current HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current uiescent Device Current Additional uiescent Device Current Per Input Pin: Unit Load SYMBOL I I I CC or or V IH to 5.5 V IL to ±0. - ± - ± µa µa V V V OH V IH or V IL V V V OL V IH or V IL V I I I CC I CC TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o CTO25 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX and or V ±0. - ± - ± µa µa to 5.5 NOTE: For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is.8ma. HCT Input Loading Table UNITS µa INPUT UNIT LOADS All Inputs 0.3 NOTE: Unit Load is I CC limit specified in DC Electrical Table, e.g., 360µA max at 25 o C. Prerequisite For Switching Function 25 o C -40 o C TO 85 o C -55 o C TO 25 o C PARAMETER SYMBOL (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES t WL ns A ns ns t WH ns B ns ns 5

6 Prerequisite For Switching Function (Continued) Reset Recovery Time R to A or B Output Pulse Width or C X = 0.µF R X = kω Output Pulse Width or C X = 28pF, R X = 2kΩ t WL ns ns ns t SU ns ns ns t W µs t W ns C X = 00pF, R X = 2kΩ t W µs C X = 00pF, R X = kω t W µs HCT TYPES A t WL ns B Reset Recovery Time R to A or B PARAMETER SYMBOL (V) Output Pulse Width or C X = 0.µF R X = kω Output Pulse Width or C X = 28pF, R X = 2kΩ t WH ns t WL ns t SU ns t W µs t W ns C X = 00pF, R X = 2kΩ t W µs C X = 00pF, R X = kω t W µs Switching Specifications Input t r, t f = 6ns 25 o C -40 o C TO 85 o C -55 o C TO 25 o C MIN TYP MAX MIN MAX MIN MAX UNITS PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 25 o C MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Trigger A, B, R to t PLH C L = 50pF ns C L = 50pF ns C L = 50pF ns C L = 5pF ns Trigger A, B, R to t PHL C L = 50pF ns C L = 50pF ns C L = 50pF ns C L = 5pF ns 6

7 Switching Specifications Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 25 o C MIN TYP MAX MIN MAX MIN MAX UNITS R to t PLH C L = 50pF ns ns ns R to t PHL C L = 50pF ns ns ns Output Transition Time t TLH, t THL C L = 50pF ns ns ns Input Capacitance C IN pf Pulse Width Match Between Circuits in the Same Package C X = 00pF, R X = kω to ± % Power Dissipation Capacitance (Notes 5, 6) HCT TYPES Trigger A, B, R to Trigger A, B, R to R to R to CPD pf t PLH C L = 50pF ns C L = 5pF ns t PHL C L = 50pF ns C L = 5pF ns t PLH C L = 50pF ns t PHL C L = 50pF ns Output Transition Time t TLH, t THL C L = 50pF ns ns ns Input Capacitance C IN pf Pulse Width Match Between Circuits in the Same Package C X = 00pF, R X = kω to ± % Power Dissipation Capacitance (Notes 5, 6) CPD pf NOTES: 5. C PD is used to determine the dynamic power consumption, per multivibrator. 6. P D = (C PD + C L ) V 2 CC f i + Σ where f i = input frequency, f o = output frequency, C L = output load capacitance, = supply voltage. 7

8 Test Circuits and Waveforms t r C L CLOCK t f C L I t WL + t WH = fcl 90% 50% 50% 50% % % t r C L = 6ns CLOCK t f C L = 6ns I t WL + t WH = fcl 3V 2.7V.3V.3V.3V 0.3V 0.3V t WL t WH t WL t WH NOTE: Outputs should be switching from % to 90% in accordance with device truth table. For f MAX, input duty cycle = 50%. FIGURE. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from % to 90% in accordance with device truth table. For f MAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT 90% 50% % INPUT 2.7V.3V 0.3V 3V t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH 90% 50% % INVERTING OUTPUT t PHL t PLH 90%.3V % FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 8

9 Typical Performance Curves 685 = 5V T A = 25 o C t W, PULSE WIDTH (µs) C X = µf K FACTOR HCT T A, AMBIENT TEMPERATURE ( o C) , SUPPLY VOLTAGE (V) FIGURE 5. HC/HCT22 OUTPUT PULSE WIDTH vs TEMPERATURE FIGURE 6. HC/HCT22 K FACTOR vs SUPPLY VOLTAGE 6 5 = 2V 6 5 = 4.5V t W, PULSE WIDTH (µs) R X = 0K R X = 50K R X = 2K t W, PULSE WIDTH (µs) R X = 0K R X = 50K R X = 2K C X, TIMING CAPACITANCE (pf) C X, TIMING CAPACITANCE (pf) FIGURE 7. HC22 OUTPUT PULSE WIDTH vs C X FIGURE 8. HC/HCT22 OUTPUT PULSE WIDTH vs C X 9

10 Typical Performance Curves (Continued) 685 t W, PULSE WIDTH (µs) = 5V C X = µf K FACTOR T A = 25 o C HCT T A, AMBIENT TEMPERATURE ( o C) , SUPPLY VOLTAGE (V) FIGURE 5. HC/HCT22 OUTPUT PULSE WIDTH vs TEMPERATURE FIGURE 6. HC/HCT22 K FACTOR vs SUPPLY VOLTAGE 6 5 = 6V t W, PULSE WIDTH (µs) R X = 0K R X = 50K R X = 2K C X, TIMING CAPACITANCE (pf) FIGURE 9. HC22 OUTPUT PULSE WIDTH vs C X

11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 999, Texas Instruments Incorporated

CD54/74HC221, CD74HCT221

Data sheet acquired from Harris Semiconductor SCHS166B November 1997 - Revised May 2000 CD54/74HC221, CD74HCT221 High Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description [ /Title