CD54/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD74HCT4052, CD54/74HC4053, CD74HCT4053

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1 Data sheet acquired from Harris Semiconductor SCHS122B November Revised May 2000 CD54/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD74HCT4052, CD54/74HC4053, CD74HCT4053 High Speed CMOS Logic Analog Multiplexers/Demultiplexers Features Description [ /Title (CD54 HC405 1, CD74 HC405 1, CD74 HCT40 51, CD74 HC405 2, Wide Analog Input Voltage Range ±5V Max Low On Resistance - 70Ω Typical ( - = 4.5V) - 40Ω Typical ( - = 9V) Low Crosstalk between Switches Fast Switching and Propagation Speeds Break-Before-Make Switching Wide Operating Temperature Range o C to 125 o C CD54HC/CD74HC Types - Operation Control Voltage V to V - Switch Voltage V to 10V - High Noise Immunity... N IL = 30%, N IH = 30% of, = 5V CD54HCT/CD74HCT Types - Operation Control Voltage V to 5.5V - Switch Voltage V to 10V - Direct LSTTL Input Logic Compatibility... V IL = 0.8V Max, V IH = 2V Min - CMOS Input Compatibility..... I I 1µA at V OL, V OH These devices are digitally controlled analog switches which utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. These analog multiplexers/demultiplexers control analog voltages that may vary across the voltage supply range (i.e. to ). They are bidirectional switches thus allowing any analog input to be used as an output and visa-versa. The switches have low on resistance and low off leakages. In addition, all three devices have an enable control which, when high, disables all switches to their off state. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC4051F -55 to Ld CERDIP CD54HC4051F3A -55 to Ld CERDIP CD74HC4051E -55 to Ld PDIP CD74HC4051M -55 to Ld SOIC CD54HCT4051F3A -55 to Ld CERDIP CD74HCT4051E -55 to Ld PDIP CD74HCT4051M -55 to Ld SOIC CD54HC4052F -55 to Ld CERDIP CD54HC4052F3A -55 to Ld CERDIP CD74HC4052E -55 to Ld PDIP CD74HC4052M -55 to Ld SOIC CD74HCT4052E -55 to Ld PDIP CD74HCT4052M -55 to Ld SOIC CD74HCT4052SM -55 to Ld SSOP CD54HC4053F -55 to Ld CERDIP CD54HC4053F3A -55 to Ld CERDIP CD74HC4053E -55 to Ld PDIP CD74HC4053M -55 to Ld SOIC CD74HCT4053E -55 to Ld PDIP CD74HCT4053M -55 to Ld SOIC CD74HCT4053PW -55 to Ld TSSOP NOTES: 1. When ordering, use the entire part number. Add the suffix 9 to obtain the variant in the tape and reel. For the TSSOP package only, add the suffix R to obtain the variant in the tape and reel. 2. Wafer or die is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2000, Texas Instruments Incorporated 1

2 Pinouts HC4051, HCT4051, HC4052, CD74HCT4052, HC4053, CD74HCT4053 CD54HC4051, CD54HCT4051 (CERDIP) CD74HC4051, CD74HCT4051 (PDIP, SOIC) TOP VIEW CD54HC4052 (CERDIP) CD74HC4052, CD74HCT4052 (PDIP, SOIC) TOP VIEW CHANNEL A4 A COM OUT/IN A CHANNEL A7 A5 E A2 A1 A0 A3 S0 S1 S2 CHANNEL ADDRESS SELECT CHANNEL B0 B2 COM OUT/IN B N CHANNEL B3 B1 E A2 A1 A N A0 A3 S0 S1 CHANNEL COM OUT/IN CHANNEL CD54HC4053 (CERDIP) CD74HC4053, CD74HCT4053 (PDIP, SOIC, TSSOP) TOP VIEW CHANNEL B1 B0 C B N A N COM OUT/IN COM OUT/IN COM OUT/IN C N C A1 A0 CHANNEL E 11 S S1 8 9 S2 2

3 Functional Diagram of HC/HCT4051 CHANNEL A 7 A A 5 A 4 A 3 A 2 A 1 A S 0 11 S 1 S LOGIC LEVEL CONVERSION BINARY TO 1 OF 8 DECODER WITH ENABLE 3 A COMMON OUT/IN E 8 7 TRUTH TABLE HC/HCT4051 INPUT STATES ENABLE S 2 S 1 S 0 ON CHANNELS L L L L A0 L L L H A1 L L H L A2 L L H H A3 L H L L A4 L H L H A5 L H H L A L H H H A7 H X X X None X = Don t care 3

4 Functional Diagram of HC4052, CD74HCT4052 A CHANNELS 1 A 3 A 2 A 1 A S 1 S LOGIC LEVEL CONVERSION BINARY TO 1 OF 4 DECODER WITH ENABLE 13 3 COMMON A OUT/IN COMMON B OUT/IN E B 0 B 1 B 2 B 3 B CHANNELS TRUTH TABLE HC4052, CD74HCT4052 INPUT STATES ENABLE S 1 S 0 ON CHANNELS L L L A0, B0 L L H A1, B1 L H L A2. B2 L H H A3, B3 H X X None X = Don t care 4

5 Functional Diagram of HC4053, CD74HCT4053 LOGIC LEVEL CONVERSION 1 BINARY TO 1 OF 2 DECODERS C 1 C 0 B 1 B 0 A 1 A 0 WITH ENABLE S A COMMON OUT/IN S B COMMON OUT/IN S C COMMON OUT/IN E 8 7 TRUTH TABLE HC4053, CD74HCT4053 INPUT STATES ENABLE S 0 S 1 S 2 ON CHANNELS L L L L C0, B0, A0 L H L L C0, B0, A1 L L H L C0, B1, A0 L H H L C0, B1, A1 L L L H C1, B0, A0 L H L H C1, B0, A1 L L H H C1, B1, A0 L H H H C1, B1, A1 H X X X None X = Don t care 5

6 Absolute Maximum Ratings (Note 3) DC Supply Voltage, V to 10.5V DC Supply Voltage, V to +7V DC Supply Voltage, V to -7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Switch Diode Current, I OK For V I < -0.5V or V I > + 0.5V ±20mA DC Switch Current, (Note 2) For V I > -0.5V or V I < + 0.5V ±25mA DC or Ground Current, I CC ±50mA DC Current, I EE mA Thermal Information Thermal Resistance (Typical, Note 4) θ JA ( o C/W) θ JC ( o C/W) PDIP Package N/A SOIC Package N/A CERDIP Package TSSOP Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C Recommended Operating Conditions For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges PARAMETER MIN MAX UNITS Supply Voltage Range (For T A = Full Package Temperature Range), (Note 5) CD54/74HC Types 2 V CD54/74HCT Types V Supply Voltage Range (For T A = Full Package Temperature Range), - CD54/74HC Types, CD54/74HCT Types (See Figure 1) 2 10 V Supply Voltage Range (For T A = Full Package Temperature Range), (Note 5) CD54/74HC Types, CD54/74HCT Types (See Figure 2) 0 - V DC Input Control Voltage, V I V Analog Switch I/O Voltage, V IS V Operating Temperature, T A o C Input Rise and Fall Times, t r, t f 2V ns 4.5V ns V ns CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. All voltages referenced to unless otherwise specified. 4. θ JA is measured with the component mounted on an evaluation PC board in free air. 5. In certain applications, the external load resistor current may include both and signal line components. To avoid drawing current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.V (calculated from r ON values shown in Electrical Specifications table). No current will flow through R L if the switch current flows into terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14 and 15 on the HC/HCT4053. Recommended Operating Area as a Function of Supply Voltages HC HCT HCT HC FIGURE 1. FIGURE 2.

7 DC Electrical Specifications TEST CONDITIONS AMBIENT TEMPERATURE, T A PARAMETER V IS V I 25 o C -40 o C - 85 o C -55 o C o C MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input Voltage, V V IH V V Low Level Input Voltage, V V IL V V On Resistance, r ON I O = 1mA, (Figure 11) or V IL or Ω V IH Ω Ω to Ω Ω Ω Maximum On Resistance Between any Two Channels, r ON Ω Ω Ω Switch On/Off Leakage Current, I IZ For Switch Off: When V IS =, V OS = ; When V IS =, V OS = For Switch On: All Applicable Combinations of V IS and V OS Voltage Levels V IL or V IH 1 and 2 Channels ±0.1 - ±1 - ±1 µa ±0.1 - ±1 - ±1 µa 4 Channels ±0.1 - ±1 - ±1 µa ±0.2 - ±2 - ±2 µa 8 Channels ±0.2 - ±2 - ±2 µa ±0.4 - ±4 - ±4 µa Control Input Leakage Current, I IL or ±0.1 - ±1 - ±1 µa Quiescent Device Current, I CC I O = 0 When V IS =, V OS = or µa When V IS =, µa V OS = 7

8 DC Electrical Specifications (Continued) TEST CONDITIONS AMBIENT TEMPERATURE, T A PARAMETER V IS V I 25 o C -40 o C - 85 o C -55 o C o C MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input Voltage, V IH Low Level Input Voltage, V IL 4.5 to to V V On Resistance, r ON I O = 1mA, (Figure 15) or V IL or Ω V IH Ω Ω to Ω Ω Ω Maximum On Resistance Between any Two Channels, r ON Ω Ω Ω Switch On/Off Leakage Current, I IZ For Switch Off: When V IS =, V OS = ; When V IS =, V OS = For Switch On: All Applicable Combinations of V IS and V OS Voltage Levels V IL or V IH 1 and 2 Channels ±0.1 - ±1 - ±1 µa ±0.1 - ±1 - ±1 µa 4 Channels ±0.1 - ±1 - ±1 µa ±0.2 - ±2 - ±2 µa 8 Channels ±0.2 - ±2 - ±2 µa ±0.4 - ±4 - ±4 µa Control Input Leakage - (Note 7) ±0.1 - ±1 - ±1 µa Current, I IL Quiescent Device Current, I CC I O = 0 When V IS =, V OS = or µa When V IS =, µa V OS = Additional Quiescent Device Current, I CC (Note ) Per Input Pin: 1 Unit Load to µa NOTES:. For dual supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. 7. Any voltage between and. HCT Input Loading Table TYPE INPUT UNIT LOADS (NOTE) 4051, 4053 All All 0.4 NOTE: Unit load is I CC limit specified in DC Specifications table, e.g., 30mA max. at 25 o C. 8

9 Switching Specifications = 5V, T A = 25 o C, Input t r, t r = ns TYPICAL PARAMETER C L (pf) HC HCT HC HCT HC HCT UNITS Propagation Delay Switch IN to OUT, t PHL, t PLH ns Switch Turn-Off (S or E), t PHZ, tplz ns Switch Turn-On (S or E), t PZH, t PZL ns Power Dissipation Capacitance, C PD (Note 8) pf NOTE: 8. C PD is used to determine the dynamic power consumption, per package. P D = C PD V 2 CC f I + (C L + C S ) V 2 CC f O f O = output frequency f I = input frequency C L = output load capacitance C S = switch capacitance = supply voltage Switching Specifications C L = 50pF, Input t r, t r = ns AMBIENT TEMPERATURE, T A 25 o C -40 o C - 85 o C -55 o C o C PARAMETER HC HCT HC HCT HC HCT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS Propagation Delay, Switch ns In to Out, t PLH, t PHL ns ns ns Maximum Switch Turn Off Delay from S or E to Switch Output t PHZ, t PLZ ns ns ns ns ns ns ns ns ns ns ns ns 9

10 Switching Specifications C L = 50pF, Input t r, t r = ns (Continued) AMBIENT TEMPERATURE, T A 25 o C -40 o C - 85 o C -55 o C o C PARAMETER HC HCT HC HCT HC HCT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS Maximum Switch Turn On Delay from S or E to Switch Output t PZL, t PZH ns ns ns ns ns ns ns ns ns ns ns ns Input (Control) pf Capacitance, C I Analog Channel Specifications Typical Values at T A = 25 o C PARAMETER TEST CONDITIONS HC/HCT TYPES HC/ HCT UNITS Switch Input Capacitance, C I All pf Common Output Capacitance, C COM pf pf pf Minimum Switch Frequency Response at -3, f MAX (Figures 12, 14, 1) See Figure 3, Notes 9, MHz MHz MHz MHz MHz MHz 10

11 Analog Channel Specifications Typical Values at T A = 25 o C PARAMETER TEST CONDITIONS HC/HCT TYPES HC/ HCT UNITS Crosstalk Between any Two Switches (Note 12) See Figure 4, Notes 10, N/A (TBE) 4053 (TBE) 4051 N/A (TBE) 4053 (TBE) Sinewave Distortion See Figure 5 All % All % E or S to Switch Feedthrough Noise See Figure Notes 10, mv (TBE) mv 4053 mv 4051 mv (TBE) mv 4053 mv Switch OFF Signal Feedthrough (Figures 13, 15, 17) See Figure 7 Notes 10, NOTES: 9. Adjust input voltage to obtain 0m at V OS for f IN = 1MHz. 10. V IS is centered at ( - )/ Adjust input for 0m. 12. Not applicable for HC/HCT

12 Test Circuits and Waveforms V IS INPUT 0.1µF R SWITCH ON R C V OS1 f IS = 1MHz SINEWAVE R = 50Ω C = 10pF /2 V IS 0.1µF SWITCH ON /2 50Ω V OS 10pF METER /2 R SWITCH OFF R C V OS2 METER /2 FIGURE 3. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 4. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT E SINE- WAVE 10µF V IS f IS = 1kHz TO 10kHz SWITCH ON /2 V I = V IH 10kΩ 50pF VIS V OS DISTORTION METER /2 00Ω SWITCH ALTERNATING ON AND OFF t r, t f ns f CONT = 1MHz 50% DUTY CYCLE /2 00Ω V OS V OS 50pF SCOPE V P-P FIGURE 5. SINEWAVE DISTORTION TEST CIRCUIT FIGURE. CONTROL TO SWITCH FEEDTHROUGH NOISE TEST CIRCUIT f IS 1MHz SINEWAVE R = 50Ω C = 10pF V IS 0.1µF R SWITCH OFF V C = V IL R C V OS METER /2 /2 FIGURE 7. SWITCH OFF SIGNAL FEEDTHROUGH 12

13 Test Circuits and Waveforms (Continued) t r = ns SWITCH INPUT t f = ns 90% 50% 10% t PLH SWITCH OUTPUT t PHL VEE 90% 50% 10% FIGURE 8A. ns E OR Sn 50% 90% 10% ns ns E OR Sn 1.3 t r t f ns 3V t PLZ t PZL t PLZ t PZL OUTPUT LOW TO OFF 10% 50% OUTPUT LOW TO OFF 10% 50% OUTPUT HIGH TO OFF t PHZ 90% t PZH 50% OUTPUT HIGH TO OFF t PHZ 90% t PZH 50% SWITCH ON SWITCH OFF SWITCH ON SWITCH ON SWITCH OFF SWITCH ON FIGURE 8B. HC TYPES FIGURE 8C. HCT TYPES FIGURE 8. SWITCH PROPAGATION DELAY, TURN-ON, TURN-OFF TIMES FOR t PLZ AND t PZL FOR t PHZ AND t PZH IN R L = 1kΩ C L 50pF OUT FOR t PLZ AND t PZL FOR t PHZ AND t PZH IN 50pF OUT FIGURE 9. SWITCH ON/OFF PROPAGATION DELAY TEST CIRCUIT FIGURE 10. SWITCH IN TO SWITCH OUT PROPAGATION DELAY TEST CIRCUIT 13

14 Typical Performance Curves ON RESISTANCE (Ω) = 4.5V - = V - = 9V INPUT SIGNAL VOLTAGE FIGURE 11. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE = 4.5V = -4.5V = -4.5V PIN 12 TO 3 = 2.25V = -2.25V = -2.25V PIN 12 TO K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 12. CHANNEL ON BANDWIDTH (HC/HCT4051) = 2.25V = -2.25V = -2.25V PIN 12 TO 3 = 4.5V = -4.5V = -4.5V PIN 12 TO K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 13. CHANNEL OFF FEEDTHROUGH (HC/HCT4051) = 4.5V = -4.5V = -4.5V PIN 4 TO 3 = 2.25V = -2.25V = -2.25V PIN 4 TO = 2.25V = -2.25V = -2.25V PIN 4 TO 3 = 4.5V = -4.5V = -4.5V PIN 4 TO K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 14. CHANNEL ON BANDWIDTH (HC/HCT4052) K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 15. CHANNEL OFF FEEDTHROUGH (HC/HCT4052) 14

15 Typical Performance Curves (Continued) = 4.5V = -4.5V = -4.5V PIN 5 TO 4 = 2.25V = -2.25V = -2.25V PIN 5 TO 4 10K 100K 1M 10M 100M FREQUENCY (Hz) = 2.25V = -2.25V = -2.25V PIN 5 TO 4 = 4.5V = -4.5V = -4.5V PIN 5 TO K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 1. CHANNEL ON BANDWIDTH (HC/HCT4053) FIGURE 17. CHANNEL OFF FEEDTHROUGH (HC/HCT4053) 15

16 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated

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