CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State Description Features

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CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 [ /Title (CD74H C173, CD74H CT173) /Subject (High Speed CMOS Logic Quad D- Type Data sheet acquired from Harris Semiconductor SCHS158E February 1998 -

1 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 [ /Title (CD74H C173, CD74H CT173) /Subject (High Speed CMOS Logic Quad D- Type Data sheet acquired from Harris Semiconductor SCHS158E February Revised October 2003 Features Three-State Buffered Outputs Gated Input and Output Enables Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Pinout CD54HC173, CD54HCT173 (CERDIP) CD74HC173 (PDIP, SOIC, SOP, TSSOP) CD74HCT173 (PDIP, SOIC) TOP VIEW High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State Description The HC173 and HCT173 high speed three-state quad D- type flip-flops are fabricated with silicon gate CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can operate at speeds comparable to the equivalent low power Schottky devices. The buffered outputs can drive 15 LSTTL loads. The large output drive capability and three-state feature make these parts ideally suited for interfacing with bus lines in bus oriented systems. The four D-type flip-flops operate synchronously from a common clock. The outputs are in the three-state mode when either of the two output disable pins are at the logic 1 level. The input ENABLES allow the flip-flops to remain in their present states without having to disrupt the clock If either of the 2 input ENABLES are taken to a logic 1 level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Reset is enabled by taking the MASTER RESET (MR) input to a logic 1 level. The data outputs change state on the positive going edge of the clock. The HCT173 logic family is functionally, as well as pin compatible with the standard LS logic family. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC173F3A -55 to Ld CERDIP CD54HCT173F3A -55 to Ld CERDIP CD74HC173E -55 to Ld PDIP OE OE2 Q 0 Q 1 Q 2 Q 3 CP MR D0 D1 D2 D3 E2 8 9 E1 CD74HC173M -55 to Ld SOIC CD74HC173MT -55 to Ld SOIC CD74HC173M96-55 to Ld SOIC CD74HC173NSR -55 to Ld SOP CD74HC173PW -55 to Ld TSSOP CD74HC173PWR -55 to Ld TSSOP CD74HC173PWT -55 to Ld TSSOP CD74HCT173E -55 to Ld PDIP CD74HCT173M -55 to Ld SOIC CD74HCT173MT -55 to Ld SOIC CD74HCT173M96-55 to Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper Handling Procedures. Copyright 2003, Texas Instruments Incorporated 1

2 Functional Diagram CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 E1 E D0 D1 D2 D3 CP Q 0 Q 1 Q 2 Q 3 MR OE1 OE2 INPUTS TRUTH TABLE DATA ENABLE DATA MR CP E1 E2 D Q n H X X X X L L L X X X Q 0 L H X X Q 0 L X H X Q 0 L L L L L L L L H H H= High Level L = Low Level X= Irrelevant = Transition from Low to High Level Q 0 = Level Before the Indicated Steady-State Input Conditions Were Established NOTE: 1. When either OE1 or OE2 (or both) is (are) high, the output is disabled to the high-impedance state, however, sequential operation of the flip-flops is not affected. 2

3 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Logic Diagram 9 E1 10 E2 D Q 14 D0 7 CP CP R Q P N 3 Q 0 15 MR 1 OE1 2 OE2 13 D1 12 D2 11 D3 3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT IN DASHED ENCLOSURE Q 1 Q 2 Q 3 3

4 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground Current, I CC ±70mA Operating Conditions Temperature Range (T A ) o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) Thermal Information Package Thermal Impedance, θ JA (see Note 2): E (PDIP) Package o C/W M (SOIC) Package o C/W NS (SOP) Package ο C/W PW (TSSOP) Package o C/W Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input V IH V V V Low Level Input V IL V V High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads V OH V OL V V IH or V V IL V V V V V IH or V V IL V V V V Input Leakage Current I I or ±0.1 - ±1 - ±1 µa Quiescent Device Current I CC or µa 4

5 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 DC Electrical Specifications (Continued) TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX UNITS Three-State Leakage Current HCT TYPES I OZ V IL or ±0.5 - ±0.5 - ±10 µa V IH High Level Input Low Level Input V IH to 5.5 V IL to V V High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads V OH V OL V IH or V V IL V V IH or V V IL V Input Leakage Current I I to ±0.1 - ±1 - ±1 µa Quiescent Device Current I CC or µa Additional Quiescent Device Current Per Input Pin: 1 Unit Load I CC (Note 3) to µa Three-State Leakage Current I OZ V IL or ±0.5 - ±5.0 - ±10 µa V IH NOTE: 3. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS D0-D E1 and E CP 0.25 MR 0.2 OE1 and OE2 0.5 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25 o C. 5

6 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Switching Specifications Input t r, t f = 6ns PARAMETER HC TYPES Propagation Delay, Clock to Output Propagation Delay, MR to Output Propagation Delay Output Enable to Q (Figure 6) SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX t PLH, t PHL C L = 50pF ns UNITS ns C L = 15pF ns CL = 50pF ns t PHL C L = 50pF ns ns C L = 15pF ns CL = 50pF ns t PLZ, t PHZ CL = 50pF ns t PZL, t PZH C L = 50pF ns C L = 15pF ns CL = 50pF ns Output Transition Times t TLH, t THL C L = 50pF ns ns ns Maximum Clock Frequency f MAX C L = 15pF MHz Input Capacitance C IN pf Three-State Output Capacitance Power Dissipation Capacitance (Notes 4, 5) HCT TYPES Propagation Delay, Clock to Output Propagation Delay, MR to Output Propagation Delay Output Enable to Q (Figure 6) C O pf C PD pf t PLH, t PHL C L = 50pF ns C L = 15pF ns t PHL C L = 50pF ns C L = 15pF ns t PZL, t PZH CL = 50pF ns C L = 50pF ns C L = 15pF ns CL = 50pF ns Output Transition Times t TLH, t THL C L = 50pF ns Maximum Clock Frequency f MAX C L = 15pF MHz Input Capacitance C IN pf Power Dissipation Capacitance (Notes 4, 5) C PD pf NOTES: 4. C PD is used to determine the dynamic power consumption, per package. 5. P D =V 2 CC fi + (C L V 2 CC +fo ) where f i = Input Frequency, f O = Input Frequency, C L = Output Load Capacitance, = Supply. 6

7 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Prerequisite For Switching Specifications 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL (V) MIN MAX MIN MAX MIN MAX UNITS HC TYPES Maximum Clock Frequency f MAX MHz MHz MHz MR Pulse Width t w ns ns ns Clock Pulse Width t w ns ns ns Set-up Time, Data to Clock and E to Clock t SU ns ns ns Hold Time, Data to Clock t H ns ns ns Hold Time, E to Clock t H ns ns ns Removal Time, MR to Clock t REM ns ns ns HCT TYPES Maximum Clock Frequency f MAX MHz MR Pulse Width t w ns Clock Pulse Width t w ns Set-up Time, E to Clock t SU ns Set-up Time, Data to Clock t SU ns Hold Time, Data to Clock t H ns Hold Time, E to Clock t H ns Removal Time, MR to Clock t REM ns 7

8 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Test Circuits and Waveforms t r C L CLOCK t f C L I t WL + t WH = fcl t r C L = 6ns CLOCK t f C L = 6ns I t WL + t WH = fcl 3V 2.7V 0.3V 0.3V t WL t WH t WL t WH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT INPUT 2.7V 0.3V 3V t THL t TLH t THL t TLH INVERTING t PHL t PLH INVERTING t PHL t PLH FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC CLOCK INPUT t r C L t f C L CLOCK INPUT t r C L 2.7V 0.3V t f C L 3V t H(H) t H(L) t H(H) t H(L) DATA INPUT t SU(H) t SU(L) DATA INPUT t SU(H) t SU(L) 3V t TLH t THL t TLH t THL t PLH t PHL t PLH t PHL t REM SET, RESET OR PRESET t REM 3V SET, RESET OR PRESET IC C L 50pF IC C L 50pF FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 8

9 CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Test Circuits and Waveforms (Continued) 6ns DISABLE 6ns t r DISABLE 6ns t f ns 3V tplz t PZL t PLZ t PZL LOW TO OFF LOW TO OFF HIGH TO OFF t PHZ t PZH HIGH TO OFF t PHZ t PZH S ENABLED S DISABLED S ENABLED S ENABLED S DISABLED S ENABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 8. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW DISABLE IC WITH THREE- STATE R L = 1kΩ C L 50pF FOR t PLZ AND t PZL FOR t PHZ AND t PZH NOTE: Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is Output R L =1kΩ to, C L = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 9

14 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

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