CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

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1 Data sheet acquired from Harris Semiconductor SCHS188 January 1998 CD74HC534, CD74HCT534, CD74HC564, CD74HCT564 High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered [ /Title (CD74 HC534, CD74 HCT53 4, CD74 HC564, CD74 HCT56 Features Buffered Inputs Common Three-State Output-Enable Control Three-State Outputs Bus Line Driving Capability Typical Propagation Delay = 13ns at = 5V, C L = 15pF, T A = 25 o C (Clock to Output) Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Description The Harris CD74HC534, CD74HCT534, CD74HC564 and CD74HCT564 are high speed Octal D-Type Flip-Flops manufactured with silicon gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LSTTL loads. Due to the large output drive capability and the three-state feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. The two types are functionally identical and differ only in their pinout arrangements. The CD74HC534, CD74HCT534, CD74HC564 and CD74HCT564 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are inverted and transferred to the Q outputs on the positive going transition of the CLOCK input. When a high logic level is applied to the ENABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The CD74HCT logic family is speed, function, and pin compatible with the standard 74LS logic family. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CD74HC534E -55 to Ld PDIP E20.3 CD74HCT534E -55 to Ld PDIP E20.3 CD74HC564E -55 to Ld PDIP E20.3 CD74HCT564E -55 to Ld PDIP E20.3 CD74HC564M -55 to Ld SOIC M20.3 CD74HCT564M -55 to Ld SOIC M20.3 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinouts CD74HC534, CD74HCT534 (PDIP) CD74HC564, CD74HCT564 (PDIP, SOIC) TOP VIEW TOP VIEW OE 1 20 OE 1 20 Q Q7 D Q0 D0 D1 Q1 Q2 D2 D3 Q D7 D6 Q6 Q5 D5 D4 Q4 D1 D2 D3 D4 D5 D6 D Q1 Q2 Q3 Q4 Q5 Q6 Q CP CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation File Number

2 Functional Diagram CD74HC534, CD74HCT534, CD74HC564, CD74HCT564 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP CP OE Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 O 7 TRUTH TABLE S OE CP Dn Qn L H L L L H L L X No Change H X X Z NOTE: H = High Level (Steady State) L = Low Level (Steady State) X = Don t Care = Transition from Low to High Level Z = High Impedance State 2

3 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Drain, per Output, I O For -0.5V < V O < + 0.5V ±35mA DC Output Source or Sink per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 3) θ JA ( o C/W) PDIP Package SOIC Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage SYMBOL TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o CTO125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V IH or V IL V V V V V V V OL V IH or V IL V V V I I or V V V ±0.1 - ±1 - ±1 µa 3

4 DC Electrical Specifications (Continued) PARAMETER Quiescent Device Three- State Leakage HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Quiescent Device Three- State Leakage Additional Quiescent Device Per Input Pin: 1 Unit Load SYMBOL I CC V IL or V IH or V O = or V IH to 5.5 V IL to µa ±0.5 - ±5.0 - ±10 µa V V V OH V IH or V IL V V V OL V IH or V IL V I I I CC V IL or V IH I CC TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o CTO125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX and or V O = or V ±0.1 - ±1 - ±1 µa µa ±0.5 - ±5.0 - ±10 µa to 5.5 NOTE: For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table µa UNIT LOADS D0 - D CP 0.30 OE 0.55 NOTE: Unit load is I CC limit specific in DC Electrical Specifications Table, e.g., 360µA max. at 25 o C. 4

5 Prerequisite for Switching Specifications 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX HC TYPES Maximum Clock Frequency f MAX MHz MHz MHz Clock Pulse Width t W ns ns ns Setup Time Data to Clock t SU ns ns ns Hold Time Data to Clock t H ns ns ns HCT TYPES Maximum Clock Frequency f MAX MHz Clock Pulse Width t W ns Setup Time Data to Clock Hold Time Data to Clock (534) Hold Time Data to Clock (564) t SU ns t H ns t H ns Switching Specifications C L = 50pF, Input t r, t f = 6ns PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay t PLH, t PHL C L = 50pF Clock to Output ns ns C L = 15pF ns C L = 50pF ns Output Disable to Q (534) t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns 5

6 Switching Specifications C L = 50pF, Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX Output Disable to Q (564) t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Output Enable to Q t PZL,t PZH C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Maximum Clock Frequency f MAX C L = 15pF MHz Output Transition Time t THL, t TLH C L = 50pF ns ns ns Input Capacitance C I C L = 50pF pf Three-State Output Capacitance Power Dissipation Capacitance (Notes 4, 5) C O pf C PD pf HCT TYPES Propagation Delay t PHL, t PLH Clock to Output C L = 50pF ns C L = 15pF ns Output Disable to Q t PLZ,t PHZ C L = 50pF ns C L = 15pF ns Output Enable to Q t PZL,t PZH C L = 50pF ns C L = 15pF ns Maximum Clock Frequency f MAX C L = 15pF MHz Output Transition Time t TLH, t THL C L = 50pF ns Input Capacitance C I C L = 50pF pf Three-State Output Capacitance Power Dissipation Capacitance (Notes 4, 5) C O pf C PD pf NOTES: 4. C PD is used to determine the dynamic power consumption, per package. 5. P D =C PD V 2 CC fi + C L V 2 CC fo where f i = Input Frequency, f O = Output Frequency, C L = Output Load Capacitance, = Supply. 6

7 Test Circuits and Waveforms t r C L CLOCK t f C L I t WL + t WH = fcl t r C L = 6ns CLOCK t f C L = 6ns I t WL + t WH = fcl 2.7V t WL t WH t WL t WH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH t r = 6ns t f = 6ns t r = 6ns t f = 6ns 2.7V 0. t THL t TLH t THL t TLH INVERTING t PHL t PLH INVERTING t PHL t PLH FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC CLOCK t r C L t f C L CLOCK t r C L 2.7V 0. t f C L t H(H) t H(L) t H(H) t H(L) DATA t SU(H) t SU(L) DATA t SU(H) t SU(L) t TLH t THL t TLH t THL t PLH t PHL t PLH t PHL t REM SET, RESET OR PRESET t REM SET, RESET OR PRESET IC C L 50pF IC C L 50pF FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7

8 Test Circuits and Waveforms (Continued) 6ns DISABLE 6ns t r DISABLE 6ns t f ns tplz t PZL t PLZ t PZL LOW TO OFF LOW TO OFF HIGH TO OFF t PHZ t PZH HIGH TO OFF t PHZ t PZH S ENABLED S DISABLED S ENABLED S ENABLED S DISABLED S ENABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 8. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OTHER S TIED HIGH OR LOW DISABLE IC WITH THREE- STATE R L = 1kΩ C L 50pF FOR t PLZ AND t PZL FOR t PHZ AND t PZH NOTE: Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is Output R L =1kΩto, C L = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8

9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated

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