CD54HC273, CD74HC273, CD54HCT273, CD74HCT273

Transcription

1 Data sheet acquired from Harris Semiconductor SCHS174B February Revised May 2003 CD54HC273, CD74HC273, CD54HCT273, CD74HCT273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset [ /Title (CD74 HC273, CD74 HCT27 3) /Subject (High Speed CMOS Logic Octal D- Type Flip- Features Common Clock and Asynchronous Master Reset Positive Edge Triggering Buffered Inputs Fanout (Over Temperature Range) - Standard Outputs LS - Bus Driver Outputs LS Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Description The HC273 and HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits. Information at the D inputis transferred to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs are reset to a logic 0. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC273F3A -55 to Ld CERDIP CD74HC273E -55 to Ld PDIP CD74HC273M -55 to Ld SOIC CD74HC273M96-55 to Ld SOIC CD54HCT273F3A -55 to Ld CERDIP CD74HCT273E -55 to Ld PDIP CD74HCT273M -55 to Ld SOIC CD74HCT273M96-55 to Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. Pinout CD54HC273, CD54HCT273 (CERDIP) CD74HC273, CD74HCT273 (PDIP, SOIC) TOP VIEW MR 1 20 Q Q7 D D7 D D6 Q Q6 Q Q5 D D5 D D4 Q Q CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2003, Texas Instruments Incorporated 1

2 Functional Diagram CP D0 Q0 D1 Q1 D2 Q2 S D3 D4 Q3 Q4 S D5 Q5 D6 Q6 D7 Q7 RESET MR TRUTH TABLE S RESET (MR) CP D n Q L X X L H H H H L L H L X Q 0 H = High Level, L = Low Level, X = Don t Care, = Transition from Low to High Level, Q 0 = Level Before the Indicated Steady-State Input Conditions Were Established. 2

3 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Drain, per Output, I O For -0.5V < V O < + 0.5V ±25mA DC Output Source or Sink per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 1) θ JC ( o C/W) E (PDIP) Package M (SOIC) Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications HC TYPES High Level Input Low Level Input Input Leakage Quiescent Device V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V OL I I I CC V IH or V V IL V V V V V IH or V V IL V V or or V V ±0.1 - ±1 - ±1 µa µa 3

4 DC Electrical Specifications (Continued) HCT TYPES High Level Input Low Level Input Input Leakage Quiescent Device Additional Quiescent Device Per Input Pin: 1 Unit Load V IH to 5.5 V IL to 5.5 V OH V OL I I I CC I CC (Note 2) V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V V V IH or V V IL V V IH or V V IL to or V ±0.1 - ±1 - ±1 µa µa to 5.5 NOTE: 2. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table µa UNIT LOADS MR 1.5 Data 0.4 CP 1.5 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25 o C. Prerequisite For Switching Specifications HC TYPES Maximum Clock Frequency (Figure 1) MR Pulse Width (Figure 1) (V) MIN TYP MAX MIN MAX MIN MAX f MAX MHz MHz MHz t W ns ns ns 4

5 Prerequisite For Switching Specifications (Continued) Clock Pulse Width (Figure 1) t W ns ns ns Set-up Time Data to Clock t SU ns (Figure 5) ns ns Hold Time, Data to Clock t H ns (Figure 5) ns ns Removal Time, MR to Clock t REM ns ns ns HCT TYPES Maximum Clock Frequency (Figure 2) f MAX MHz MR Pulse Width (Figure 2) t w ns Clock Pulse Width (Figure 2) t w ns Set-up Time Data to Clock t SU ns (Figure 6) Hold Time, Data to Clock (Figure 6) t H ns Removal Time, MR to Clock t REM ns Switching Specifications Input t r, t f = 6ns (V) MIN TYP MAX MIN MAX MIN MAX (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX HC TYPES Clock to Output (Figure 3), C L = 50pF ns ns ns C L = 15pF ns MR to Output (Figure 3) Output Transition Time (Figure 3) C L = 50pF ns ns ns, C L = 50pF ns ns ns Input Capacitance C I pf Maximum Clock Frequency f MAX C L = 15pF MHz 5

6 Switching Specifications Input t r, t f = 6ns (Continued) (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX Power Dissipation Capacitance (Notes 3, 4) HCT TYPES Clock to Output (Figure 4) MR to Output (Figure 4) C PD pf, C L = 50pF ns C L = 15pF ns C L = 50pF ns Output Transition Time, C L = 50pF ns Input Capacitance C IN pf Maximum Clock Frequency f MAX C L = 15pF MHz Power Dissipation Capacitance (Notes 3, 4) C PD pf NOTES: 3. C PD is used to determine the dynamic power consumption, per flip-flop. 4. P D =C PD V 2 CC fi + (C L V 2 CC +fo ) where f i = Input Frequency, f O = Output Frequency, C L = Output Load Capacitance, = Supply. Test Circuits and Waveforms t r C L t f C L I t WL + t WH = fcl t r C L = 6ns t f C L = 6ns I t WL + t WH = fcl 2.7V t WL t WH t WL t WH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 1. HC PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 2. HCT PULSE RISE AND FALL TIMES AND PULSE WIDTH t r = 6ns t f = 6ns t r = 6ns t f = 6ns 2.7V 0. INVERTING INVERTING FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA- TION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6

7 Test Circuits and Waveforms (Continued) t r C L t f C L t r C L 2.7V 0. t f C L t H(H) t H(L) t H(H) t H(L) t SU(H) t SU(L) t SU(H) t SU(L) t REM SET, RESET OR PRESET t REM SET, RESET OR PRESET IC C L 50pF IC C L 50pF FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7