INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Transcription

1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines File under Integrated Circuits, IC06 December 1990

2 FEATURES Output capability: standard I CC category: MSI GENERAL DESCRIPTION The are high-speed Si-gate CMOS devices and are pin compatible with 4040 of the 4000B series. They are specified in compliance with JEDEC standard no. 7A. The are s with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q 0 to Q 11 ). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. APPLICATIONS Frequency dividing circuits Time delay circuits Control counters QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS HC HCT UNIT t PHL / t PLH propagation delay C L = 15 pf; V CC =5 V CP to Q 0 16 ns Q n to Q n ns f max maximum clock frequency MHz C I input capacitance pf C PD power dissipation capacitance per package notes 1 and 2 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz f o = output frequency in MHz (C L V 2 CC f o ) = sum of outputs C L = output load capacitance in pf V CC = supply voltage in V 2. For HC the condition is V I = GND to V CC For HCT the condition is V I = GND to V CC 1.5 V ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December

3 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 8 GND ground (0 V) 9, 7, 6, 5, 3, 2, 4, 13, 12,, 15, 1 Q 0 to Q 11 parallel outputs 10 CP clock input (HIGH-to-LOW, edge-triggered) 11 MR master reset input (active HIGH) 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December

4 FUNCTION TABLE INPUTS OUTPUTS CP MR Q n X L L H no change count L Fig.4 Functional diagram. Notes 1. H = HIGH voltage level L = LOW voltage level X = don t care = LOW-to-HIGH clock transition = HIGH-to-LOW clock transition Fig.5 Logic diagram. Fig.6 Timing diagram. December

5 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard I CC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; t r =t f = 6 ns; C L = 50 pf SYMBOL t PHL / t PLH t PHL / t PLH t PHL PARAMETER propagation delay 47 CP to Q 0 17 propagation delay 28 Q n to Q n propagation delay 61 MR to Q n t THL / t TLH output transition time t rem f max clock pulse width HIGH or LOW master reset pulse width; HIGH removal time MR to CP maximum clock pulse frequency T amb ( C) 74HC to to +125 min. typ. max. min. max. min. max UNIT TEST CONDITIONS V CC (V) MHz 2.0 WAVEFORMS December

6 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS Logic Family Specifications. Output capability: standard I CC category: MSI Note to HCT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT CP MR UNIT LOAD COEFFICIENT AC CHARACTERISTICS FOR 74HCT GND = 0 V; t r =t f = 6 ns; C L = 50 pf T amb ( C) TEST CONDITIONS ns ns ns 74HCT SYMBOL PARAMETER UNIT V WAVEFORMS to to +125 CC (V) min. typ. max. min. max. min. max. t PHL / t PLH propagation delay CP to Q 0 t PHL / t PLH propagation delay Q n to Q n+1 t PHL propagation delay MR to Q n t THL / t TLH output transition time ns t rem f max clock pulse width HIGH or LOW master reset pulse width; HIGH removal time MR to CP maximum clock pulse frequency 16 7 ns 16 6 ns ns MHz December

7 AC WAVEFORMS (1) HC : V M = 50%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Waveforms showing the clock (CP) to output (Q n ) propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency. Also showing the master reset (MR) pulse width, the master reset to output (Q n ) propagation delays and the master reset to clock (CP) removal time. PACKAGE OUTLINES See 74HC/HCT/HCU/HCMOS Logic Package Outlines. December