Obsolete Product(s) - Obsolete Product(s)
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- Cornelius Baker
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1 7 STAGE BINARY COUNTER HIGH SPEED : f MAX = 79 MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: I OH = I OL = 4mA (MIN) BALANCED PROPAGATION DELAYS: t PLH t PHL WIDE OPERATING VOLTAGE RANGE: V CC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4024 DESCRIPTION The M74HC4024 is an high speed CMOS 7 STAGE BINARY COUNTER fabricated with silicon gate C 2 MOS technology. This devices is incremented on the falling edge (negative traition) of the input clock, and all its PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES TSSOP PACKAGE TUBE T & R DIP M74HC4024B1R SOP M74HC4024M1R M74HC4024RM13TR TSSOP M74HC4024TTR outputs are reset to a low level by applying a logical high level on their reset input (CLEAR). All inputs are equipped with protection circuits agait static discharge and traient excess voltage. DIP SOP July /10
2 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION TRUTH TABLE LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditio is not implied (*) 500mW at 65 C; derate to 300mW by 10mW/ C from 65 C to 85 C 2/10 PIN No SYMBOL NAME AND FUNCTION 1 CLOCK Clock Input (HIGH to LOW, Edge-triggered) 2 CLEAR Reser Input (Active High) 12, 11, 9, 6, 5, 4, 3 Q1 to Q7 Parallel Inputs 8, 10, 13 NC Not Connected 7 GND Ground (0V) 14 Vcc Positive Supply Voltage CLOCK CLEAR OUTPUT STATE X H ALL OUTPUTS = "L" L NO CHANGE L ADVANCE TO NEXT STATE Symbol Parameter Value Unit V CC Supply Voltage -0.5 to +7 V V I DC Input Voltage -0.5 to V CC V V O DC Output Voltage -0.5 to V CC V I IK DC Input Diode Current ± 20 ma I OK DC Output Diode Current ± 20 ma I O DC Output Current ± 25 ma I CC or I GND DC V CC or Ground Current ± 50 ma P D Power Dissipation 500(*) mw T stg Storage Temperature -65 to +150 C T L Lead Temperature (10 sec) 300 C
3 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit V CC Supply Voltage 2 to 6 V V I Input Voltage 0 to V CC V V O Output Voltage 0 to V CC V T op Operating Temperature -55 to 125 C t r, t f V CC = 4.5V 0 to 500 Input Rise and Fall Time V CC = 2.0V 0 to 1000 V CC = 6.0V 0 to 400 DC SPECIFICATIONS Symbol V IH V IL V OH V OL I I Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current V CC (V) Test Condition Value T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max I O =-20 µa I O =-20 µa I O =-20 µa I O =-4.0 ma I O =-5.2 ma I O =20 µa I O =20 µa I O =20 µa I O =4.0 ma I O =5.2 ma V I = V CC or GND ± 0.1 ± 1 ± 1 µa I CC 6.0 V I = V CC or GND µa Unit V V V V 3/10
4 AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = 6) Test Condition Value Symbol t TLH t THL t PLH t PHL t PLH t PHL t PHL f MAX t W(H) t W(L) t W(H) t REM Parameter Output Traition Time Propagation Delay Time (Qn - Qn+1) Propagation Delay Time (CLOCK -Q1) Propagation Delay Time (CLEAR - Qn) Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (CLEAR) Minimum Removal Time V CC (V) CAPACITIVE CHARACTERISTICS T A = 25 C -40 to 85 C -55 to 125 C Min. Typ. Max. Min. Max. Min. Max Test Condition 1) C PD is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating current coumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC Value Symbol Parameter V CC T A = 25 C -40 to 85 C -55 to 125 C Unit (V) Min. Typ. Max. Min. Max. Min. Max. C IN Input Capacitance pf C PD Power Dissipation Capacitance (note pf 1) Unit MHz 4/10
5 TEST CIRCUIT C L = 50pF or equivalent (includes jig and probe capacitance) R T = Z OUT of pulse generator (typically 50Ω) WAVEFORM 1 : MINIMUM PULSE WIDTH (CLEAR) AND REMOVAL TIME (f=1mhz; 50% duty cycle) 5/10
6 WAVEFORM 2 : PROPAGATION DELAY TIME (f=1mhz; 50% duty cycle) WAVEFORM 3 : MINIMUM PULSE WIDTH (CLOCK), PROPAGATION DELAY TIME (f=1mhz; 50% duty cycle) 6/10
7 Plastic DIP-14 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. a B b b D E e e F I L Z P001A 7/10
8 SO-14 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A a a b b C c1 45 (typ.) D E e e F G L M S 8 (max.) PO13G 8/10
9 TSSOP14 MECHANICAL DATA DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A A A b c D E E e 0.65 BSC BSC K L A A2 A1 b e D c K L E E1 PIN 1 IDENTIFICATION D 9/10
10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respoibility for the coequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licee is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificatio mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 10/ STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom
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