DATA SHEET. 74HC4050 Hex high-to-low level shifter. Product specification File under Integrated Circuits, IC06

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1 DATA SHEET File under Integrated Circuits, IC06 December 1990

2 Philips Semiconducts FEATURES Output capability: standard I CC categy: SSI GENERAL DESCRIPTION The is a high-speed Si-gate CMOS device and is pin compatible with the 4050 of the 4000B series. It is specified in compliance with JEDEC standard no. 7A. The provides six non-inverting buffers with a modified input protection structure, which has no diode connected to V CC. Input voltages of up to 15 V may therefe be used. This feature enables the non-inverting buffers to be used as logic level translats, which will convert high level logic to low level logic, while operating from a low voltage power supply. F example 15 V logic ( 4000B series ) can be converted down to 2 V logic. The actual input switch level remains related to the V CC and is the same as mentioned in the family characteristics. APPLICATIONS Converting 15 V logic ( 4000B series) down to 2 V logic. QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS HC t PHL / t PLH propagation delay na to ny C L = 15 pf; V CC = 5 V 7 ns C I input capacitance 3.5 pf C PD power dissipation capacitance per buffer note 1 14 pf UNIT Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C L V 2 CC f o ) where: f i = input frequency in MHz f o = output frequency in MHz C L = output load capacitance in pf V CC = supply voltage in V (C L V 2 CC f o ) = sum of outputs ORDERING INFORMATION See /HCT/HCU/HCMOS Logic Package Infmation. December

3 Philips Semiconducts PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 V CC positive supply voltage 2, 4, 6, 10, 12, 15 1Y to 6Y data outputs 3, 5, 7, 9, 11, 14 1A to 6A data inputs 8 GND ground (0 V) 13, 16 n.c. not connected Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December

4 Philips Semiconducts Fig.4 Functional diagram. Fig.5 Input protection f HC4050. Single sided thick oxide field effect metal gate transist as input protection. Fig.6 Logic diagram (one level shifter). FUNCTION TABLE (1) INPUT na L H OUTPUT ny L H Note 1. H = HIGH voltage level L = LOW voltage level December

5 Philips Semiconducts RATINGS Limiting values in accdance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS V CC DC supply voltage V V IK DC input voltage range V I IK DC input diode current 20 ma f V I < 0.5 V ±I OK DC output diode current 20 ma f V O < 0.5 V V O > V CC V ±I O DC output source sink current - standard outputs 25 ma f 0.5 V < V O < V CC V DC V ±I CC ; CC GND current f types with: ±I GND - standard outputs 50 ma T stg stage temperature range C power dissipation per package f temperature range: 40 to +125 C P tot plastic DIL 750 mw above +70 C: derate linearly with 12 mw/k plastic mini-pack (SO) 500 mw above +70 C: derate linearly with 8 mw/k RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER min. typ. max. UNIT CONDITIONS V CC DC supply voltage V V I DC input voltage range GND 15 V T amb operating ambient temperature range C see DC and AC T amb operating ambient temperature range C characteristics t r, t f input rise and fall times ns V CC = 2.0 V; V IN = 2.0 V V CC = V; V IN = V V CC = V; V IN = V V CC = V; V IN = 10.0 V V CC = V; V IN = 15.0 V December

6 Philips Semiconducts DC CHARACTERISTICS FOR Voltages are referenced to GND (ground = 0 V) T amb ( C) TEST CONDITIONS SYMBOL PARAMETER to to +125 min. typ. max. min. max. min. max. UNIT V CC (V) V I OTHER V OH V OH V OL V OL HIGH level input voltage LOW level input voltage HIGH level output voltage - all outputs HIGH level output voltage - standard outputs LOW level output voltage - all outputs LOW level output voltage - standard outputs ± I I input leakage current µa I CC quiescent supply current V V µa 2.0 to V CC GND 15 V µa 15 V GND I O =20µA I O =20µA I O =20µA I O = 4.0 ma I O = 5.2 ma I O =20µA I O =20µA I O =20µA I O = 4.0 ma I O = 5.2 ma December

7 Philips Semiconducts AC CHARACTERISTICS FOR GND = 0 V; t r =t f = 6 ns; C L = 50 pf SYMBOL t PHL / t PLH PARAMETER propagation delay na to ny T amb ( C) to to +125 min. typ. max. min. max. min. max t THL / t TLH output transition time UNIT TEST CONDITIONS V CC (V) ns 2.0 ns 2.0 WAVEFORMS Fig.7 Fig.7 AC WAVEFORMS (1) HC : V M = 50%; V I = GND to V CC. HCT: V M = 1.3 V; V I = GND to 3 V. Fig.7 Wavefms showing the input (na) to output (ny) propagation delays and the output transition times. PACKAGE OUTLINES See /HCT/HCU/HCMOS Logic Package Outlines. December

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