QS54/74FCT373T, 2373T. High-Speed CMOS Bus Interface 8-Bit Latches MDSL QUALITY SEMICONDUCTOR, INC. 1 DECEMBER 28, 1998

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1 Q QUALITY SEMICONDUCTOR, INC. QS54/74FCT373T, 2373T High-Speed CMOS Bus Interface 8-Bit Latches QS54/74FCT373T QS54/74FCT2373T FEATURES/BENEFITS Pin and function compatible to the 74F373 74FCT373 and 74ABT373 Industrial temperature 40 C to 85 C CMOS power levels: <7.5mW static Available in DIP, SOIC, QSOP, ZIP, HQSOP Undershoot clamp diodes on all inputs TTL-compatible input and output levels Ground bounce controlled outputs Reduced output swing of 0-3.5V Military product compliant to MIL-STD-883, Class B FCT-T 373T JEDEC-FCT spec compatible Std., A, C, and D speed grades with 3.7ns for D I OL = 48mA Ind., 32mA Mil. FCT-T 2373T Built-in 25Ω series resistor outputs reduce reflection and other system noise Std., C and D speed grades with 3.7ns for D I OL = 12mA Ind. Figure 1. Functional Block Diagram DESCRIPTION The QSFCT373T is an 8-bit high-speed CMOS TTLcompatible buffered latches with three-state outputs that are ideal for driving high capacitance loads such as memory and address buses. The 2373 is a 25Ω resistor output version useful for driving transmission lines and reducing system noise. The 2373 series parts can replace 373 devices in existing designs to reduce noise. All inputs have clamp diodes for undershoot noise suppression. All outputs have ground bounce suppression (see QSI Application Note AN- 001), and outputs will not load an active bus when is removed from the device. Di D Q 25Ω Oi FCT2373 Only MDSL QUALITY SEMICONDUCTOR, INC. 1 This datasheet has been downloaded from at this page

2 Figure 2. Pin Configurations (All Pins Top View) PDIP, SOIC, QSOP, HQSOP ZIP O0 D0 D1 O1 O2 D2 D3 O3 GND O7 D7 D6 O6 O5 D5 D4 O4 D0 O1 D2 O3 D4 O5 D6 O O0 D1 O2 D3 GND O4 D5 O6 D7 Table 1. Pin Description Name I/O Description Di I Data Inputs Oi O Data Outputs I Latch Enable I Output Enable Table 2. Function Table Internal Inputs Q Outputs Di Value Oi Function H X X X Hi-Z Disable Outputs L L X H H Enable Outputs L L X L L L H L L L Pass Inputs L H H H H L L X Q Q Hold Prior Data 2 QUALITY SEMICONDUCTOR, INC. MDSL

3 Table 3. Absolute Maximum Ratings Supply Voltage to Ground V to 7.0V DC Output Voltage V OUT V to 7.0V DC Input Voltage V IN V to 7.0V AC Input Voltage (for a pulse width 20ns) V DC Input Diode Current with V IN < mA DC Output Diode Current with V OUT < mA DC Output Current Max. Sink Current/Pin mA Maximum Power Dissipation watts T STG Storage Temperature to 150 C Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to QSI devices that result in functional or reliability type failures. Table 4. Capacitance (1) T A = 25 C, f = 1MHz, V IN = 0V, V OUT = 0V Pins (2) SOIC QSOP PDIP ZIP Unit 1, 3, 4, 7, 8, 11, 13, 14, 17, pf 2, 5, 6, 9, 12, 15, 16, pf 1. Capacitance is characterized but not tested. 2. Pin reference for 20-pin package. Table 5. Power Supply Characteristics Symbol Parameter Test Conditions (1) Min Max Unit I CC Quiescent Power = Max., freq = ma Supply Current 0V V IN 0.2V or -0.2V V IN I CC Supply Current per = Max., V IN = 3.4V, freq = 0 (2) 2.0 ma TTL HIGH Q CCD Supply Current per = Max., Outputs Open and Enabled 0.25 ma/ Input per MHz One Bit 50% Duty Cycle MHz Other Inputs at GND or V (3,4) CC 1. For conditions shown as Min. or Max., use the appropriate values specified under DC specifications. 2. Per TTL driven input (V IN = 3.4V). 3. For flip-flops, Q CCD is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of device power consumption only and does not include power to drive load capacitance or tester capacitance. This parameter is guaranteed by design but not tested. 4. I C can be computed using the above parameters as explained in the Technical Overview section. MDSL QUALITY SEMICONDUCTOR, INC. 3

4 Table 6. DC Electrical Characteristics Over Operating Range Industrial T A = 40 C to 85 C, = 5.0V ±5% Military T A = 55 C to 125 C, = 5.0V ±10% Symbol Parameter Test Conditions Min Typ (1) Max Unit V IH Input HIGH Voltage Logic HIGH for All Inputs 2.0 V V IL Input LOW Voltage Logic LOW for All Inputs 0.8 V V T Input Hysteresis V TLH V THL for All Inputs 0.2 V I IH Input Current = Max., 0 V IN < 5 µa I IL Input HIGH or LOW I OZ Off-State Output = Max., 0 V IN 5 µa Current (Hi-Z) I OS Short Circuit Current = Max., V OUT = GND (2,3) 60 ma (FCT373) I OR Current Drive = Min., V OUT = 2.0V (3) 50 ma (FCT Ω) V IC Input Clamp Voltage = Min., I IN = 18mA, T A = 25 C (3) V V OH Output HIGH Voltage = Min. I OH = 12mA (MIL) 2.4 V I OH = 15mA (IND) 2.4 V OL Output LOW Voltage = Min. I OL = 32mA (MIL) 0.50 V (FCT373) I OL = 48mA (IND) 0.50 VOL Output LOW Voltage = Min. I OL = 12mA (MIL) 0.50 V (FCT Ω) I OL = 12mA (IND) 0.50 R OUT Output Resistance = Min. I OL = 12mA (MIL) 25 Ω (FCT Ω) I OL = 12mA (IND) Typical values indicate = 5.0V and T A = 25 C. 2. Not more than one output should be shorted and the duration is 1 second. 3. These parameters are guaranteed by design but not tested. 4 QUALITY SEMICONDUCTOR, INC. MDSL

5 Table 7. Switching Characteristics Over Operating Range Industrial T A = 40 C to 85 C, = 5.0V ±5% Military T A = 55 C to 125 C, = 5.0V ±10% C LOAD = 50pF, R LOAD = 500Ω unless otherwise noted A 373C 373D A 2373C 2373D Symbol Description (1) Min Max Min Max Min Max Min Max Unit t PHL Propagation Delay IND ns t PLH Data to Oi, 373 MIL t PHL Propagation Delay IND ns t PLH Data to Oi, 2373 MIL t PHL Propagation Delay IND ns t PLH to Oi, 373 MIL t PHL Propagation Delay IND ns t PLH to Oi, 2373 MIL t PZH Output Enable Time IND ns t PZL to Yi, 373 MIL t PZH Output Enable Time IND ns tpzl to Yi, 2373 MIL t PHZ Output Disable Time IND (2) ns t PLZ to Yi MIL (2) t S Data Setup Time IND ns MIL t H Data Hold Time IND ns MIL t W Pulse Width IND (2) ns HIGH or LOW MIL (2) Minimums guaranteed but not tested for all parameters except t S and t H. 2. This parameter is guaranteed by design but not tested. 3. See Test Circuit and Waveforms. MDSL QUALITY SEMICONDUCTOR, INC. 5

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