CD54/74HC175, CD54/74HCT175

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Buck Quinn
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CD54/74HC175, CD54/74HCT175 Data sheet acquired from Harris Semiconductor SCHS160A August 1997 - evised May 2000 High Speed CMOS Logic uad D-Type Flip-Flop with eset [ /Title (CD74 HC175, CD74 HCT17

1 CD54/74HC175, CD54/74HCT175 Data sheet acquired from Harris Semiconductor SCHS160A August evised May 2000 High Speed CMOS Logic uad D-Type Flip-Flop with eset [ /Title (CD74 HC175, CD74 HCT17 5) /Subject High peed MOS ogic uad - ype lip- Features Common Clock and Asynchronous eset on Four D-Type Flip-Flops Positive Edge Pulse Triggering Complementary Outputs Buffered Inputs Typical f MAX = 50MHz at = 5V, = 15pF, T A = 25 o C Fanout (Over Temperature ange) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature ange o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power eduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Description The HC175 and HCT175 are high speed uad D-type Flip- Flops with individual D-inputs and, complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices. Information at the D input is transferred to the, outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock () and a common reset (M). esetting is accomplished by a low voltage level independent of the clock. All four outputs are reset to a logic 0 and all four outputs to a logic 1. Ordering Information PAT NUMBE TEMP. ANGE ( o C) PACKAGE CD54HC175F3A -55 to Ld CEDIP CD74HC175E -55 to Ld PDIP CD74HC175M -55 to Ld SOIC CD54HCT175F3A -55 to Ld CEDIP CD74HCT175E -55 to Ld PDIP CD74HCT175M -55 to Ld SOIC CD74HCT175W -55 to 125 Wafer NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2000, Texas Instruments Incorporated 1

2 Pinout CD54HC175, CD54HCT175 (CEDIP) CD74HC175, CD74HCT175 (PDIP, SOIC) TOP VIEW M 0 0 D 0 D D 3 D Functional Diagram 4 D 0 9 M 1 D D 1 5 D D 2 D D 3 D TUTH TABLE S OUTPUTS ESET (M) CLOCK DATA D n n n L X X L H H H H L H L L H H L X 0 0 NOTE: H = High Level, L = Low Level, X = Don t Care, = Transition from Low to High Level, 0 = Level Before the Indicated Steady-State Input Conditions Were Established. 2

3 Logic Diagram ONE OF FOU F/F 4 (5, 12, 13) D D n p n p n 3( 6, 11, 14) n p n p n 2( 7, 10, 15) n 1 M 9 TO OTHE THEE F/F TO OTHE THEE F/F

4 Absolute Maximum atings DC Supply, V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground Current, I CC or I ±50mA Thermal Information Thermal esistance (Typical, Note 3) θ JA ( o C/W) PDIP Package SOIC Package Maximum Junction Temperature o C Maximum Storage Temperature ange o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature ange (T A ) o C to 125 o C Supply ange, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input ise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum atings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current uiescent Device Current 25 o C -40 o C TO +85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V OL I I I CC V IH or V V IL V V V V V IH or V V IL V V or or V V ±0.1 - ±1 - ±1 µa µa 4

5 DC Electrical Specifications (Continued) HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current uiescent Device Current Additional uiescent Device Current Per Input Pin: 1 Unit Load (Note 4) V IH to 5.5 V IL to 5.5 V OH V OL I I I CC I CC 25 o C -40 o C TO +85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V V V IH or V V IL V V IH or V V IL to or V ±0.1 - ±1 - ±1 µa µa to 5.5 NOTES: 4. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. 5. Die for this part number is available which meets all electrical specifications. HCT Input Loading Table µa UNIT LOADS M D 0.15 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g. 360µA max at 25 o C. Prerequisite For Switching Specifications 25 o C -40 o C TO 85 o C -55 o C TO 125 o C (V) MIN TYP MAX MIN MAX MIN MAX HC TYPES Clock Pulse Width t w ns ns ns M Pulse Width t w ns ns ns 5

6 Prerequisite For Switching Specifications (Continued) Setup Time, Data to Clock t SU ns ns ns Hold Time, Data to Clock t H ns ns ns emoval Time, M to Clock t EM ns ns ns Clock Frequency f MAX MHz MHz MHz HCT TYPES Clock Pulse Width t w ns M Pulse Width t w ns Setup Time Data to Clock t SU ns Hold Time Data to Clock t H ns emoval Time M to Clock t EM ns Clock Frequency f MAX MHz Switching Specifications Input t r, t f = 6ns (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX HC TYPES Propagation Delay, Clock to or t PLH, t PHL = 50pF ns ns ns = 15pF ns Propagation Delay, M to or t PLH, t PHL = 50pF ns ns ns = 15pF ns Output Transition Times t TLH, t THL = 50pF ns ns ns Input Capacitance C IN pf Power Dissipation Capacitance (Notes 6, 7) C PD pf 6

7 Switching Specifications Input t r, t f = 6ns (Continued) (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C TYP MAX MAX MAX HCT TYPES Propagation Delay, Clock to or Propagation Delay, M to or t PLH, t PHL = 50pF ns = 15pF ns t PLH, t PHL = 50pF ns = 15pF ns Output Transition Times t TLH, t THL = 50pF ns Input Capacitance C IN pf Power Dissipation Capacitance (Notes 6, 7) C PD pf NOTES: 6. C PD is used to determine the dynamic power consumption, per flip-flop. 7. P D =V 2 CC fi + ( V 2 CC +fo ) where f i = Input Frequency, f O = Input Frequency, = Output Load Capacitance, = Supply. Test Circuits and Waveforms CLOCK t r 10% t f 50% CLOCK t r 2.7V 0.3V t f 3V t H(H) t H(L) t H(H) t H(L) DATA t SU(H) t SU(L) 50% DATA t SU(H) t SU(L) 3V OUTPUT t TLH t THL 50% 10% OUTPUT t TLH t THL 10% t PLH t PHL t PLH t PHL t EM SET, ESET 50% O PESET t EM 3V SET, ESET O PESET IC 50pF IC 50pF FIGUE 1. HC SETUP TIMES, HOLD TIMES, EMOVAL TIME, AND POPAGATION DELAY TIMES FO EDGE TIGGEED SEUENTIAL LOGIC CICUITS FIGUE 2. HCT SETUP TIMES, HOLD TIMES, EMOVAL TIME, AND POPAGATION DELAY TIMES FO EDGE TIGGEED SEUENTIAL LOGIC CICUITS 7

8 IMPOTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated

CD54/74HC74, CD54/74HCT74

CD54/74HC74, CD54/74HCT74 Data sheet acquired from Harris Semiconductor SCHS124A January 1998 - Revised May 2000 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger Features Description [ /Title