CD74HC374, CD74HCT374, CD74HC574, CD74HCT574

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ata sheet acquired from Harris Semiconductor SCHS183 February 1998 C74HC374, C74HCT374, C74HC574, C74HCT574 High Speed CMOS Logic Octal -Type Flip-Flop, Three-State Positive-Edge Triggered [ /Title

15ns at = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs............... 10 LSTTL Loads - Bus river Outputs............. 15 LSTTL Loads Wide Operating Temperature Range.

1 ata sheet acquired from Harris Semiconductor SCHS183 February 1998 C74HC374, C74HCT374, C74HC574, C74HCT574 High Speed CMOS Logic Octal -Type Flip-Flop, Three-State Positive-Edge Triggered [ /Title (C74 HC374, C74 HCT37 4, C74 HC574, C74 HCT57 Features Buffered Inputs Common Three-State Output Enable Control Three-State Outputs Bus Line riving Capability Typical Propagation elay (Clock to Q) = 15ns at = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus river Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation elay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - irect LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH escription The Harris C74HC374, C74HCT374, C74HC574 and C74HCT574 are Octal -Type Flip-Flops with Three-State Outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the LOW to HIGH transition of clock (CP). The Output Enable (OE) controls the three-state outputs and is independent of the register operation. When Output Enable (OE) is HIGH the outputs will be in the high impedance state. The 374 and 574 are identical in function and differ only in their pinout arrangements. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. C74HC374E -55 to Ld PIP E20.3 C74HCT374E -55 to Ld PIP E20.3 C74HCT574E -55 to Ld PIP E20.3 C74HC574E -55 to Ld PIP E20.3 C74HC574M -55 to Ld SOIC M20.3 C74HC374M -55 to Ld SOIC M20.3 C74HCT374M -55 to Ld SOIC M20.3 C74HCT574M -55 to Ld SOIC M20.3 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. Pinouts C74HC374, C74HCT374 (PIP, SOIC) TOP VIEW C74HCT574 (PIP, SOIC) TOP VIEW OE 1 20 OE 1 20 Q Q Q Q Q2 Q Q Q3 Q Q Q Q Q6 Q Q Q CP CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation File Number

2 C74HC374, C74HCT374, C74HC574, C74HCT574 Functional iagram CP OE Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 TRUTH TABLE S OE CP n Qn L H H L L L L L X Q0 H X X Z NOTE: H = High Level (Steady State) L = Low Level (Steady State) X = on t Care = Transition from Low to High Level Q0 = The level of Q before the indicated steady-state input conditions were established Z = High Impedance State 2

3 C74HC374, C74HCT374, C74HC574, C74HCT574 Absolute Maximum Ratings C Supply, V to 7V C Input iode, I IK For V I < -0.5V or V I > + 0.5V ±20mA C Output iode, I OK For V O < -0.5V or V O > + 0.5V ±20mA C rain, per Output, I O For -0.5V < V O < + 0.5V ±35mA C Output Source or Sink per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA C or Ground, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 3) θ JA ( o C/W) PIP Package SOIC Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V C Input or Output, V I, V O V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θ JA is measured with the component mounted on an evaluation PC board in free air. C Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage SYMBOL TEST CONITIONS 25 o C -40 o C TO 85 o C -55 o CTO125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V IH or V IL V V V V V V V OL V IH or V IL V V V I I or V V V ±0.1 - ±1 - ±1 µa 3

4 C74HC374, C74HCT374, C74HC574, C74HCT574 C Electrical Specifications (Continued) PARAMETER Quiescent evice Three- State Leakage HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Quiescent evice Three- State Leakage Additional Quiescent evice Per Input Pin: 1 Unit Load SYMBOL I CC V IL or V IH or V O = or V IH to 5.5 V IL to µa ±0.5 - ±5.0 - ±10 µa V V V OH V IH or V IL V V V OL V IH or V IL V I I I CC V IL or V IH I CC TEST CONITIONS 25 o C -40 o C TO 85 o C -55 o CTO125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX and or V O = or V ±0.1 - ±1 - ±1 µa µa ±0.5 - ±5.0 - ±10 µa to 5.5 NOTE: For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table UNIT LOAS µa HCT374 HCT CP OE NOTE: Unit load is I CC limit specific in C Electrical Specifications Table, e.g., 360µA max. at 25 o C. 4

5 C74HC374, C74HCT374, C74HC574, C74HCT574 Prerequisite for Switching Specifications PARAMETER SYMBOL (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN TYP MAX MIN TYP MAX HC TYPES Maximum Clock Frequency f MAX MHz MHz MHz Clock Pulse Width t W ns ns ns Setup Time ata to Clock t SU ns ns ns Hold Time ata to Clock t H ns ns ns HCT TYPES Maximum Clock Frequency f MAX MHz Clock Pulse Width t W ns Setup Time ata to Clock Hold Time ata to Clock t SU ns t H ns Switching Specifications C L = 50pF, Input t r, t f = 6ns PARAMETER SYMBOL TEST CONITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation elay t PLH, t PHL C L = 50pF Clock to Output ns ns C L = 15pF ns C L = 50pF ns Output isable to Q t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns 5

6 C74HC374, C74HCT374, C74HC574, C74HCT574 Switching Specifications C L = 50pF, Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX Output Enable to Q t PZL,t PZH C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Maximum Clock Frequency f MAX C L = 15pF MHz Output Transition Time t THL, t TLH C L = 50pF ns ns ns Input Capacitance C I C L = 50pF pf Three-State Output Capacitance Power issipation Capacitance (Notes 4, 5) C O pf C P C L = 15pF pf HCT TYPES Propagation elay t PHL, t PLH Clock to Output C L = 50pF ns C L = 15pF ns Output isable to Q t PLZ,t PHZ C L = 50pF ns C L = 15pF ns Output Enable to Q t PZL,t PZH C L = 50pF ns C L = 15pF ns Maximum Clock Frequency f MAX C L = 15pF MHz Output Transition Time t TLH, t THL C L = 50pF ns Input Capacitance C I C L = 50pF pf Three-State Output Capacitance Power issipation Capacitance (Notes 4, 5) C O pf C P C L = 15pF pf NOTES: 4. C P is used to determine the dynamic power consumption, per package. 5. P =C P V 2 CC fi + V 2 CC fo C L where f i = Input Frequency, f O = Output Frequency, C L = Output Load Capacitance, = Supply. 6

7 C74HC374, C74HCT374, C74HC574, C74HCT574 Test Circuits and Waveforms t r C L CLOCK t f C L I t WL + t WH = fcl t r C L = 6ns CLOCK t f C L = 6ns I t WL + t WH = fcl 2.7V t WL t WH t WL t WH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 1. HC CLOCK PULSE RISE AN FALL TIMES AN PULSE WITH NOTE: Outputs should be switching from to in accordance with device truth table. For f MAX, input duty cycle =. FIGURE 2. HCT CLOCK PULSE RISE AN FALL TIMES AN PULSE WITH t r = 6ns t f = 6ns t r = 6ns t f = 6ns 2.7V 0. t THL t TLH t THL t TLH INVERTING t PHL t PLH INVERTING t PHL t PLH FIGURE 3. HC TRANSITION TIMES AN PROPAGATION ELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AN PROPAGATION ELAY TIMES, COMBINATION LOGIC CLOCK t r C L t f C L CLOCK t r C L 2.7V 0. t f C L t H(H) t H(L) t H(H) t H(L) ATA t SU(H) t SU(L) ATA t SU(H) t SU(L) t TLH t THL t TLH t THL t PLH t PHL t PLH t PHL t REM SET, RESET OR PRESET t REM SET, RESET OR PRESET IC C L 50pF IC C L 50pF FIGURE 5. HC SETUP TIMES, HOL TIMES, REMOVAL TIME, AN PROPAGATION ELAY TIMES FOR EGE TRIGGERE SEQUENTIAL LOGIC CIRCUITS FIGURE 6. HCT SETUP TIMES, HOL TIMES, REMOVAL TIME, AN PROPAGATION ELAY TIMES FOR EGE TRIGGERE SEQUENTIAL LOGIC CIRCUITS 7

8 C74HC374, C74HCT374, C74HC574, C74HCT574 Test Circuits and Waveforms (Continued) 6ns ISABLE 6ns t r ISABLE 6ns t f ns tplz t PZL t PLZ t PZL LOW TO OFF LOW TO OFF HIGH TO OFF t PHZ t PZH HIGH TO OFF t PHZ t PZH S ENABLE S ISABLE S ENABLE S ENABLE S ISABLE S ENABLE FIGURE 7. HC THREE-STATE PROPAGATION ELAY WAVEFORM FIGURE 8. HCT THREE-STATE PROPAGATION ELAY WAVEFORM OTHER S TIE HIGH OR LOW ISABLE IC WITH THREE- STATE R L = 1kΩ C L 50pF FOR t PLZ AN t PZL FOR t PHZ AN t PZH NOTE: Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is Output R L =1kΩto, C L = 50pF. FIGURE 9. HC AN HCT THREE-STATE PROPAGATION ELAY TEST CIRCUIT 8

9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONUCTOR PROUCTS MAY INVOLVE POTENTIAL RISKS OF EATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL AMAGE ( CRITICAL APPLICATIONS ). TI SEMICONUCTOR PROUCTS ARE NOT ESIGNE, AUTHORIZE, OR WARRANTE TO BE SUITABLE FOR USE IN LIFE-SUPPORT EVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PROUCTS IN SUCH APPLICATIONS IS UNERSTOO TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated

CD74HC374, CD74HCT374, CD74HC574, CD74HCT574

CD74HC374, CD74HCT374, CD74HC574, CD74HCT574 ata sheet acquired from Harris Semiconductor SCHS183 February 1998 C74HC374, C74HCT374, C74HC574, C74HCT574 High Speed CMOS Logic Octal -Type Flip-Flop, Three-State Positive-Edge Triggered Features escription