CD4051B, CD4052B, CD4053B

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Data sheet acquired from Harris Semiconductor SCHS0G August - Revised October 00 [ /Title (CD0 B, CD0 B, CD0 B) /Subject (CMOS Analog Multiplexers/Dem ultiplexers with Logic Level Conversion) /Author

1 Data sheet acquired from Harris Semiconductor SCHS0G August - Revised October 00 [ /Title (CD0 B, CD0 B, CD0 B) /Subject (CMOS Analog Multiplexers/Dem ultiplexers with Logic Level Conversion) /Author () /Keywords (Harris Semiconductor, CD000 Features Wide Range of Digital and Analog Signal Levels - Digital V to 0V - Analog V P-P Low ON Resistance, Ω (Typ) Over V P-P Signal Input Range for - = V High OFF Resistance, Channel Leakage of ±00pA (Typ) at - = V Logic-Level Conversion for Digital Addressing Signals of V to 0V ( - = V to 0V) to Switch Analog Signals to 0V P-P ( - = 0V) Matched Switch Characteristics, r ON = Ω (Typ) for - = V Very Low Quiescent Power Dissipation Under All Digital- Control Input and Supply Conditions, 0.µW (Typ) at - = - = 0V Binary Address Decoding on Chip V, 0V, and V Parametric Ratings 00% Tested for Quiescent Current at 0V Maximum Input Current of µa at V Over Full Package Temperature Range, 00nA at V and o C Break-Before-Make Switching Eliminates Channel Overlap Applications Analog and Digital Multiplexing and Demultiplexing A/D and D/A Conversion Signal Gating CMOS Analog Multiplexers/Demultiplexers with Logic Level Conversion The CD0B, CD0B, and CD0B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 0V P-P can be achieved by digital signal amplitudes of.v to 0V (if - = V, a - of up to V can be controlled; for - level differences above V, a - of at least.v is required). For example, if = +.V, = 0V, and = -.V, analog signals from -.V to +.V can be controlled by digital inputs of 0V to V. These multiplexer circuits dissipate extremely low quiescent power over the full - and - supply-voltage ranges, independent of the logic state of the control signals. When a logic is present at the inhibit input terminal, all channels are off. The CD0B is a single -Channel multiplexer having three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select of channels to be turned on, and connect one of the inputs to the output. The CD0B is a differential -Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select of pairs of channels to be turned on and connect the analog inputs to the outputs. The CD0B is a triple -Channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-throw configuration. When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the COMMON OUT/IN terminals are the inputs. Ordering Information PART NUMBER CD0BFA, CD0BFA, CD0BFA CD0BE, CD0BE, CD0BE CD0BM, CD0BMT, CD0BM CD0BM, CD0BMT, CD0BM CD0BM, CD0BMT, CD0BM CD0BNSR, CD0BNSR, CD0BNSR CD0BPW, CD0BPWR, CD0BPW, CD0BPWR CD0BPW, CD0BPWR TEMP. RANGE ( o C) PACKAGE - to Ld CERAMIC DIP - to Ld PDIP - to Ld SOIC - to Ld SOP - to Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes and R denote tape and reel. The suffix T denotes a small-quantity reel of 0. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright 00, Texas Instruments Incorporated

2 Pinouts CD0B (PDIP, CDIP, SOIC, SOP, TSSOP) TOP VIEW CD0B (PDIP, CDIP, SOP, TSSOP) TOP VIEW COM OUT/IN INH CHANNELS IN/OUT CHANNELS IN/OUT 0 A CHANNELS IN/OUT Y CHANNELS 0 IN/OUT COMMON Y OUT/IN Y CHANNELS IN/OUT INH X CHANNELS IN/OUT COMMON X OUT/IN 0 X CHANNELS IN/OUT 0 B 0 A C B CD0B (PDIP, CDIP, SOP, TSSOP) TOP VIEW by IN/OUT bx OUT/IN bx OR by cy OUT/IN ax OR ay OUT/IN CX OR CY IN/OUT CX ay ax IN/OUT INH A 0 B C Functional Block Diagrams CD0B CHANNEL IN/OUT 0 A B C 0 LOGIC LEVEL CONVERSION BINARY TO OF DECODER WITH INHIBIT COMMON OUT/IN INH All inputs are protected by standard CMOS protection network.

3 Functional Block Diagrams (Continued) CD0B X CHANNELS IN/OUT 0 A B INH 0 LOGIC LEVEL CONVERSION BINARY TO OF DECODER WITH INHIBIT COMMON X OUT/IN COMMON Y OUT/IN 0 Y CHANNELS IN/OUT CD0B LOGIC LEVEL CONVERSION BINARY TO OF IN/OUT DECODERS WITH INHIBIT cy cx by bx ay ax COMMON OUT/IN ax OR ay A COMMON OUT/IN bx OR by B 0 C COMMON OUT/IN cx OR cy INH All inputs are protected by standard CMOS protection network.

4 INPUT STATES TRUTH TABLES INHIBIT C B A ON CHANNEL(S) CD0B X X X None CD0B INHIBIT B A x, 0y 0 0 x, y 0 0 x, y 0 x, y X X None CD0B INHIBIT A OR B OR C 0 0 ax or bx or cx 0 ay or by or cy X None X = Don t Care

5 Absolute Maximum Ratings Supply Voltage (V+ to V-) Voltages Referenced to Terminal V to 0V DC Input Voltage Range V to +0.V DC Input Current, Any One Input ±0mA Operating Conditions Temperature Range o C to o C Thermal Information Package Thermal Impedance, θ JA (see Note ): E (PDIP) package o C/W M (SOIC) package o C/W NS (SOP) package o C/W PW (TSSOP) package o C/W Maximum Junction Temperature (Ceramic Package) o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 0 o C Maximum Lead Temperature (Soldering 0s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. The package thermal impedance is calculated in accordance with JESD -. Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, V SUPPLY = ±V, A V = +, R L = 00Ω, Unless Otherwise Specified (Note ) CONDITIONS LIMITS AT INDICATED TEMPERATURES ( o C) PARAMETER V IS (V) (V) (V) (V) - -0 MIN TYP MAX UNITS SIGNAL INPUTS (V IS ) AND OUTPUTS (V OS ) Quiescent Device Current, I DD Max µa µa µa µa Drain to Source ON Resistance r ON Max 0 V IS Change in ON Resistance (Between Any Two Channels), r ON Ω Ω Ω Ω Ω Ω OFF Channel Leakage Current: Any Channel OFF (Max) or ALL Channels OFF (Common OUT/IN) (Max) ±00 (Note ) ±000 (Note ) - ±0.0 ±00 (Note ) na Capacitance: Input, C IS pf Output, C OS CD pf CD pf CD pf Feedthrough C IOS pf Propagation Delay Time (Signal Input to Output R L = 00kΩ, C L = 0pF, t r, t f = 0ns ns ns ns

6 Electrical Specifications Common Conditions Here: If Whole Table is For the Full Temp. Range, V SUPPLY = ±V, A V = +, R L = 00Ω, Unless Otherwise Specified (Continued) (Note ) CONDITIONS LIMITS AT INDICATED TEMPERATURES ( o C) PARAMETER V IS (V) (V) (V) (V) - -0 MIN TYP MAX UNITS CONTROL (ADDRESS OR INHIBIT), V C Input Low Voltage, V IL, Max Input High Voltage, V IH, Min V IL = through kω; V IH = through kω =, R L = kω to, I IS < µa on All OFF Channels V V - - V V V - - V Input Current, I IN (Max) V IN = 0, ±0. ±0. ± ± - ±0 - ±0. µa Propagation Delay Time: Address-to-Signal OUT (Channels ON or OFF) See Figures 0,, t r, t f = 0ns, C L = 0pF, R L = 0kΩ ns ns ns ns Propagation Delay Time: Inhibit-to-Signal OUT (Channel Turning ON) See Figure t r, t f = 0ns, C L = 0pF, R L = kω ns ns ns Propagation Delay Time: Inhibit-to-Signal OUT (Channel Turning OFF) See Figure Input Capacitance, C IN (Any Address or Inhibit Input) t r, t f = 0ns, C L = 0pF, R L = 0kΩ ns ns ns ns ns pf NOTE:. Determined by minimum feasible leakage measurement for automatic testing. Electrical Specifications TEST CONDITIONS LIMITS PARAMETER V IS (V) (V) R L (kω) TYP UNITS Cutoff (-db) Frequency Channel ON (Sine Wave Input) (Note ) 0 V OS at Common OUT/IN CD0 0 MHz =, CD0 MHz 0Log V OS = db V IS CD0 0 MHz V OS at Any Channel 0 MHz

7 Electrical Specifications TEST CONDITIONS LIMITS PARAMETER V IS (V) (V) R L (kω) TYP UNITS Total Harmonic Distortion, THD (Note ) 0 0. % (Note ) 0 0. % (Note ) 0. % =, f IS = khz Sine Wave % -0dB Feedthrough Frequency (All Channels OFF) -0dB Signal Crosstalk Frequency (Note ) 0 V OS at Common OUT/IN CD0 MHz =, CD0 0 MHz CD0 MHz V OS at Any Channel MHz (Note ) 0 Between Any Channels MHz =, 0Log V OS = 0dB V IS 0Log V OS = 0dB V IS Between Sections, CD0 Only Measured on Common MHz Measured on Any Channel 0 MHz Between Any Two Sections, CD0 Only In Pin, Out Pin. MHz In Pin, Out Pin MHz Address-or-Inhibit-to-Signal Crosstalk (Note ) =0, =0,t r,t f = 0ns, V CC = - (Square Wave) mv PEAK mv PEAK NOTES:. Peak-to-Peak voltage symmetrical about. Both ends of channel Typical Performance Curves r ON, CHANNEL ON RESISTANCE (Ω) = V T A = o C T A = o C T A = - o C r ON, CHANNEL ON RESISTANCE (Ω) = 0V T A = o C T A = o C T A = - o C V IS, INPUT SIGNAL VOLTAGE (V) FIGURE. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) V IS, INPUT SIGNAL VOLTAGE (V) FIGURE. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

8 Typical Performance Curves (Continued) r ON, CHANNEL ON RESISTANCE (Ω) T A = o C - = V V IS, INPUT SIGNAL VOLTAGE (V) 0V V r ON, CHANNEL ON RESISTANCE (Ω) = V T A = o C V IS, INPUT SIGNAL VOLTAGE (V) T A = o C T A = - o C FIGURE. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) FIGURE. CHANNEL ON RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) V OS, OUTPUT SIGNAL VOLTAGE (V) = V = 0V = -V T A = o C R L = 00kΩ, R L = 0kΩ kω 00Ω 00Ω V IS, INPUT SIGNAL VOLTAGE (V) P D, POWER DISSIPATION PACKAGE (µw) 0 T A = o C TEST CIRCUIT V ALTERNATING O DD AND I PATTERN B/D C L = 0pF 0 f CD0 V A B C DD = V 00Ω 0 0 CD0 = 0V 0 = V 00Ω Ι C L C L = pf SWITCHING FREQUENCY (khz) FIGURE. ON CHARACTERISTICS FOR OF CHANNELS (CD0B) FIGURE. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD0B) P D, POWER DISSIPATION PACKAGE (µw) T A = o C ALTERNATING O AND I PATTERN C L = 0pF = V = V C L = pf = 0V 00Ω SWITCHING FREQUENCY (khz) f TEST CIRCUIT V B/D CD0 DD AB 00Ω 0 C L CD0 Ι 0 0 P D, POWER DISSIPATION PACKAGE (µw) T A = o C ALTERNATING O AND I PATTERN C L = 0pF C L = pf = V 00Ω = V = 0V TEST CIRCUIT f 00Ω SWITCHING FREQUENCY (khz) Ι 0 CD0 C L 0 FIGURE. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD0B) FIGURE. DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD0B)

9 Test Circuits and Waveforms = V =.V = V = V.V V V = 0V = 0V = 0V = 0V = 0V (A) = -.V = -0V = -V (B) (C) (D) NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = and =. The analog signal (through the ) may swing from to. FIGURE. TYPICAL BIAS VOLTAGES t r = 0ns t f = 0ns t r = 0ns t f = 0ns 0% 0% 0% TURN-ON TIME 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% 0% TURN-OFF TIME 0% t PHZ 0% TURN-OFF TIME 0% TURN-ON TIME FIGURE 0. WAVEFORMS, CHANNEL BEING TURNED ON (R L = kω) FIGURE. WAVEFORMS, CHANNEL BEING TURNED OFF (R L = kω) 0 I DD I DD I DD 0 0 CD0 CD0 CD0 FIGURE. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF

10 Test Circuits and Waveforms (Continued) I DD 0 I DD 0 0 I DD CD0 CD0 CD0 FIGURE. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF V OUTPUT DD OUTPUT OUTPUT R L C L R L C L R C L L V V EE DD V EE V V V DD EE SS CLOCK V 0 SS 0 0 CLOCK IN IN CLOCK IN CD0 CD0 CD0 FIGURE. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT R L OUTPUT CLOCK IN 0pF VSS 0 OUTPUT R L CLOCK IN 0pF 0 OUTPUT RL 0pF CLOCK IN 0 t PHL AND t PLH CD0 V t PHL AND t SS PLH CD0 V t PHL AND t SS PLH CD0 FIGURE. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT µa K V IH V IL K 0 CD0B V IH MEASURE < µa ON ALL OFF CHANNELS (e.g., CHANNEL ) V IL V IH V IL 0 CD0B K K µa V IH V IL MEASURE < µa ON ALL OFF CHANNELS (e.g., CHANNEL x) V IH V IL K 0 CD0B K µa V IH V IL MEASURE < µa ON ALL OFF CHANNELS (e.g., CHANNEL by) FIGURE. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY) 0

11 Test Circuits and Waveforms (Continued) Ι 0 CD0 CD0 Ι 0 CD0 0kΩ ON KEITHLEY 0 DIGITAL MULTIMETER kω RANGE H.P. MOSELEY 00A Y X X-Y PLOTTER FIGURE. QUIESCENT DEVICE CURRENT FIGURE. CHANNEL ON RESISTANCE MEASUREMENT CIRCUIT 0 CD0 CD0 Ι NOTE: Measure inputs sequentially, to both and connect all unused inputs to either or. 0 CD0 Ι NOTE: Measure inputs sequentially, to both and connect all unused inputs to either or. FIGURE. INPUT CURRENT V P-P OFF CHANNEL K RF VM COMMON CHANNEL ON CHANNEL OFF R L R L RF VM V P-P R L CHANNEL OFF CHANNEL ON RF VM R L FIGURE 0. FEEDTHROUGH (ALL TYPES) FIGURE. CROSSTALK BETWEEN ANY TWO CHANNELS (ALL TYPES) V P-P CHANNEL IN X ON OR OFF CHANNEL IN Y ON OR OFF RF VM R L R L FIGURE. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD0B, CD0B)

12 Test Circuits and Waveforms (Continued) DIFFERENTIAL SIGNALS CD0 CD0 COMMUNICATIONS LINK DIFF. AMPLIFIER/ LINE DRIVER DIFF. RECEIVER DIFF. MULTIPLEXING DEMULTIPLEXING FIGURE. TYPICAL TIME-DIVISION APPLICATION OF THE CD0B Special Considerations In applications where separate power sources are used to drive and the signal inputs, the current capability should exceed /R L (R L = effective external load). This provision avoids permanent current flow or clamp action on the supply when power is applied or removed from the CD0B, CD0B or CD0B. A B C A B C CD0B INH D E A B E / CD Q Q Q 0 A B C INH CD0B COMMON OUTPUT A B C CD0B INH FIGURE. -TO- MUX ADDRESSING

13 PACKAGE OPTION ADDENDUM -Feb-00 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan () Lead/Ball Finish MSL Peak Temp () 00EA ACTIVE CDIP J None Call TI Level-NC-NC-NC 00EA ACTIVE CDIP J None Call TI Level-NC-NC-NC CD0BE ACTIVE PDIP N Pb-Free Level-NC-NC-NC CD0BF ACTIVE CDIP J None Call TI Level-NC-NC-NC CD0BFA ACTIVE CDIP J None Call TI Level-NC-NC-NC CD0BM ACTIVE SOIC D 0 Pb-Free CD0BM ACTIVE SOIC D 00 Pb-Free CD0BMT ACTIVE SOIC D 0 Pb-Free CD0BNSR ACTIVE SO NS 000 Pb-Free CD0BPW ACTIVE TSSOP PW 0 Pb-Free CD0BPWR ACTIVE TSSOP PW 000 Pb-Free CD0BE ACTIVE PDIP N Pb-Free Level--0C- YEAR Level--0C- YEAR Level--0C- YEAR Level--0C- YEAR/ Level--C-UNLIM Level--0C-UNLIM Level--0C-UNLIM Level-NC-NC-NC CD0BF ACTIVE CDIP J None Call TI Level-NC-NC-NC CD0BFA ACTIVE CDIP J None Call TI Level-NC-NC-NC CD0BM ACTIVE SOIC D 0 Pb-Free CD0BM ACTIVE SOIC D 00 Pb-Free CD0BMT ACTIVE SOIC D 0 Pb-Free CD0BNSR ACTIVE SO NS 000 Pb-Free CD0BPW ACTIVE TSSOP PW 0 Pb-Free CD0BPWR ACTIVE TSSOP PW 000 Pb-Free CD0BE ACTIVE PDIP N Pb-Free Level--0C- YEAR/ Level--C-UNLIM Level--0C- YEAR/ Level--C-UNLIM Level--0C- YEAR/ Level--C-UNLIM Level--0C- YEAR/ Level--C-UNLIM Level--0C-UNLIM Level--0C-UNLIM Level-NC-NC-NC CD0BF ACTIVE CDIP J None Call TI Level-NC-NC-NC CD0BFA ACTIVE CDIP J None Call TI Level-NC-NC-NC CD0BM ACTIVE SOIC D 0 Pb-Free CD0BM ACTIVE SOIC D 00 Pb-Free CD0BMT ACTIVE SOIC D 0 Pb-Free CD0BNSR ACTIVE SO NS 000 Pb-Free CD0BPW ACTIVE TSSOP PW 0 Pb-Free Level--0C- YEAR/ Level--C-UNLIM Level--0C- YEAR/ Level--C-UNLIM Level--0C- YEAR/ Level--C-UNLIM Level--0C- YEAR/ Level--C-UNLIM Level--0C-UNLIM Addendum-Page

14 PACKAGE OPTION ADDENDUM -Feb-00 Orderable Device Status () Package Type Package Drawing Pins Package Qty CD0BPWR ACTIVE TSSOP PW 000 Pb-Free Eco Plan () Lead/Ball Finish MSL Peak Temp () Level--0C-UNLIM () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - May not be currently available - please check for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free : TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.% of total product weight. () MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

19 MECHANICAL DATA MTSS00C JANUARY REVISED FEBRUARY PW (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,0 0, 0,0 M 0,,0,0,0,0 0, NOM Gage Plane A 0 0, 0, 0,0,0 MAX 0, 0,0 Seating Plane 0,0 DIM PINS ** 0 A MAX,0,0,0,0,0,0 A MIN,0,0,0,0,0,0 000/F 0/ NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,. D. Falls within JEDEC MO- POST OFFICE BOX 0 DALLAS, TEXAS

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CD4051B, CD4052B, CD4053B

CD4051B, CD4052B, CD4053B CD0B, CD0B, CD0B Data sheet acquired from Harris Semiconductor SCHS0G August - Revised October 00 [ /Title (CD0 B, CD0 B, CD0 B) /Subject (CMOS Analog Multiplexers/Dem ultiplexers with Logic Level Conversion)