CD4051B-Q1, CD4052B-Q1, CD4053B-Q1 CMOS ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LOGIC LEVEL CONVERSION

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1 Features Qualified for Automotive Applications Wide Range of Digital and Analog Signal Levels Digital: V to 0 V Analog: 0 V P-P Low ON Resistance, Ω (Typ) Over V P-P Signal Input Range for = V High OFF Resistance, Channel Leakage of 00 pa (Typ) at = V Logic-Level Conversion for Digital Addressing Signals of V to 0 V ( = V to 0 V) to Switch Analog Signals to 0 V P-P ( = 0 V) Matched Switching Characteristics, r on = Ω (Typ) for = V description/ordering information CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0. µw (Typ) at = = 0 V Binary Address Decoding on Chip -V, 0-V, and -V Parametric Ratings 00% Tested for Quiescent Current at 0 V Maximum Input Current of µa at V Over Full Package Temperature Range, 00 na at V and C Break-Before-Make Switching Eliminates Channel Overlap Applications Analog and Digital Multiplexing and Demultiplexing Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Conversion Signal Gating The CD0B, CD0B, and CD0B analog multiplexers are digitally-controlled analog switches that have low ON impedance and very low OFF leakage current. Control of analog signals up to 0 V P-P can be achieved by digital signal amplitudes of. V to 0 V (If = V, a of up to V can be controlled; for level differences above V, a of at least. V is required). For example, if =. V, = 0 V, and =. V, analog signals from. V to. V can be controlled by digital inputs of 0 V to V. These multiplexer circuits dissipate extremely low quiescent power over the full and supply-voltage ranges, independent of the logic state of the control signals. When a logic high (H) is present at the inhibit (INH) input, all channels are off. ORDERING INFORMATION T A PACKAGE ORDERABLE PART NUMBER 0 C to C TOP-SIDE MARKING SOIC M Reel of 00 CD0BQMQ CD0Q TSSOP PW Reel of 000 CD0BQPWRQ CM0BQ SOIC M Reel of 00 CD0BQMQ CD0Q TSSOP PW Reel of 000 CD0BQPWRQ CD0Q SOIC M Reel of 00 CD0BQMQ CD0Q TSSOP PW Reel of 000 CD0BQPWRQ CD0Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at Package drawings, thermal data, and symbolization are available at Product Preview Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 00, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS

2 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 description/ordering information (continued) The CD0B is a single eight-channel multiplexer that has three binary control inputs (A, B, and C) and an inhibit input. The three binary signals select one of eight channels to be turned on and connect one of the eight inputs to the output. The CD0B is a differential four-channel multiplexer that has two binary control inputs (A and B) and an inhibit input. The two binary input signals select one of four pairs of channels to be turned on and connect the analog inputs to the outputs. The CD0B is a triple two-channel multiplexer with three separate digital control inputs (A, B, and C) and an inhibit input. Each control input selects one of a pair of channels, which are connected in a single-pole, double-throw configuration. When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs, and the common (COM OUT/IN) terminals are the inputs. CD0 M OR PW PACKAGE (TOP VIEW) CD0 M OR PW PACKAGE (TOP VIEW) CHANNEL I/O CHANNEL I/O COM OUT/IN CHANNEL I/O CHANNEL I/O INH 0 CHANNEL I/O CHANNEL I/O CHANNEL I/O 0 CHANNEL I/O A B C Y CHANNEL I/O 0 Y CHANNEL I/O COM Y OUT/IN Y CHANNEL I/O Y CHANNEL I/O INH 0 X CHANNEL I/O X CHANNEL I/O COM X OUT/IN X CHANNEL I/O 0 X CHANNEL I/O A B CD0 M OR PW PACKAGE (TOP VIEW) IN/OUT by IN/OUT bx IN/OUT cy OUT/IN CX OR CY IN/OUT CX INH 0 OUT/IN bx or by OUT/IN ax or ay IN/OUT ay IN/OUT ax A B C POST OFFICE BOX 0 DALLAS, TEXAS

3 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 Function Tables CD0 INPUTS ON INH C B A CHANNEL L L L L 0 L L L H L L H L L L H H L H L L L H L H L H H L L H H H H X X X None X = don t care CD0 INPUTS ON INH B A CHANNEL L L L 0x, 0y L L H x, y L H L x, y L H H x, y H X X None X = don t care CD0 INPUTS ON INH A OR B OR C CHANNEL L L ax or bx or cx L H ay or by or cy H X None X = don t care POST OFFICE BOX 0 DALLAS, TEXAS

4 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 logic diagram (positive logic) CD0B CHANNEL I/O 0 A B C 0 Logic-Level Conversion Binary to -of- Decoder With Inhibit COM OUT/IN INH All inputs are protected by CMOS protection network. CD0B X CHANNEL I/O 0 A B INH 0 Logic-Level Conversion Binary to -of- Decoder With Inhibit COM X OUT/IN COM Y OUT/IN 0 Y CHANNEL I/O All inputs are protected by CMOS protection network. POST OFFICE BOX 0 DALLAS, TEXAS

5 logic diagrams (positive logic) (continued) CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 CD0B cy cx IN/OUT by bx ay ax A B 0 Logic-Level Conversion Binary to -of- Decoders With Inhibit COM OUT/IN ac or ay COM OUT/IN bc or by C COM OUT/IN xc or xy INH All inputs are protected by standard CMOS protection network. absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, V+ to V (voltages referenced to terminal) to 0 V DC input voltage range V to + 0. V DC input current, any one input ±0 ma Package thermal impedance, θ JA (see Note ): M package C/W PW package C/W Maximum junction temperature, T J C Lead temperature (during soldering): At distance / ± / inch (, ± 0, mm) from case for 0 s max C Storage temperature range, T stg C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : The package thermal impedance is calculated in accordance with JESD -. POST OFFICE BOX 0 DALLAS, TEXAS

6 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 recommended operating conditions MIN MAX UNIT Supply voltage 0 V T A Operating free-air temperature 0 C electrical characteristics, V SUPPLY = ± V, A V = V, R L = 00 Ω, unless otherwise noted (see Note ) I DD PARAMETER TEST CONDITIONS (V) LIMITS AT INDICATED TEMPERATURES C 0 C C MIN TYP MAX Quiescent device current Signal Input (V is ) and Output (V os ) Drain-to-source = 0V V, = 0V, r on Ω ON-state resistance V VIS =0to r on ON-state resistance difference between = 0 V, = 0 V 0 0 Ω any two switches Input/output leakage current (switch off) Any channel OFF (MAX) or all channels OFF (COM OUT/IN) (Max), = 0 V, = 0 V, See Note UNIT µaa ±0. ± ±0 ±0. µa C is Input capacitance = V, = V pf CD0 0 C os Output capacitance = V, = V CD0 pf C ios t pd NOTES: Feedthrough capacitance Propagation delay (signal input to output) CD0 = V, = V 0. pf V IS(p-p) =, R L = 00 kω, C L =0pF pf, t r, t f =0ns. Peak-to-peak voltage symmetrical about. Determined by minimum feasible leakage measurement for automatic testing ns 0 0 POST OFFICE BOX 0 DALLAS, TEXAS

7 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 electrical characteristics, V SUPPLY = ± V, A V = V, R L = 00 Ω, unless otherwise noted (see Note ) (continued) PARAMETER TEST CONDITIONS TEMPERATURES LIMITS AT INDICATED (V) (V) C 0 C C MIN TYP MAX Control (Address or Inhibit), V C VIL = VDD through kω,... V V Input low voltage IH = through kω, IL R L =kω to, 0 V I is < µa on all OFF channels V IH Input high voltage V IL = through kω,... V IH = through kω, R L =kω to, 0 V I is < µa on all OFF channels I IN Input current V IN = 0 V, V ±0. ± ±0 ±0. µa t pd t pd t pd C IN Address-to-signal t r, t f =0ns ns, C L =0pF pf, OUT (channels ON R L = 0 kω, = 0 V, or OFF) )propagationp See Figure 0, Figure, and delay Figure Inhibit-to-signal t r, t f = 0 ns, C L = 0 pf, OUT (channel R kω 0V turning ON) L = kω, = V, See Figure propagation delay Inhibit-to-signal OUT (channel turning OFF) propagation delay Input capacitance, any address or inhibit input t r, t f = 0 ns, C L = 0 pf, R L = 0 kω, = 0V, See Figure NOTES: : Peak-to-peak voltage symmetrical about : Determined by minimum feasible leakage measurement for automatic testing UNIT ns ns ns. pf POST OFFICE BOX 0 DALLAS, TEXAS

8 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 electrical specifications THD V PARAMETER TEST CONDITIONS IS (V) -db cutoff frequency, channel ON (sine-wave input) Total harmonic distortion 0-dB feedthrough h frequency (all channels OFF) 0-dB signal crosstalk frequency Address or inhibit to signal crosstalk (V) LIMITS AT INDICATED TEMPERATURES C MIN TYP MAX UNIT R L = kω, CD0 0 0 V OS at COM OUT/IN, CD0 0 See Note, V OS at COM OUT/IN CD0 0 0 MHz =, 0log V OS /V IS = db, V OS at any channel R L = 0 kω, See Note =, f is = -khz sine wave 0. R L = kω, CD0 0 V OS at COM OUT/IN, CD0 0 0 See Note CD0 0 MHz =, 0log V OS /V IS = 0 db, V OS at any channel R L = kω, between any two channels, See Note 0 =, 0log V OS /V IS = 0 db, Between sections, Measured on common =, 0log V OS /V IS = 0 db, Between sections, Measured on any channel CD0 =, 0log V OS /V IS = 0 db, Between any two sections,. In pin, Out pin =, 0log V OS /V IS = 0 db, CD0 Between any two sections, In pin, Out pin R L = 0 kω, See Note 0 = 0 V, = 0 V, t r, t f = 0 ns, V CC = (square wave) 0 % MHz mv PEAK NOTES:. Peak-to-peak voltage symmetrical about. Both ends of channel POST OFFICE BOX 0 DALLAS, TEXAS

9 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 TYPICAL CHARACTERISTICS r on Channel ON State Resistance CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE Supply Voltage ( ) = V 0 0 V is Input Signal Voltage V Figure T A = C C C CS-RI r on Channel ON State Resistance CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE Supply Voltage ( ) = 0 V T A = C C C V is Input Signal Voltage V Figure CS-RI CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE CHANNEL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE r on Channel ON State Resistance T A = C Supply Voltage ( ) = V 0 V V r on Channel ON State Resistance Supply Voltage ( ) = V T A = C C C V is Input Signal Voltage V Figure CS-0RI V is Input Signal Voltage V Figure CS-RI POST OFFICE BOX 0 DALLAS, TEXAS

10 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 TYPICAL CHARACTERISTICS V os Output Signal Voltage V 0 = V = 0 V = V T A = C ON CHARACTERISTICS FOR -OF- CHANNELS (CD0B) R L = 00 k, R L = 0 k 0 V is Input Signal Voltage V Figure k P D Power Dissipation Per Package W DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD0B) T A = C Alternating O and I Pattern C L = 0 pf = V C L = pf = V 0 0 = 0 V f Switching Frequency khz Figure 0 f Test Circuit 00 Ω B/D CD0 A B C 0 CD0 C L 00 Ω Ι 0 0 P D Power Dissipation Per Package W DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD0B) T A = C Alternating ÒOÓ and ÒIÓ Pattern C L = 0 pf = V = V C L = pf 0 0 = 0 V f Switching Frequency khz Figure 0 00 Ω f 00 Ω 0 CD0 Test Circuit CD0 B/D A B Ι 0 C L 0 P D Power Dissipation Per Package W DYNAMIC POWER DISSIPATION vs SWITCHING FREQUENCY (CD0B) T A = C Alternating O and I Pattern C L = 0 pf C L = pf = V 0 0 f Switching Frequency khz Figure 0 = V = 0 V Test Circuit f C L CD0 0 Ι POST OFFICE BOX 0 DALLAS, TEXAS

11 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 PARAMETER MEASUREMENT INFORMATION = V =. V = V = V V V. V = 0 V = 0 V = 0 V = 0 V = 0 V (A) =. V = 0 V = V (B) (C) (D) NOTE: The A, B, C, and INH input logic levels are L = and H =. The analog signal (through the ) may swing from to. Figure. Typical Bias-Voltage Test Circuits 0% tr = 0 ns 0% 0% Turn-On Time 0% 0% tf = 0 ns 0% 0% tr = 0 ns 0% 0% 0% 0% tf = 0 ns 0% 0% 0% 0% Turn-Off Time 0% tphz 0% Turn-Off Time 0% Turn-On Time Figure 0. Channel Turned ON Waveforms (R L = kω) Figure. Channel Turned OFF Waveforms (R L = kω) POST OFFICE BOX 0 DALLAS, TEXAS

12 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 PARAMETER MEASUREMENT INFORMATION 0 CD0 I DD 0 CD0 CD0 Figure. OFF Channel Leakage Current, Any Channel OFF I DD 0 CD0 I DD I DD 0 I DD 0 0 I DD CD0 CD0 CD0 Figure. OFF Channel Leakage Current, All Channels OFF 0 CD0 R L Output Clock In C L Output C L R L 0 CD0 Clock In VEE 0 CD0 R L Clock In Output CL Figure. Propagation Delay, Address Input to Signal Output R L Output Clock In 0 pf 0 R L Output Clock In 0 pf 0 R L Output Clock In 0 pf 0 t PHL and t PLH CD0 t PHL and t PLH CD0 Figure. Propagation Delay, Inhibit Input to Signal Output t PHL and t PLH CD0 POST OFFICE BOX 0 DALLAS, TEXAS

13 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 PARAMETER MEASUREMENT INFORMATION µa K K V IH V IL 0 CD0B V IH V IL V IH V IL 0 CD0B K K µa V IL V IH V IH V IL K 0 CD0B K ma VIH V IL Measure A on All OFF Channels (e.g., Channel ) Measure A on All OFF Channels (e.g., Channel x) Measure A on All OFF Channels (e.g., Channel by) Figure. Input-Voltage Test Circuit (Noise Immunity) 0 0 Ι CD0 CD0 Ι CD0 Figure. Quiescent Device Current Keithley 0 Digital Multimeter 0 k On -k Range Y X Y Plotter H.P. Moseley 00A X Figure. Channel ON-Resistance Test Circuit POST OFFICE BOX 0 DALLAS, TEXAS

14 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 PARAMETER MEASUREMENT INFORMATION 0 CD0 CD0 Ι 0 CD0 CD0 Ι NOTE: Measure inputs sequentially to both and. Connect all unused inputs to either or. NOTE: Measure inputs sequentially to both and. Connect all unused inputs to either or. Figure. Input Current V P P OFF Channel K RF VM Common Channel ON Channel OFF RL RL RF VM V P P RL Channel OFF Channel ON RF VM RL Figure 0. Feedthrough Figure. Crosstalk Between Any Two Channels V P P Channel In X Channel In Y RF ON or OFF ON or OFF VM R L R L Figure. Crosstalk Between Duals or Triplets (CD0B, CD0B) Differential Signals CD0 CD0 Communications Link Differential Amplifier/Line Driver Differential. Receiver Differential Multiplexing Demultiplexing Figure. Typical Time-Division Application of the CD0B POST OFFICE BOX 0 DALLAS, TEXAS

15 CD0B-Q, CD0B-Q, CD0B-Q SCHSA AUGUST 00 REVISED JANUARY 00 APPLICATION INFORMATION In applications where separate power sources drive and the signal inputs, the current capability should exceed /R L (R L = effective external load). This provision avoids permanent current flow or clamp action on the supply when power is applied or removed from the CD0B, CD0B, or CD0B. A B C A B C CD0B INH D E A B E / CD Q0 Q Q A B C CD0B INH Common Output A B C CD0B INH Figure. -to- Multiplexer Addressing POST OFFICE BOX 0 DALLAS, TEXAS

16 PACKAGE OPTION ADDENDUM -Feb-0 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan CD0BQPWRGQ ACTIVE TSSOP PW 000 Green (RoHS & no Sb/Br) CD0BQPWRQ ACTIVE TSSOP PW 000 Green (RoHS & no Sb/Br) CD0BQMGQ ACTIVE SOIC D 00 Green (RoHS & no Sb/Br) CD0BQMQ ACTIVE SOIC D 00 Green (RoHS & no Sb/Br) () Lead/Ball Finish () MSL Peak Temp () Op Temp ( C) Device Marking (/) CU NIPDAU Level--0C-UNLIM -0 to CM0BQ CU NIPDAU Level--0C-UNLIM -0 to CM0BQ CU NIPDAU Level--0C-UNLIM -0 to CD0Q CU NIPDAU Level--0C-UNLIM -0 to CD0Q Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or ) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) () MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. () Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. () Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page

17 PACKAGE OPTION ADDENDUM -Feb-0 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD0B-Q, CD0B-Q : Catalog: CD0B, CD0B Military: CD0B-MIL, CD0B-MIL NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications Addendum-Page

18 PACKAGE MATERIALS INFORMATION -Mar-0 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant CD0BQPWRGQ TSSOP PW Q CD0BQPWRQ TSSOP PW Q Pack Materials-Page

19 PACKAGE MATERIALS INFORMATION -Mar-0 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD0BQPWRGQ TSSOP PW CD0BQPWRQ TSSOP PW Pack Materials-Page

22 SCALE.00 PW00A PACKAGE OUTLINE TSSOP -. mm max height SMALL OUTLINE PACKAGE A. TYP. PIN INDEX AREA X 0. C SEATING PLANE 0. C X.. NOTE. B.. NOTE X C A B. MAX SEE DETAIL A (0.) TYP 0. GAGE PLANE A 0 DETAIL A TYPICAL 00/A 0/0 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y.M.. This drawing is subject to change without notice.. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0. mm per side.. This dimension does not include interlead flash. Interlead flash shall not exceed 0. mm per side.. Reference JEDEC registration MO-.

23 .000 PW00A EXAMPLE BOARD LAYOUT TSSOP -. mm max height SMALL OUTLINE PACKAGE X (.) SYMM X (0.) (R0.0) TYP SYMM X (0.) (.) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 0X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.0 MAX ALL AROUND 0.0 MIN ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS SOLDER MASK DEFINED 00/A 0/0 NOTES: (continued). Publication IPC- may have alternate designs.. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

24 PW00A EXAMPLE STENCIL DESIGN TSSOP -. mm max height SMALL OUTLINE PACKAGE X (0.) X (.) SYMM (R0.0) TYP SYMM X (0.) (.) SOLDER PASTE EXAMPLE BASED ON 0. mm THICK STENCIL SCALE: 0X 00/A 0/0 NOTES: (continued). Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC- may have alternate design recommendations.. Board assembly site may have different recommendations for stencil design.

25 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES AS IS AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for () selecting the appropriate TI products for your application, () designing, validating and testing your application, and () ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI s products are provided subject to TI s Terms of Sale ( or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI s provision of these resources does not expand or otherwise alter TI s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 0, Dallas, Texas Copyright 0, Texas Instruments Incorporated

Data sheet acquired from Harris Semiconductor SCHS038C Revised October 2003

Data sheet acquired from Harris Semiconductor SCHS038C Revised October 2003 The CD4035B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages