VOLTAGE PROTECTION FOR 2-, 3-, OR 4-CELL Lion BATTERIES (2 nd PROTECTION)

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1 Not Recommended for New Designs: bq900, bq900a, bq90 FEATURES FUNCTION -, -, or -Cell Secondary Protection Each cell in a multiple cell pack is compared to an Low Power Consumption I CC < µa internal reference voltage. If one cell reaches an [VCELL (ALL) < V (PROTECT) ] overvoltage condition, the protection sequence begins. The bq90x device starts charging an High Accuracy Over Sense Voltage: external capacitor through the pin. When the bq900:. V ± mv pin voltage reaches. V, the pin changes from bq900a:.0 V ± mv a low level to a high level. VC VC VC GND PW PACKAGE (TOP VIEW) bq900, bq900a bq90, bq90 SLUSC JULY 00 REVISED SEPTEMBER 00 VOLTAGE PROTECTION FOR -, -, OR -CELL Lion BATTERIES ( nd PROTECTION) bq90:. V ± mv bq90:. V ± mv Prefixed Protection Threshold Voltage Programmable Delay Time High Power Supply Ripple Rejection Stable During Pulse Charge Operation 7 VDD VC APPLICATIONS nd Level Protection in Lion Battery Packs in Notebook PCs Portable Instrumentation Medical and Test Equipment DESCRIPTION The bq900, bq900a, bq90, and bq90 are BiCMOS secondary protection ICs for -, -, or -cell Lithium-Ion battery packs that incorporate a high-accuracy precision over voltage detection circuit. They include a programmable delay circuit for over voltage detection time. VDD VC DCT PACKAGE (TOP VIEW) VC 7 VC VC GND ORDERING INFORMATION PACKAGE T A V (PROTECT) MSSOP (DCT) SYMBOL TSSOP (PW) () SYMBOL C to C. V bq900dct CIQ bq900pw 00.0 V bq900adct CIT Not Available -. V bq90dct CIR bq90pw 0. V bq90dct CIS Not Available - () The bq900, bq900a, bq90, and bq90 are available taped and reeled. Add an R suffix to the device type (e.g., bq900pwr) to order tape and reel version. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 00 00, Texas Instruments Incorporated

2 bq900, bq900a bq90, bq90 SLUSC JULY 00 REVISED SEPTEMBER 00 Not Recommended for New Designs: bq900, bq900a, bq90 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted ()() Supply voltage range (VDD) 0. V to V Input voltage range (VC, VC, VC, VC) 0. V to V Output voltage range () () Continuous total power dissipation PACKAGE DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS UNIT 0. V to V 0. V to V See Dissipation Rating Table Storage temperature range, T stg C to 0 C Lead temperature (soldering, 0 sec) 00 C () Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. () All voltages are with respect to ground of this device except the differential voltage of VC-VC, VC-VC, VC-VC and VC-GND. PACKAGE T A = C DERATING FACTOR T A = 70 C T A = C POWER RATING ABOVE T A = C POWER RATING POWER RATING DCT mw. mw/ C mw mw PW mw. mw/ C mw 7 mw MIN NOM MAX UNIT V DD Supply Voltage.0 V V DD +0. V I Input voltage range VC, VC, VC, VC 0 V t d() Delay time capacitance 0. µf R IN Voltage-monitor filter resistance 00 k Ω C IN Voltage-monitor filter capacitance µf R VD Supply-voltage filter resistance 0 kω C VD Supply-voltage filter capacitance 0. µf T A Operating ambient temperature range C

3 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, T A = C (unless otherwise noted) () bq900, bq900a bq90, bq90 SLUSC JULY 00 REVISED SEPTEMBER 00 PARAMETER TEST CONDITION MIN NOM MAX UNIT V (OA) Over voltage detection accuracy mv T A = 0 C to C 0 V (PROTECT) bq900. Over voltage detection bq90a.0 voltage () bq90. bq90. Over voltage detection V hys 00 mv hysteresis () V, V, VC input = VC VC = VC VC = VC VC I I Input current 0. µa = VC GND =. V t D Over voltage detection delay time = 0. µf.0..0 S I (_dis) GND clamp current = V µa VC VC = VC VC = VC VC = VC GND =. V.0.0 (see Figure ) I CC Supply current µa VC = VC = VC = VC = VC VC = VC GND =... V (see Figure ) V () pin drive voltage Not Recommended for New Designs: bq900, bq900a, bq90 VC VC = VC VC = VC VC = VC GND = V (PROTECT) MAX, VDD = VC, IOH = 0 ma VC=VC=VC=VC=V (PROTECT) MAX, VDD=.V, T A = 0 C to 70 C, IOH = 0µA V 7 V..0. V = V, VC VC = VC VC = VC VC = I OH High-level output current ma VC GND =.7 V = 0. V VC VC = VC VC = VC VC = I OL Low-level output current µa VC GND =. V () Levels of the over-voltage detection and the hysteresis can be adjusted. For assistance contact Texas Instruments sales representative. V I CC VC V V V I IN I IN VC VC GND VDD VC 7 I IN Figure. I CC, I IN Measurement (TSSOP Package) Terminal Functions TERMINAL MSOP TSSOP DESCRIPTION NAME (DTC) (PW) VC Sense voltage input for most positive cell 7 VC Sense voltage input for second most positive cell VC Sense voltage input for third most positive cell GND Ground pin VC Sense voltage input for least positive cell

4 bq900, bq900a bq90, bq90 SLUSC JULY 00 REVISED SEPTEMBER 00 Not Recommended for New Designs: bq900, bq900a, bq90 Terminal Functions (continued) TERMINAL MSOP TSSOP DESCRIPTION NAME (DTC) (PW) An external capacitor is connected to determine the programmable delay time 7 VDD Power supply Output FUNCTIONAL BLOCK DIAGRAM R VD VDD CVD VC R IN I = 0. A (TYP) C IN VC R IN R IN C IN VC C IN R IN VC C IN.V (TYP) GND OVERVOLTAGE PROTECTION When one of the cell voltages exceeds V (PROTECT), an internal current source begins to charge the capacitor, C (DELAY), connected to the pin. If the voltage at the pin, V, reaches. V, the pin is activated and transitions high. An externally connected NCH FET is activiated and blows the external fuse in the positive battery rail, see Figure. If all cell voltages fall below V (PROTECT) before the voltage at pin reaches. V, the delay time does not run out. An internal switch clamps the pin to GND and discharges the capacitor, C (DELAY), and secures the full delay time for the next occurring overvoltage event. Once the pin is activated, it transitions back from high to low after all battery cells reach V (PROTECT) - V hys. DELAY TIME CALCULATION The delay time is calculated as follows:

5 . V C (DELAY) t d I t I d C (DELAY). V Where I () = current source = 0. µa Not Recommended for New Designs: bq900, bq900a, bq90 bq900, bq900a bq90, bq90 SLUSC JULY 00 REVISED SEPTEMBER 00 V (PROTECT) Cell Voltage (VCn - VC(n-), VC - GND) V (PROTECT) - V hys. V t DELAY t d = (. V x C DELAY )/I Figure. Timing for Overvoltage Sensing V CC vs V O(H) (I O(H) = 0mA) V CC vs V O(H) (I O(H) = -ma T A = C 7 VOH High-Level Output Voltage V 7 T A = C T A = C VOH High-Level Output Voltage V T A = C T A = C T A = C V DD Supply Voltage V V DD Supply Voltage V Figure. Figure.

6 bq900, bq900a bq90, bq90 SLUSC JULY 00 REVISED SEPTEMBER 00 Not Recommended for New Designs: bq900, bq900a, bq90 APPLICATION INFORMATION BATTERY CONNECTIONS The following diagrams show the TSSOP package device in different cell configurations. VC VC VC VDD 7 VC VDD 7 VC VC GND VC C DELAY GND VC C DELAY Figure. -Series Cell Configuration Figure. -Series Cell Configuration (Connect together VC and VC) VC VC VDD 7 VC GND VC C DELAY Figure 7. -Series Cell Configuration CELL CONNECTIONS To prevent incorrect output activation the following connection sequences must be used. -Series Cell Configuration VC(=VDD) VC VC VC GND or GND VC VC VC VC(=VDD) -Series Cell Configuration VC(=VC=VDD) VC VC GND or GND VC VC VC(=VC=VDD) -Series Cell Configuration VC(=VC=VC=VDD) VC GND or GND VC VC(=VC=VC=VDD)

7 PACKAGE OPTION ADDENDUM -Sep-0 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan BQ900DCT NRND SM DCT 000 Pb-Free (RoHS) BQ900DCTE NRND SM DCT 000 Pb-Free (RoHS) BQ900PW NRND TSSOP PW 0 Green (RoHS & no Sb/Br) BQ90PW NRND TSSOP PW 0 Green (RoHS & no Sb/Br) () Lead/Ball Finish () MSL Peak Temp () Op Temp ( C) Device Marking (/) CU SNBI Level--0C-UNLIM CIQ CU SNBI Level--0C-UNLIM CIQ CU NIPDAU Level--0C-UNLIM - to 900 CU NIPDAU Level--0C-UNLIM -0 to 90 Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 0 RoHS substances, including the requirement that RoHS substance do not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=000ppm threshold. Antimony trioxide based flame retardants must also meet the <=000ppm threshold requirement. () MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. () Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. () Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page

8 PACKAGE OPTION ADDENDUM -Sep-0 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

9 MECHANICAL DATA MPDS09B MAY 999 REVISED OCTOBER 00 DCT (R-PDSO-G) PLASTIC SMALL-LINE PACKAGE 0, 0,0 0, 0, M PIN INDEX AREA ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ,,7,90,70,,7 0 0, NOM Gage Plane 0, 0,0 0,0,0 MAX Seating Plane 0,0 0,0 0,00 7/C 09/0 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion D. Falls within JEDEC MO-7 variation DA. POST OFFICE BOX 0 DALLAS, TEXAS 7

SCALE.00 PW000A PACKAGE LINE TSSOP -. mm max height SMALL LINE PACKAGE. TYP. SEATING PLANE C A PIN ID AREA 0. C X 0...9 NOTE X.9 B.. NOTE X 0.0 0.9 0. C A B. MAX SEE DETAIL A (0.) TYP 0.

11 SCALE.00 PW000A PACKAGE LINE TSSOP -. mm max height SMALL LINE PACKAGE. TYP. SEATING PLANE C A PIN ID AREA 0. C X NOTE X.9 B.. NOTE X C A B. MAX SEE DETAIL A (0.) TYP 0. GAGE PLANE DETAIL A TYPICAL /A 0/0 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y.M.. This drawing is subject to change without notice.. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0. mm per side.. This dimension does not include interlead flash. Interlead flash shall not exceed 0. mm per side.. Reference JEDEC registration MO-, variation AA.

12 PW000A EXAMPLE BOARD LAY TSSOP -. mm max height SMALL LINE PACKAGE X (0.) X (.) SYMM (R 0.0) TYP SYMM X (0.) (.) LAND PATTERN EXAMPLE SCALE:0X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.0 MAX ALL AROUND 0.0 MIN ALL AROUND NON SOLDER MASK DEFINED SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE /A 0/0 NOTES: (continued). Publication IPC-7 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

13 PW000A EXAMPLE STENCIL DESIGN TSSOP -. mm max height SMALL LINE PACKAGE X (0.) X (.) SYMM (R 0.0) TYP SYMM X (0.) (.) SOLDER PASTE EXAMPLE BASED ON 0. mm THICK STENCIL SCALE:0X /A 0/0 NOTES: (continued). Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

14 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES AS IS AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITH LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for () selecting the appropriate TI products for your application, () designing, validating and testing your application, and () ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI s products are provided subject to TI s Terms of Sale (/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI s provision of these resources does not expand or otherwise alter TI s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 0, Dallas, Texas 7 Copyright 0, Texas Instruments Incorporated

Data sheet acquired from Harris Semiconductor SCHS038C Revised October 2003

Data sheet acquired from Harris Semiconductor SCHS038C Revised October 2003 The CD4035B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages