AVAILABLE OPTIONS LOGIC FUNCTION. Dual inverting drivers Dual noninverting drivers One inverting and one noninverting driver

Transcription

1 Industry-Standard Driver Replacement -ns Max Rise/Fall Times and 0-ns Max Propagation Delay -nf Load, V CC = V -A Peak Output Current, V CC = V -µa Supply Current Input High or Low -V to -V Supply-Voltage Range; Internal Regulator Extends Range to 0 V (TPS, TPS, TPS) 0 C to C Ambient-Temperature Operating Range description The TPSxx series of dual high-speed MOSFET drivers are capable of delivering peak currents of A into highly capacitive loads. This performance is achieved with a design that inherently minimizes shoot-through current and consumes an order of magnitude less supply current than competitive products. The TPS, TPS, and TPS drivers include a regulator to allow operation with supply inputs between V and 0 V. The regulator output can power other circuitry, provided power dissipation does SLVSF NOVEMBER 99 REVISED OCTOBER 00 not exceed package limitations. When the regulator is not required, REG_IN and REG_OUT can be left disconnected or both can be connected to V CC or GND. The TPS and the TPS have -input gates that give the user greater flexibility in controlling the MOSFET. The TPS has AND input gates with one inverting input. The TPS has dual-input NAND gates. TPSx series drivers, available in -pin PDIP, SOIC, and TSSOP packages operate over a ambient temperature range of 0 C to C. TA 0 C to C INTERNAL REGULATOR Yes No AVAILABLE OPTIONS LOGIC FUNCTION Dual inverting drivers Dual noninverting drivers One inverting and one noninverting driver Dual -input AND drivers, one inverting input on each driver Dual -input NAND drivers TPS, TPS, TPS...D, P, AND PW PACKAGES (TOP VIEW) REG_IN IN GND IN SMALL OUTLINE (D) TPSD TPSD TPSD TPSD TPSD PACKAGED DEVICES PLASTIC DIP (P) TPSP TPSP TPSP TPSP TPSP TSSOP (PW) TPSPW TPSPW TPSPW TPSPW TPSPW The D package is available taped and reeled. Add R suffix to device type (e.g., TPSDR). The PW package is only available left-end taped and reeled and is indicated by the R suffix on the device type (e.g., TPSPWR). IN IN IN IN 7 7 REG_OUT OUT V CC OUT TPS...D, P, AND PW PACKAGES (TOP VIEW) GND OUT V CC OUT TPS...D, P, AND PW PACKAGES (TOP VIEW) IN IN IN IN 7 GND OUT V CC OUT Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 00, Texas Instruments Incorporated

2 SLVSF NOVEMBER 99 REVISED OCTOBER 00 functional block diagram TPS REG_IN Regulator IN 7 REG_OUT VCC OUT regulator diagram (TPS, TPS, TPS only) REG_IN IN GND OUT 7. Ω REG_OUT REG_IN IN IN GND TPS Regulator 7 REG_OUT VCC OUT OUT REG_IN IN IN GND TPS Regulator 7 REG_OUT VCC OUT OUT input stage diagram IN VCC To Drive Stage IN IN IN IN TPS 7 VCC OUT OUT output stage diagram VCC GND Predrive IN IN IN IN GND TPS 7 VCC OUT OUT OUT

3 TPSxxY chip information SLVSF NOVEMBER 99 REVISED OCTOBER 00 This chip, when properly assembled, displays characteristics similar to those of the TPSxx. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS () () REG_IN IN IN () () () TPSY TPSY TPSY () (7) () () REG_OUT OUT VCC OUT (7) () GND 7 () () IN IN IN IN () () () () TPSY () GND (7) () () OUT VCC OUT () () IN IN IN IN () () () () TPSY () (7) () () OUT VCC OUT () GND CHIP THICKNESS: MILS TYPICAL 7 BONDING PADS: MILS MINIMUM TJmax OPERATING TEMPERATURE = 0 C TOLERANCES ARE ±0%. ALL DIMENSIONS ARE IN MILS.

4 SLVSF NOVEMBER 99 REVISED OCTOBER 00 TPS, TPS, TPS Terminal Functions TERMINAL NUMBERS TERMINAL TPS TPS TPS NAME Dual Inverting Dual Noninverting Complimentary DESCRIPTION Drivers Drivers Drivers REG_IN Regulator input IN Input GND Ground IN Input OUT = IN = IN = IN Output VCC Supply voltage OUT 7 = IN 7 = IN 7 = IN Output REG_OUT Regulator output TPS, TPS TERMINAL NAME TPS Dual AND Drivers with Single Inverting Input TERMINAL NUMBERS TPS Dual NAND Drivers DESCRIPTION IN Noninverting input of driver IN - Inverting input of driver IN - Noninverting input of driver IN Noninverting input of driver IN - Inverting input of driver IN - Noninverting input of driver OUT = IN IN = IN IN Output VCC Supply voltage OUT 7 = IN IN 7 = IN IN Output GND Ground PACKAGE TA C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 70 C POWER RATING TA = C POWER RATING P 090 mw.7 mw/ C 97 mw mw D 70 mw. mw/ C 7 mw 0 mw PW 0 mw.7 mw/ C mw 70 mw

5 SLVSF NOVEMBER 99 REVISED OCTOBER 00 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V to V Regulator input voltage range, REG_IN V CC 0. V to V Input voltage range, IN, IN, IN, IN, IN, IN, IN, IN V to V CC +0. V Output voltage range, OUT, OUT < V < V CC +0. V Continuous regulator output current, REG_OUT ma Continuous output current, OUT, OUT ±00 ma Continuous total power dissipation See Dissipation Rating Table Operating ambient temperature range, T A C to C Storage temperature range, T stg C to 0 C Lead temperature, mm (/ inch) from case for 0 seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : All voltages are with respect to device GND pin. recommended operating conditions MIN MAX UNIT Regulator input voltage range 0 V Supply voltage, VCC V Input voltage, IN, IN, IN, IN, IN, IN, IN, IN 0. VCC V Continuous regulator output current, REG_OUT 0 0 ma Ambient temperature operating range 0 C TPSxx electrical characteristics over recommended operating ambient temperature range, V CC = 0 V, REG_IN open for TPS//, C L = nf (unless otherwise noted) inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = V. V Positive-going input threshold voltage VCC = 0 V. 9 V VCC = V. V VCC = V. V Negative-going input threshold voltage VCC = 0 V. V VCC = V. V Input hysteresis VCC = V. V Input current Inputs = 0 V or VCC 0. µa Input capacitance 0 pf Typicals are for unless otherwise noted. outputs High-level output voltage Low-level output voltage PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO = ma IO = 00 ma 9. IO = ma IO = 00 ma Peak output current VCC = 0 V A Typicals are for unless otherwise noted. V V

6 SLVSF NOVEMBER 99 REVISED OCTOBER 00 regulator (TPS// only) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage REG_IN 0 V, 0 IO 0 ma 0. V Output voltage in dropout IO = 0 ma, REG_IN = 0 V 9 9. V Typicals are for unless otherwise noted. supply current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply current into VCC Inputs high or low 0. µa Supply current into REG_IN REG_IN = 0 V, REG_OUT open 0 00 µa Typicals are for unless otherwise noted. TPSxxY electrical characteristics at T A = C, V CC = 0 V, REG_IN open for TPS//, C L = nf (unless otherwise noted) inputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = V. V Positive-going input threshold voltage VCC = 0 V. V VCC = V. V VCC = V. V Negative-going input threshold voltage VCC = 0 V. V VCC = V. V Input hysteresis VCC = V. V Input current Inputs = 0 V or VCC 0. µa Input capacitance pf outputs High-level output voltage Low-level output voltage PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IO = ma 9.9 IO = 00 ma 9. IO = ma 0. IO = 00 ma Peak output current VCC = 0. V A regulator (TPS,, ) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output voltage REG_IN 0 V, 0 IO 0 ma. V Output voltage in dropout IO = 0 ma, REG_IN = 0 V 9. V power supply current PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply current into VCC Inputs high or low 0. µa Supply current into REG_IN REG_IN = 0 V, REG_OUT open 0 µa V V

7 SLVSF NOVEMBER 99 REVISED OCTOBER 00 switching characteristics for all devices over recommended operating ambient temperature range, REG_IN open for TPS//, C L = nf (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC = V tr Rise time VCC = 0 V 0 ns VCC = V 0 VCC = V tf Fall time VCC = 0 V 0 ns VCC = V VCC = V 0 tphl Prop delay time high-to-low-level output VCC = 0 V ns VCC = V 0 VCC = V 0 tplh Prop delay time low-to-high-level output VCC = 0 V ns VCC = V 0 PARAMETER MEASUREMENT INFORMATION TPS Regulator + 0. µf.7 µf VCC Input 7 Output 0 Ω nf NOTE A: Input rise and fall times should be 0 ns for accurate measurement of ac parameters. Figure. Test Circuit For Measurement of Switching Characteristics 7

8 SLVSF NOVEMBER 99 REVISED OCTOBER 00 PARAMETER MEASUREMENT INFORMATION TPS Regulator 0 0 V dc 7 xout Current Loop VCC + 0. µf.7 µf 0 V Figure. Shoot-through Current Test Setup IN 0% 0% 0 V tf tr OUT 90% 0% 0% 90% 0% 0% 0 V tphl tplh Figure. Typical Timing Diagram (TPS) TYPICAL CHARACTERISTICS Tables of Characteristics Graphs and Application Information typical characteristics PARAMETER vs PARAMETER FIGURE PAGE Rise time Supply voltage 0 Fall time Supply voltage 0 Propagation delay time Supply voltage, 7 0 Supply voltage Supply current Load capacitance 9 Ambient temperature 0 Input threshold voltage Supply voltage Regulator output voltage Regulator input voltage, Regulator quiescent current Regulator input voltage Peak source current Supply voltage Peak sink current Supply voltage Shoot-through current Input voltage, high-to-low 7 Input voltage, low-to-high

9 TYPICAL CHARACTERISTICS SLVSF NOVEMBER 99 REVISED OCTOBER 00 Tables of Characteristics Graphs and Application Information (Continued) general applications PARAMETER vs PARAMETER FIGURE PAGE Switching test circuits and application information 9, 0 Low-to-high,,, 7 Voltage of OUT vs OUT Time High-to-low,,, 7 circuit for measuring paralleled switching characteristics PARAMETER vs PARAMETER FIGURE PAGE Switching test circuits and application information 7 7 Low-to-high, 0 Input voltage vs output voltage Time High-to-low 9, Hex- to Hex- application information PARAMETER vs PARAMETER FIGURE PAGE Driving test circuit and application information 9 Hex- size 0 Hex- size 0 Drain-source voltage vs drain current Time Hex- size 9 Hex- size Hex- size parallel drive Hex- size 0 Hex- size 7 Drain-source voltage vs gate-source voltage at turn-on Time Hex- size 0 Hex- size Hex- size parallel drive Hex- size 0 Hex- size Drain-source voltage vs gate-source voltage at turn-off Time Hex- size Hex- size Hex- size parallel drive 7 synchronous buck regulator application PARAMETER vs PARAMETER FIGURE PAGE.-V -A Synchronous-Rectified Buck Regulator Circuit Q drain voltage vs gate voltage at turn-on 9 Q drain voltage vs gate voltage at turn-off 0 Q drain voltage vs Q gate-source voltage Time,,, 7 A 7 Output ripple voltage vs inductor current A 7 9

10 SLVSF NOVEMBER 99 REVISED OCTOBER 00 TYPICAL CHARACTERISTICS RISE TIME vs SUPPLY VOLTAGE FALL TIME vs SUPPLY VOLTAGE CL = nf CL = nf 0 0 Rise Time ns tr TA = C TA = 7 C Fall Time ns tf TA = C TA = 7 C TA = C T A = 0 C TA = C TA = 0 C VCC Supply Voltage V Figure VCC Supply Voltage V Figure PROPAGATION DELAY TIME, HIGH-TO-LOW-LEVEL OUTPUT vs SUPPLY VOLTAGE PROPAGATION DELAY TIME, LOW-TO-HIGH-LEVEL OUTPUT vs SUPPLY VOLTAGE CL = nf CL = nf t PHL Propagation Delay Time, High-To-Low-Level Output ns TA = C TA = 7 C T A = C TA = 0 C t PLH Propagation Delay Time, Low-To-High-Level Output ns TA = 7 C TA = C TA= C TA = C VCC Supply Voltage V Figure TA = 0 C VCC Supply Voltage V Figure 7 0

11 TYPICAL CHARACTERISTICS SLVSF NOVEMBER 99 REVISED OCTOBER 00 Supply Current ma I CC 0 Duty Cycle = 0% CL = nf SUPPLY CURRENT vs SUPPLY VOLTAGE MHz 00 khz 0 khz 7 khz 00 khz Supply Current ma I CC.. 0. VCC = 0 V f = 00 khz SUPPLY CURRENT vs LOAD CAPACITANCE 0 0 VCC Supply Voltage V Figure CL Load Capacitance nf Figure 9 SUPPLY CURRENT vs AMBIENT TEMPERATURE INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE Supply Current ma I CC CL = nf VCC = 0 V Duty Cycle = 0% f = 00 khz Input Threshold Voltage V V IT Threshold Threshold TA Temperature C Figure VCC Supply Voltage V Figure

12 SLVSF NOVEMBER 99 REVISED OCTOBER 00 TYPICAL CHARACTERISTICS REGULATOR OUTPUT VOLTAGE vs REGULATOR INPUT VOLTAGE REGULATOR OUTPUT VOLTAGE vs REGULATOR INPUT VOLTAGE Regulator Output Voltage V RL = 0 kω TA = C TA = C Regulator Output Voltage V RL = 0 kω TA = C TA = C 0 0 Regulator Input Voltage V Figure 0 Regulator Input Voltage V Figure REGULATOR QUIESCENT CURRENT vs REGULATOR INPUT VOLTAGE PEAK SOURCE CURRENT vs SUPPLY VOLTAGE µ A Regulator Quiescent Current TA = C TA = C RL = 0 kω Peak Source Current A... RL = 0. Ω f = 00 khz Duty Cycle = % Regulator Input Voltage V Figure 0 0 VCC Supply Voltage V Figure

13 TYPICAL CHARACTERISTICS SLVSF NOVEMBER 99 REVISED OCTOBER 00. RL = 0. Ω f = 00 khz Duty Cycle = % PEAK SINK CURRENT vs SUPPLY VOLTAGE Peak Sink Current A VCC Supply Voltage V Figure SHOOT-THROUGH CURRENT vs INPUT VOLTAGE, HIGH-TO-LOW SHOOT-THROUGH CURRENT vs INPUT VOLTAGE, LOW-TO-HIGH VCC = 0 V CL = 0 VCC = 0 V CL = 0 Shoot-Through Current ma Shoot-Through Current ma VI Input Voltage, High-to-Low V VI Input Voltage, Low-to-High V Figure 7 Figure

14 SLVSF NOVEMBER 99 REVISED OCTOBER 00 APPLICATION INFORMATION The TPS, TPS and TPS circuits each contain one regulator and two MOSFET drivers. The regulator can be used to limit V CC to between 0 V and V for a range of input voltages from V to 0 V, while providing up to 0 ma of dc drive. The TPS and TPS both contain two drivers, each of which has two inputs. The TPS has inverting drivers, the TPS has noninverting drivers, and the TPS has one inverting and one noninverting driver. The TPS is a dual -input AND driver with one inverting input on each driver, and the TPS is a dual -input NAND driver. These MOSFET drivers are capable of supplying up to. A or sinking up to.9 A (see Figures and ) of instantaneous current to n-channel or p-channel MOSFETs. The TPS family of MOSFET drivers have very fast switching times combined with very short propagation delays. These features enhance the operation of today s high-frequency circuits. The CMOS input circuit has a positive threshold of approximately / of V CC, with a negative threshold of / of V CC, and a very high input impedance in the range of 0 9 Ω. Noise immunity is also very high because of the Schmidt trigger switching. In addition, the design is such that the normal shoot-through current in CMOS (when the input is biased halfway between V CC and ground) is limited to less than ma. The limited shoot-through is evident in the graphs in Figures 7 and. The input stage shown in the functional block diagram better illustrates the way the front end works. The circuitry of the device is such that regardless of the rise and/or fall time of the input signal, the output signal will always have a fast transition speed; this basically isolates the waveforms at the input from the output. Therefore, the specified switching times are not affected by the slopes of the input waveforms. The basic driver portion of the circuits operate over a supply voltage range of V to V with a maximum bias current of µa. Each driver consists of a CMOS input and a buffered output with a -A instantaneous drive capability. They have propagation delays of less than 0 ns and rise and fall times of less than 0 ns each. Placing a 0.-µF ceramic capacitor between V CC and ground is recommended; this will supply the instantaneous current needed by the fast switching and high current surges of the driver when it is driving a MOSFET. The output circuit is also shown in the functional block diagram. This driver uses a unique combination of a bipolar transistor in parallel with a MOSFET for the ability to swing from V CC to ground while providing A of instantaneous driver current. This unique parallel combination of bipolar and MOSFET output transistors provides the drive required at V CC and ground to guarantee turn-off of even low-threshold MOSFETs. Typical bipolar-only output devices don t easily approach V CC or ground. The regulator, included in the TPS, TPS and TPS, has an input voltage range of V to 0 V. It produces an output voltage of 0 V to V and is capable of supplying from 0 to 0 ma of output current. In grounded source applications, this extends the overall circuit operation to 0 V by clamping the driver supply voltage (V CC ) to a safe level for both the driver and the MOSFET gate. The bias current for full operation is a maximum of 0 µa. A 0.-µF capacitor connected between the regulator output and ground is required to ensure stability. For transient response, an additional.7-µf electrolytic capacitor on the output and a 0.-µF ceramic capacitor on the input will optimize the performance of this circuit. When the regulator is not in use, it can be left open at both the input and the output, or the input can be shorted to the output and tied to either the V CC or the ground pin of the chip.

15 APPLICATION INFORMATION SLVSF NOVEMBER 99 REVISED OCTOBER 00 matching and paralleling connections Figures and show the delays for the rise and fall time of each channel. As can be seen on a -ns scale, there is very little difference between the two channels at no load. Figures and show the difference between the two channels for a -nf load on each output. There is a slight delay on the rising edge, but little or no delay on the falling edge. As an example of extreme overload, Figures and show the difference between the two channels, or two drivers in the package, each driving a 0-nF load. As would be expected, the rise and fall times are significantly slowed down. Figures and 9 show the effect of paralleling the two channels and driving a -nf load. A noticeable improvement is evident in the rise and fall times of the output waveforms. Finally, Figures 0 and show the two drivers being paralleled to drive the 0-nF load and as could be expected the waveforms are improved. In summary, the paralleling of the two drivers in a package enhances the capability of the drivers to handle a larger load. Because of manufacturing tolerances, it is not recommended to parallel drivers that are not in the same package. TPS Regulator VCC + 0. µf.7 µf 0 Ω 7 nf Output Figure 9. Test Circuit for Measuring Switching Characteristics TPS Regulator VCC + 0. µf.7 µf 0 Ω 7 CL() Output Output CL() NOTE A: Input rise and fall times should be 0 ns for accurate measurement of ac parameters. Figure 0. Test Circuit for Measuring Switching Characteristics with the Inputs Connected in Parallel

16 SLVSF NOVEMBER 99 REVISED OCTOBER 00 APPLICATION INFORMATION VO at OUT ( V/div, ns/div) VO at OUT ( V/div, ns/div) VI = V CL = 0 Paralleled Input VO at OUT ( V/div, ns/div) VO at OUT ( V/div, ns/div) VI = V CL = 0 Paralleled Inputs Figure. Voltage of OUT vs Voltage at OUT, Low-to-High Output Delay Figure. Voltage at OUT vs Voltage at OUT, High-to-Low Output Delay VO at OUT ( V/div, 0 ns/div) VO at OUT ( V/div, 0 ns/div) VI = V CL = nf on Each Output Paralleled Input VO at OUT ( V/div, 0 ns/div) VO at OUT ( V/div, 0 ns/div) VI = V CL = nf Each Output Paralleled Input Figure. Voltage at OUT vs Voltage at OUT, Low-to-High Output Delay Figure. Voltage at OUT vs Voltage at OUT, High-to-Low Output Delay

17 APPLICATION INFORMATION SLVSF NOVEMBER 99 REVISED OCTOBER 00 VO at OUT ( V/div, 0 ns/div) VO at OUT ( V/div, 0 ns/div) VO at ( V/div, 0 ns/div) VO at OUT ( V/div, 0 ns/div) VCC = V CL = 0 nf on Each Output Paralleled Input Figure. Voltage at OUT vs Voltage at OUT, Low-to-High Output Delay VCC = V CL = 0 nf on Each Output Paralleled Input Figure. Voltage at OUT vs Voltage at OUT, High-to-Low Output Delay TPS Regulator VCC + 0. µf.7 µf 0 Ω 7 CL Output NOTE A: Input rise and fall times should be 0 ns for accurate measurement of ac parameters. Figure 7. Test Circuit for Measuring Paralleled Switching Characteristics 7

18 SLVSF NOVEMBER 99 REVISED OCTOBER 00 APPLICATION INFORMATION VI ( V/div, 0 ns/div) VCC = V CL = nf Paralleled Input and Output VI ( V/div, 0 ns/div) VCC = V CL = nf Paralleled Input and Output VO ( V/div, 0 ns/div) VO ( V/div, 0 ns/div) Figure. Input Voltage vs Output Voltage, Low-to-High Propagation Delay of Paralleled Drivers Figure 9. Input Voltage vs Output Voltage, High-to-Low Propagation Delay of Paralleled Drivers VI ( V/div, 0 ns/div) VCC = V CL = 0 nf Paralleled Input and Output VI ( V/div, 0 ns/div) VO ( V/div, 0 ns/div) VCC = V CL = 0 nf Paralleled Input and Output VO ( V/div, 0 ns/div) Figure 0. Input Voltage vs Output Voltage, Low-to-High Propagation Delay of Paralleled Drivers Figure. Input Voltage vs Output Voltage, High-to-Low Propagation Delay of Paralleled Drivers

19 APPLICATION INFORMATION SLVSF NOVEMBER 99 REVISED OCTOBER 00 Figures through 7 illustrate the performance of the TPS driving MOSFETs with clamped inductive loads, similar to what is encountered in discontinuous-mode flyback converters. The MOSFETs that were tested range in size from Hex- to Hex-, although the TPSxx family is only recommended for Hex- or below. The test circuit is shown in Figure. The layout rules observed in building the test circuit also apply to real applications. Decoupling capacitor C is a 0.-µF ceramic device, connected between V CC and GND of the TPS, with short lead lengths. The connection between the driver output and the MOSFET gate, and between GND and the MOSFET source, are as short as possible to minimize inductance. Ideally, GND of the driver is connected directly to the MOSFET source. The tests were conducted with the pulse generator frequency set very low to eliminate the need for heat sinking, and the duty cycle was set to turn off the MOSFET when the drain current reached 0% of its rated value. The input voltage was adjusted to clamp the drain voltage at 0% of its rating. As shown, the driver is capable of driving each of the Hex- through Hex- MOSFETs to switch in 0 ns or less. Even the Hex- is turned on in less than 0 ns. Figures, and 7 show that paralleling the two drivers in a package enhances the gate waveforms and improves the switching speed of the MOSFET. Generally, one driver is capable of driving up to a Hex- size. The TPS family is even capable of driving large MOSFETs that have a low gate charge. L CR VI Current Loop Regulator 7 Q + VDS VDS VGS R 0 Ω VCC C 0. µf + C.7 µf Figure. TPS Driving Hex- through Hex- Devices 9

20 SLVSF NOVEMBER 99 REVISED OCTOBER 00 APPLICATION INFORMATION VCC = V VI = V VDS (0 V/div, 0. µs/div) VCC = V VI = V VDS (0 V/div, 0 ns/div) VGS ( V/div, 0 ns/div) ID (0. A/div, 0. µs/div) Figure. Drain-Source Voltage vs Drain Current, TPS Driving an IRFD0 (Hex- Size) Figure. Drain-Source Voltage vs Gate-Source Voltage, at Turn-on, TPS Driving an IRFD0 (Hex- Size) VCC = V VI = V VDS (0 V/div, 0 ns/div) VDS (0 V/div, 0. µs/div) VGS ( V/div, 0 ns/div) VCC = V VI = 0 V VGS (0. A/div, 0. µs/div) Figure. Drain-Source Voltage vs Gate-Source Voltage, at Turn-off, TPS Driving an IRFD0 (Hex- Size) Figure. Drain-Source Voltage vs Drain Current, TPS Driving an IRFD0 (Hex- Size) 0

21 APPLICATION INFORMATION SLVSF NOVEMBER 99 REVISED OCTOBER 00 VCC = V VI = 0 V VCC = V VI = 0 V VDS (0 V/div, 0 ns/div) VDS (0 V/div, 0 ns/div) VGS ( V/div, 0 ns/div) VGS ( V/div, 0 ns/div) Figure 7. Drain-Source Voltage vs Gate-Source Voltage, at Turn-on, TPS Driving an IRFD0 (Hex- Size) Figure. Drain-Source Voltage vs Gate-Source Voltage, at Turn-off, TPS Driving an IRFD0 (Hex- Size) VCC = V VI = 0 V VDS (0 V/div, 0 ns/div) VDS (0 V/div, µs/div) VCC = V VI = 0 V VGS ( A/div, 0 ns/div) ID ( A/div, µs/div) Figure 9. Drain-Source Voltage vs Drain Current, TPS Driving an IRF0 (Hex- Size) Figure 0. Drain-Source Voltage vs Gate-Source Voltage, at Turn-on, TPS Driving an IRF0 (Hex- Size)

22 SLVSF NOVEMBER 99 REVISED OCTOBER 00 APPLICATION INFORMATION VDS (0 V/div, 0. µs/div) VDS (0 V/div, 0 ns/div) VCC = V VI = 0 V VCC = V VI = 0 V ID ( A/div, 0. µs/div) VGS ( V/div, 0 ns/div) Figure. Drain-Source Voltage vs Drain Current, One Driver, TPS Driving an IRF0 (Hex- Size) Figure. Drain-Source Voltage vs Gate-Source Voltage, at Turn-off, TPS Driving an IRF0 (Hex- Size) VDS (0 V/div, 0 ns/div) VGS ( V/div, 0 ns/div) VDS (0 V/div, 0 ns/div) VGS ( V/div, 0 ns/div) VCC = V VI = 0 V Figure. Drain-Source Voltage vs Gate-Source Voltage, at Turn-on, One Driver, TPS Driving an IRF0 (Hex- Size) VCC = V VI = 0 V Figure. Drain-Source Voltage vs Gate-Source Voltage, at Turn-off, One Driver, TPS Driving an IRF0 (Hex- Size)

23 APPLICATION INFORMATION SLVSF NOVEMBER 99 REVISED OCTOBER 00 VDS (0 V/div, 0. µs/div) VDS (0 V/div, 0 ns/div) VCC = V VI = 0 V ID ( A/div, 0. µs/div) VGS ( V/div, 0 ns/div) VCC = V VI = 0 V Figure. Drain-Source Voltage vs Drain Current, Parallel Drivers, TPS Driving an IRF0 (Hex- Size) Figure. Drain-Source Voltage vs Gate-Source Voltage, at Turn-on, Parallel Drivers, TPS Driving an IRF0 (Hex- Size) VDS (0 V/div, 0 ns/div) VGS ( V/div, 0 ns/div) VCC = V VI = 0 V Figure 7. Drain-Source Voltage vs Gate-Source Voltage, at Turn-off, Parallel Drivers, TPS Driving an IRF0 (Hex- Size)

24 SLVSF NOVEMBER 99 REVISED OCTOBER 00 synchronous buck regulator APPLICATION INFORMATION Figure is the schematic for a 00-kHz synchronous-rectified buck converter implemented with a TL00 pulse-width-modulation (PWM) controller and a TPS driver. The bill of materials is provided in Table. The converter operates over an input range from. V to V and has a.-v output capable of supplying A continuously and A during load surges. The converter achieves an efficiency of 90.% at A and 7.% at A. Figures 9 and 0 show the power switch switching performance. The output ripple voltage waveforms are documented in Figures and. The TPS drives both the power switch, Q, and the synchronous rectifier, Q. Large shoot-through currents, caused by power switch and synchronous rectifier remaining on simultaneously during the transitions, are prevented by small delays built into the drive signals, using CR, CR, R, R, and the input capacitance of the TPS. These delays allow the power switch to turn off before the synchronous rectifier turns on and vice versa. Figure shows the delay between the drain of Q and the gate of Q; expanded views are provided in Figures and. Q IRF70 L 7 µf V I V I GND GND J C00 00 µf V REG_IN REG_OUT IN U OUT GND TPSD V CC IN OUT C 0.7 µf R 0 kω C 00 µf V 7 R 0 kω C 0. µf R Ω Q IRF70 CR 0BQ0 R7. Ω C 000 pf C 00 µf V + C 0.00 µf C7 00 µf V R. kω % R. kω C 0.0 µf C 0 µf 0 V R 0 Ω J C 0.0 µf. V. V GND GND CR CR R0 kω BASZX R 0 kω C µf OUT V CC COMP FB U TL00CD GND RT DTC SCP 7 R.00 kω % BASZX R 0 kω R kω % R kω % C9 0. µf + C µf Figure..-V -A Synchronous-Rectified Buck Regulator Circuit NOTE: If the parasitics of the external circuit cause the voltage to violate the Absolute Maximum Rating for the Output pins, Schottky diodes should be added from ground to output and from output to Vcc.

25 APPLICATION INFORMATION SLVSF NOVEMBER 99 REVISED OCTOBER 00 Table. Bill of Materials,.-V, -A Synchronous-Rectified Buck Converter REFERENCE DESCRIPTION VENDOR U TL00CD, PWM Texas Instruments, U TPSD, N.I. MOSFET Driver Texas Instruments, CR A, V, Schottky, 0BQ0 International Rectifier, 0-- CR,CR Signal Diode, BASZX Zetex, C C C C µf, V, Tantalum 0.0 µf, 0 V 0.00 µf, 0 V 0.0 µf, 0 V C,C7,C0,C 00 µf, V, Tantalum, TPSE07M0R000 AVX, C C9 C 000 pf, 0 V 0. µf, 0 V 0.7 µf, 0 V, ZU C 0 µf, 0 V, Ceramic, CC0CYV0Z TDK, C C J,J 0. µf, 0 V.0 µf, 0 V -Pin Header L 7 µh, A/ A, SML00 Nova Magnetics, Inc., Q IRF70, P-FET International Rectifier, 0-- Q IRF70, N-FET International Rectifier, 0-- R.00 kω, % R R. kω 0 Ω R. kω, % R,R,R R R7 0 kω Ω. Ω R kω, % R kω, % R0 kω R 0 kω NOTES:. Unless otherwise specified, capacitors are X7R ceramics.. Unless otherwise specified, resistors are %, /0 W.

26 SLVSF NOVEMBER 99 REVISED OCTOBER 00 APPLICATION INFORMATION VD ( V/div, 0 ns/div) VG ( V/div, 0 ns/div) VD ( V/div, 0 ns/div) VI = V VO =. V at A VG ( V/div, 0 ns/div) VI = V VO =. V at A Figure 9. Q Drain Voltage vs Gate Voltage, at Switch Turn-on Figure 0. Q Drain Voltage vs Gate Voltage, at Switch Turn-off VD ( V/div, 0. µs/div) VI = V VO =. V at A VI = V VO =. V at A VD ( V/div, 0 ns/div) VGS ( V/div, 0. µs/div) VGS ( V/div, 0 ns/div) Figure. Q Drain Voltage vs Q Gate-Source Voltage Figure. Q Drain Voltage vs Q Gate-Source Voltage

27 APPLICATION INFORMATION SLVSF NOVEMBER 99 REVISED OCTOBER 00 VI = V VO =. V at A VD ( V/div, 0 ns/div) VGS ( V/div, 0 ns/div) Figure. Q Drain Voltage vs Q Gate-Source Voltage VI = V VO =. V at A Inductor Current ( A/div, µs/div) Inductor Current ( A/div, µs/div) VI = V VO =. V at A Output Ripple Voltage (0 mv/div, µs/div) Output Ripple Voltage (0 mv/div, µs/div) Figure. Output Ripple Voltage vs Inductor Current, at A Figure. Output Ripple Voltage vs Inductor Current, at A 7

28 PACKAGE OPTION ADDENDUM -Aug-0 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan TPSD ACTIVE SOIC D 7 Green (RoHS TPSDR ACTIVE SOIC D 00 Green (RoHS TPSP ACTIVE PDIP P 0 Green (RoHS TPSPW ACTIVE TSSOP PW 0 Green (RoHS TPSPWR ACTIVE TSSOP PW 000 Green (RoHS TPSD ACTIVE SOIC D 7 Green (RoHS TPSDR ACTIVE SOIC D 00 Green (RoHS TPSDRG ACTIVE SOIC D 00 Green (RoHS TPSP ACTIVE PDIP P 0 Green (RoHS TPSPWR ACTIVE TSSOP PW 000 Green (RoHS TPSD ACTIVE SOIC D 7 Green (RoHS TPSDR ACTIVE SOIC D 00 Green (RoHS TPSP ACTIVE PDIP P 0 Green (RoHS TPSPWR ACTIVE TSSOP PW 000 Green (RoHS TPSD ACTIVE SOIC D 7 Green (RoHS TPSDR ACTIVE SOIC D 00 Green (RoHS TPSDRG ACTIVE SOIC D 00 Green (RoHS () Lead/Ball Finish () MSL Peak Temp () Op Temp ( C) Device Marking (/) CU NIPDAU Level--0C-UNLIM CU NIPDAU Level--0C-UNLIM -0 to CU NIPDAU N / A for Pkg Type TPSP CU NIPDAU Level--0C-UNLIM PS CU NIPDAU Level--0C-UNLIM PS CU NIPDAU Level--0C-UNLIM -0 to CU NIPDAU Level--0C-UNLIM CU NIPDAU Level--0C-UNLIM CU NIPDAU N / A for Pkg Type TPSP CU NIPDAU Level--0C-UNLIM PS CU NIPDAU Level--0C-UNLIM -0 to CU NIPDAU Level--0C-UNLIM -0 to CU NIPDAU N / A for Pkg Type -0 to TPSP CU NIPDAU Level--0C-UNLIM -0 to PS CU NIPDAU Level--0C-UNLIM CU NIPDAU Level--0C-UNLIM -0 to CU NIPDAU Level--0C-UNLIM -0 to Samples Addendum-Page

29 PACKAGE OPTION ADDENDUM -Aug-0 Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan TPSP ACTIVE PDIP P 0 Green (RoHS TPSPE ACTIVE PDIP P 0 Green (RoHS TPSPW ACTIVE TSSOP PW 0 Green (RoHS TPSPWR ACTIVE TSSOP PW 000 Green (RoHS TPSD ACTIVE SOIC D 7 Green (RoHS TPSDG ACTIVE SOIC D 7 Green (RoHS TPSDR ACTIVE SOIC D 00 Green (RoHS TPSP ACTIVE PDIP P 0 Green (RoHS TPSPWR ACTIVE TSSOP PW 000 Green (RoHS () Lead/Ball Finish () MSL Peak Temp () Op Temp ( C) Device Marking (/) CU NIPDAU N / A for Pkg Type TPSP CU NIPDAU N / A for Pkg Type TPSP CU NIPDAU Level--0C-UNLIM PS CU NIPDAU Level--0C-UNLIM -0 to PS CU NIPDAU Level--0C-UNLIM CU NIPDAU Level--0C-UNLIM CU NIPDAU Level--0C-UNLIM -0 to CU NIPDAU N / A for Pkg Type TPSP CU NIPDAU Level--0C-UNLIM PS Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 0 RoHS substances, including the requirement that RoHS substance do not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=000ppm threshold. Antimony trioxide based flame retardants must also meet the <=000ppm threshold requirement. () MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page

30 PACKAGE OPTION ADDENDUM -Aug-0 () Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. () Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS : Automotive: TPS-Q NOTE: Qualified Version Definitions: Automotive - Q00 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page

31 PACKAGE MATERIALS INFORMATION 0-Oct-0 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant TPSDR SOIC D Q TPSPWR TSSOP PW Q TPSDR SOIC D Q TPSDR SOIC D Q TPSPWR TSSOP PW Q TPSDR SOIC D Q TPSPWR TSSOP PW Q TPSDR SOIC D Q TPSDR SOIC D Q TPSPWR TSSOP PW Q TPSDR SOIC D Q TPSPWR TSSOP PW Q Pack Materials-Page

32 PACKAGE MATERIALS INFORMATION 0-Oct-0 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPSDR SOIC D TPSPWR TSSOP PW TPSDR SOIC D TPSDR SOIC D TPSPWR TSSOP PW TPSDR SOIC D TPSPWR TSSOP PW TPSDR SOIC D TPSDR SOIC D TPSPWR TSSOP PW TPSDR SOIC D TPSPWR TSSOP PW Pack Materials-Page

33

34

35

36 SCALE.00 PW000A PACKAGE OUTLINE TSSOP -. mm max height SMALL OUTLINE PACKAGE. TYP. SEATING PLANE C A PIN ID AREA 0. C X NOTE X.9 B.. NOTE X C A B. MAX SEE DETAIL A (0.) TYP 0. GAGE PLANE DETAIL A TYPICAL /A 0/0 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y.M.. This drawing is subject to change without notice.. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0. mm per side.. This dimension does not include interlead flash. Interlead flash shall not exceed 0. mm per side.. Reference JEDEC registration MO-, variation AA.

37 PW000A EXAMPLE BOARD LAYOUT TSSOP -. mm max height SMALL OUTLINE PACKAGE X (0.) X (.) SYMM (R 0.0) TYP SYMM X (0.) (.) LAND PATTERN EXAMPLE SCALE:0X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.0 MAX ALL AROUND 0.0 MIN ALL AROUND NON SOLDER MASK DEFINED SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE /A 0/0 NOTES: (continued). Publication IPC-7 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

38 PW000A EXAMPLE STENCIL DESIGN TSSOP -. mm max height SMALL OUTLINE PACKAGE X (0.) X (.) SYMM (R 0.0) TYP SYMM X (0.) (.) SOLDER PASTE EXAMPLE BASED ON 0. mm THICK STENCIL SCALE:0X /A 0/0 NOTES: (continued). Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

39 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES AS IS AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for () selecting the appropriate TI products for your application, () designing, validating and testing your application, and () ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI s products are provided subject to TI s Terms of Sale (/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI s provision of these resources does not expand or otherwise alter TI s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 0, Dallas, Texas 7 Copyright 0, Texas Instruments Incorporated