SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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1 Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Noninverting Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads Low Power Consumption, 80-μA Max I CC Typical t pd = 22 ns ±6-mA Output Drive at 5 V Low Input Current of 1 μa Max Bus-Structured Pinout description/ordering information These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F DECEMBER 1982 REVISED AUGUST 2003 ORDERING INFORMATION T A PACKAGE ORDERABLE TOP-SIDE PART NUMBER MARKING PDIP N Tube of 20 SN74HC574N SN74HC574N Tube of 25 SN74HC574DW SOIC DW Reel of 2000 SN74HC574DWR HC574 SSOP DB Reel of 2000 SN74HC574DBR HC C to85 C SOP NS Reel of 2000 SN74HC574NSR HC574 Tube of 70 SN74HC574PW TSSOP PW Reel of 2000 SN74HC574PWR HC574 Reel of 250 SN54HC574...J OR W PACKAGE SN74HC DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) SN74HC574PWT SN54HC FK PACKAGE (TOP VIEW) CDIP J Tube of 20 SNJ54HC574J SNJ54HC574J 55 C to 125 C CFP W Tube of 85 SNJ54HC574W SNJ54HC574W LCCC FK Tube of 55 SNJ54HC574FK SNJ54HC574FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at 3D 4D 5D 6D 7D OE 1D 2D 3D 4D 5D 6D 7D 8D GND D 1D 8D GND CLK OE 1Q 8Q 7Q 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 2Q 3Q 4Q 5Q 6Q Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX DALLAS, TEXAS

2 SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F DECEMBER 1982 REVISED AUGUST 2003 description/ordering information (continued) OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L H H L L L L H or L X Q 0 H X X Z logic diagram (positive logic) OE 1 CLK 11 1D 2 1D C1 19 1Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V to 7 V Input clamp current, I IK (V I < 0 or V I > ) (see Note 1) ±20 ma Output clamp current, I OK (V O < 0 or V O > ) (see Note 1) ±20 ma Continuous output current, I O (V O = 0 to ) ±35 ma Continuous current through or GND ±70 ma Package thermal impedance, θ JA (see Note 2): DB package C/W DW package C/W N package C/W NS package C/W PW package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DALLAS, TEXAS 75265

3 recommended operating conditions (see Note 3) SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F DECEMBER 1982 REVISED AUGUST 2003 SN54HC574 SN74HC574 MIN NOM MAX MIN NOM MAX Supply voltage V = 2 V V IH High-level input voltage = 4.5 V V = 6 V = 2 V V IL Low-level input voltage = 4.5 V V = 6 V V I Input voltage 0 0 V V O Output voltage 0 0 V = 2 V Δt/Δv Input transition rise/fall time = 4.5 V ns = 6 V T A Operating free-air temperature C NOTE 3: All unused inputs of the device must be held at or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) UNIT T A = 25 C SN54HC574 SN74HC574 PARAMETER TEST CONDITIONS MIN TYP MAX MIN MAX MIN MAX UNIT V OH V I = V IH or V IL 2 V V V I OH = 20 μa 4.5 V I OH = 6 ma 4.5 V V OL V I = V IH or V IL I OH = 7.8 ma 6 V V V V I OL = 20 μa 4.5 V I OL = 6 ma 4.5 V I OL = 7.8 ma 6 V I I V I = or 0 6 V ±0.1 ±100 ±1000 ±1000 na I OZ V O = or 0 6 V ±0.01 ±0.5 ±10 ±5 μa I CC V I = or 0, I O = 0 6 V μa C i 2 V to 6 V pf POST OFFICE BOX DALLAS, TEXAS

4 SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F DECEMBER 1982 REVISED AUGUST 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) T A = 25 C SN54HC574 SN74HC574 MIN MAX MIN MAX MIN MAX UNIT 2 V f clock Clock frequency 4.5 V MHz 6 V V t w Pulse duration, CLK high or low 4.5 V ns 6 V V t su Setup time, data before CLK 4.5 V ns 6 V V t h Hold time, data after CLK 4.5 V ns 6 V switching characteristics over recommended operating free-air temperature range, C L = 50 pf (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) T A = 25 C SN54HC574 SN74HC574 MIN TYP MAX MIN MAX MIN MAX 2 V f max 4.5 V MHz 6 V UNIT 2 V t pd CLK Any Q 4.5 V ns 6 V V t en OE Any Q 4.5 V ns 6 V V t dis OE Any Q 4.5 V ns 6 V V t t Any yq 4.5 V ns 6 V POST OFFICE BOX DALLAS, TEXAS 75265

5 SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F DECEMBER 1982 REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, C L = 150 pf (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) T A = 25 C SN54HC574 SN74HC574 MIN TYP MAX MIN MAX MIN MAX 2 V 6 5 f max 4.5 V MHz 6 V UNIT 2 V t pd CLK Any Q 4.5 V ns 6 V V t en OE Any Q 4.5 V ns 6 V V t t Any yq 4.5 V ns 6 V operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS TYP UNIT C pd Power dissipation capacitance per flip-flop No load 100 pf POST OFFICE BOX DALLAS, TEXAS

6 SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F DECEMBER 1982 REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION PARAMETER R L C L S1 S2 From Output Under Test C L (see Note A) Test Point R L LOAD CIRCUIT S1 S2 t PZH t en t PZL t PHZ t dis t PLZ t pd or t t 1 kω 1 kω 50 pf or 150 pf 50 pf 50 pf or 150 pf Open Closed Open Closed Open Closed Open Closed Open Open High-Level Pulse Low-Level Pulse t w VOLTAGE WAVEFORMS PULSE DURATIONS 0 V 0 V Reference Input Data Input 10% t su VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES t h 90% 90% t r 0 V 10% 0 V t f Input In-Phase Output t PLH 10% t PHL 90% 90% t r t PHL t PLH 0 V V OH 10% V OL t f Output Control (Low-Level Enabling) t PZL Output Waveform 1 (See Note B) t PZH t PLZ 10% t PHZ 0 V V OL Out-of- Phase Output 90% 10% 10% t f V OH 90% V OL t r Output Waveform 2 (See Note B) 90% V OH 0 V VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, Z O = 50 Ω, t r = 6 ns, t f = 6 ns. D. For clock inputs, f max is measured when the input duty cycle is. E. The outputs are measured one at a time with one input transition per measurement. F. t PLZ and t PHZ are the same as t dis. G. t PZL and t PZH are the same as t en. H. t PLH and t PHL are the same as t pd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 PACKAGE OPTION ADDENDUM 26-Sep-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) JM38510/65604BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65604BRA M38510/65604BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 65604BRA SN54HC574J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC574J Device Marking (4/5) Samples SN74HC574APWR ACTIVE TSSOP PW Green (RoHS & no Sb/Br) SN74HC574DBR ACTIVE SSOP DB Green (RoHS & no Sb/Br) SN74HC574DBRG4 ACTIVE SSOP DB Green (RoHS & no Sb/Br) SN74HC574DW ACTIVE SOIC DW Green (RoHS & no Sb/Br) SN74HC574DWG4 ACTIVE SOIC DW Green (RoHS & no Sb/Br) SN74HC574DWR ACTIVE SOIC DW Green (RoHS & no Sb/Br) SN74HC574N ACTIVE PDIP N Pb-Free (RoHS) SN74HC574NE4 ACTIVE PDIP N Pb-Free (RoHS) SN74HC574NSR ACTIVE SO NS Green (RoHS & no Sb/Br) SN74HC574PW ACTIVE TSSOP PW Green (RoHS & no Sb/Br) SN74HC574PWR ACTIVE TSSOP PW Green (RoHS & no Sb/Br) SN74HC574PWRG4 ACTIVE TSSOP PW Green (RoHS & no Sb/Br) SN74HC574PWT ACTIVE TSSOP PW Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC574A CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 CU NIPDAU CU SN Level-1-260C-UNLIM -40 to 85 HC574 CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC574N CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC574N CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 CU NIPDAU CU SN Level-1-260C-UNLIM -40 to 85 HC574 CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 SNJ54HC574FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54HC 574FK Addendum-Page 1

8 PACKAGE OPTION ADDENDUM 26-Sep-2018 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) SNJ54HC574J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54HC574J Device Marking (4/5) Samples SNJ54HC574W ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 SNJ54HC574W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC574, SN74HC574 : Addendum-Page 2

9 PACKAGE OPTION ADDENDUM 26-Sep-2018 Catalog: SN74HC574 Military: SN54HC574 NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications Addendum-Page 3

10 PACKAGE MATERIALS INFORMATION 27-Sep-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74HC574APWR TSSOP PW Q1 SN74HC574DBR SSOP DB Q1 SN74HC574DWR SOIC DW Q1 SN74HC574DWR SOIC DW Q1 SN74HC574NSR SO NS Q1 SN74HC574PWR TSSOP PW Q1 SN74HC574PWT TSSOP PW Q1 Pack Materials-Page 1

11 PACKAGE MATERIALS INFORMATION 27-Sep-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC574APWR TSSOP PW SN74HC574DBR SSOP DB SN74HC574DWR SOIC DW SN74HC574DWR SOIC DW SN74HC574NSR SO NS SN74HC574PWR TSSOP PW SN74HC574PWT TSSOP PW Pack Materials-Page 2

SCALE 1.200 DW0020A PACKAGE OUTLINE SOIC - 2.65 mm max height SOIC C 10.63 TYP 9.97 SEATING PLANE A 1 PIN 1 ID AREA 20 18X 1.27 0.1 C 13.0 12.6 NOTE 3 2X 11.43 10 B 7.6 7.4 NOTE 4 11 20X 0.51 0.31 0.

13 SCALE DW0020A PACKAGE OUTLINE SOIC mm max height SOIC C TYP 9.97 SEATING PLANE A 1 PIN 1 ID AREA 20 18X C NOTE 3 2X B NOTE X C A B 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE DETAIL A TYPICAL /A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS

14 DW0020A EXAMPLE BOARD LAYOUT SOIC mm max height SOIC 20X (2) SYMM X (0.6) 18X (1.27) SYMM (R 0.05) TYP (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.07 MAX ALL AROUND NON SOLDER MASK DEFINED 0.07 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS /A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

15 DW0020A EXAMPLE STENCIL DESIGN SOIC mm max height SOIC 20X (0.6) 20X (2) 1 SYMM 20 18X (1.27) SYMM (9.3) SOLDER PASTE EXAMPLE BASED ON mm THICK STENCIL SCALE:6X /A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

22 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

23 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES AS IS AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI s products are provided subject to TI s Terms of Sale ( or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI s provision of these resources does not expand or otherwise alter TI s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box , Dallas, Texas Copyright 2018, Texas Instruments Incorporated

Data sheet acquired from Harris Semiconductor SCHS038C Revised October 2003

Data sheet acquired from Harris Semiconductor SCHS038C Revised October 2003 The CD4035B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages