SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

Size: px

Start display at page:

Download "SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS"

Gary Hood
5 years ago
Views:

1 State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 ma Per JEDEC Standard JESD-17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pf, R = 0) Typical V OLP (Output Ground Bounce) < 1 V at V CC = 5 V, T A = 25 C High-Drive Outputs ( 32-mA I OH, 64-mA I OL ) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS184D JANUARY 1991 REVISED JANUARY 1997 SN54ABT241...J OR W PACKAGE SN74ABT241A... DB, DW, N, OR PW PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 SN54ABT FK PACKAGE (TOP VIEW) description These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT240, SN74ABT240A, and ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE) inputs, and complementary OE and OE inputs To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The SN54ABT241 is characterized for operation over the full military temperature range of 55 C to 125 C. The SN74ABT241A is characterized for operation from 40 C to 85 C. 1A2 2Y3 1A3 2Y2 1A4 2Y4 1A1 2Y1 GND 2A1 1OE 1Y4 V CC 2A2 2OE 1Y1 2A4 1Y2 2A3 1Y3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS184D JANUARY 1991 REVISED JANUARY 1997 FUNCTION TABLES INPUTS OUTPUT 1OE 1A 1Y L H H L L L H X Z INPUTS OUTPUT 2OE 2A 2Y H H H H L L L X Z logic symbol 1OE 1 EN 2OE 19 EN 1A1 1A2 1A3 1A Y1 1Y2 1Y3 1Y4 2A1 2A2 2A3 2A Y1 2Y2 2Y3 2Y4 This symbol is in accordance with ANSI/IEEE Std and IEC Publication logic diagram (positive logic) 1OE 1 2OE 19 1A Y1 2A Y1 1A Y2 2A Y2 1A Y3 2A Y3 1A Y4 2A Y4 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS184D JANUARY 1991 REVISED JANUARY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (see Note 1) V to 7 V Voltage range applied to any output in the high or power-off state, V O V to 5.5 V Current into any output in the low state, I O : SN54ABT ma SN74ABT241A ma Input clamp current, I IK (V I < 0) ma Output clamp current, I OK (V O < 0) ma Package thermal impedance, θ JA (see Note 2): DB package C/W DW package C/W N package C/W PW package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) SN54ABT241 SN74ABT241A UNIT MIN MAX MIN MAX VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V VI Input voltage 0 VCC 0 VCC V IOH High-level output current ma IOL Low-level output current ma t/ v Input transition rise or fall rate Outputs enabled 5 5 ns/v TA Operating free-air temperature C NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX DALLAS, TEXAS

4 SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS184D JANUARY 1991 REVISED JANUARY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25 C SN54ABT241 SN74ABT241A MIN TYP MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = 18 ma V VOH VCC = 4.5 V, IOH = 3 ma VCC = 5 V, IOH = 3 ma VCC =45V 4.5 VOL VCC =45V 4.5 IOH = 24 ma 2 2 IOH = 32 ma 2* 2 IOL = 48 ma IOL = 64 ma 0.55* 0.55 Vhys 100 mv II VCC = 5.5 V, VI = VCC or GND ±1 ±1 ±1 µa IOZH VCC = 5.5 V, VO = 2.7 V µa IOZL VCC = 5.5 V, VO = 0.5 V µa Ioff VCC = 0, VI or VO 4.5 V ±100 ±100 µa ICEX VCC = 5.5 V, VO = 5.5 V Outputs high µa IO VCC = 5.5 V, VO = 2.5 V ma ICC ICC Data inputs Control inputs VCC = V, IO = 0, VI =VCC or GND UNIT Outputs high µa Outputs low ma Outputs disabled µa VCC = 5.5 V, One input at 3.4 V, Outputs enabled Other inputs at VCC or GND Outputs disabled ma VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V 4 pf Co VO = 2.5 V or 0.5 V 5.5 pf * On products compliant to MIL-PRF-38535, this parameter does not apply. All typical values are at VCC = 5 V. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. V V 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS184D JANUARY 1991 REVISED JANUARY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C L = 50 pf (unless otherwise noted) (see Figure 1) SN54ABT241 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25 C MIN MAX UNIT MIN TYP MAX tplh tphl A Y ns tpzh tpzl OE or OE Y ns tphz tplz OE or OE Y ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C L = 50 pf (unless otherwise noted) (see Figure 1) SN74ABT241A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25 C MIN MAX UNIT MIN TYP MAX tplh tphl A Y ns tpzh tpzl OE or OE Y ns tphz tplz OE or OE Y ns POST OFFICE BOX DALLAS, TEXAS

6 SN54ABT241, SN74ABT241A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS184D JANUARY 1991 REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S1 7 V Open GND TEST tplh/tphl tplz/tpzl tphz/tpzh S1 Open 7 V Open LOAD CIRCUIT Timing Input 3 V 0 V Input tw 3 V 0 V Data Input tsu th 3 V 0 V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input Output Output tplh tphl tphl tplh VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3 V 0 V VOH VOL VOH VOL Output Control Output Waveform 1 S1 at 7 V (see Note B) Output Waveform 2 S1 at Open (see Note B) tpzl tpzh tplz tphz VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING 3 V 0 V 3.5 V VOL V VOL VOH VOH 0.3 V 0 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 PACKAGE OPTION ADDENDUM 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to Q2A SNJ54ABT 241FK Device Marking QRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to QR A SNJ54ABT241J QSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to QS A SNJ54ABT241W SN74ABT241ADBR ACTIVE SSOP DB Green (RoHS & no Sb/Br) SN74ABT241ADW ACTIVE SOIC DW Green (RoHS & no Sb/Br) SN74ABT241ADWR ACTIVE SOIC DW Green (RoHS & no Sb/Br) SN74ABT241ADWRE4 ACTIVE SOIC DW Green (RoHS & no Sb/Br) SN74ABT241AN ACTIVE PDIP N Pb-Free (RoHS) SN74ABT241APW ACTIVE TSSOP PW Green (RoHS & no Sb/Br) SN74ABT241APWR ACTIVE TSSOP PW Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB241A CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT241A CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT241A CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT241A CU NIPDAU N / A for Pkg Type -40 to 85 SN74ABT241AN CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB241A CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB241A SNJ54ABT241FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to Q2A SNJ54ABT 241FK SNJ54ABT241J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to QR A SNJ54ABT241J SNJ54ABT241W ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to QS A SNJ54ABT241W (4/5) Samples (1) The marketing status values are defined as follows: Addendum-Page 1

8 PACKAGE OPTION ADDENDUM 17-Mar-2017 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT241 : Catalog: SN74ABT241 NOTE: Qualified Version Definitions: Addendum-Page 2

9 PACKAGE OPTION ADDENDUM 17-Mar-2017 Catalog - TI's standard catalog product Addendum-Page 3

10 PACKAGE MATERIALS INFORMATION 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74ABT241ADBR SSOP DB Q1 SN74ABT241ADWR SOIC DW Q1 SN74ABT241APWR TSSOP PW Q1 Pack Materials-Page 1

11 PACKAGE MATERIALS INFORMATION 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT241ADBR SSOP DB SN74ABT241ADWR SOIC DW SN74ABT241APWR TSSOP PW Pack Materials-Page 2

17 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

SCALE 1.200 DW0020A PACKAGE OUTLINE SOIC - 2.65 mm max height SOIC C 10.63 TYP 9.97 SEATING PLANE A 1 PIN 1 ID AREA 20 18X 1.27 0.1 C 13.0 12.6 NOTE 3 2X 11.43 10 B 7.6 7.4 NOTE 4 11 20X 0.51 0.31 0.

19 SCALE DW0020A PACKAGE OUTLINE SOIC mm max height SOIC C TYP 9.97 SEATING PLANE A 1 PIN 1 ID AREA 20 18X C NOTE 3 2X B NOTE X C A B 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE DETAIL A TYPICAL /A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS

20 DW0020A EXAMPLE BOARD LAYOUT SOIC mm max height SOIC 20X (2) SYMM X (0.6) 18X (1.27) SYMM (R 0.05) TYP (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.07 MAX ALL AROUND NON SOLDER MASK DEFINED 0.07 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS /A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

21 DW0020A EXAMPLE STENCIL DESIGN SOIC mm max height SOIC 20X (0.6) 20X (2) 1 SYMM 20 18X (1.27) SYMM (9.3) SOLDER PASTE EXAMPLE BASED ON mm THICK STENCIL SCALE:6X /A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS Typical V OLP (Output Ground Bounce)