Single 3-Input Positive-XOR Gate Check for Samples: SN74LVC1G386

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1 1 SN74LVC1G386 SCES439E APRIL 2003 REVISED DECEMBER 2013 Single 3-Input Positive-XOR Gate Check for Samples: SN74LVC1G386 1FEATURES DESCRIPTION 2 Available in the Texas Instruments The SN74LVC1G386 device performs the Boolean NanoStar and NanoFree function Y = A B C in positive logic. Packages NanoStar and NanoFree package technology is Supports 5-V Operation a major breakthrough in IC packaging concepts, using the die as the package. Inputs Accept Voltages to 5.5 V Supports Down Translation to This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the I off Supports Live Insertion, Partial-Poweroutputs, preventing damaging current backflow Down Mode, Back-Drive Protection through the device when it is powered down. Latch-Up Performance Exceeds 100 ma Per JESD 78, Class II ESD Protection Exceeds JESD V Human-Body Model (A114-A) 200-achine Model (A115-A) 1000-V Charged-Device Model (C101) DBV PACKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) A GND C A GND B 1 6 C Y B GND A 3 4 Y C B 3 4 Y GND DRY PACKAGE (TOP VIEW) A 1 6 B C Y A GND B DSF PACKAGE (TOP VIEW) C Y See mechanical drawings for dimensions. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright , Texas Instruments Incorporated

2 SN74LVC1G386 SCES439E APRIL 2003 REVISED DECEMBER 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. INPUTS Function Table A B C OUTPUT Y L L L L L L H H L H L H L H H L H L L H H L H L H H L L H H H H Logic Diagram (Positive Logic) A B Y C Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Supply voltage range V V I Input voltage range (2) V V O Voltage range applied to any output in the high-impedance or power-off state (2) V V O Voltage range applied to any output in the high or low state (2)(3) V I IK Input clamp current V I < 0 50 ma I OK Output clamp current V O < 0 50 ma I O Continuous output current ±50 ma Continuous current through or GND ±100 ma DBV package 165 θ JA Package thermal impedance (4) DCK package 259 C/W YEP or YZP package 123 T stg Storage temperature range C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of is provided in the recommended operating conditions table. (4) The package thermal impedance is calculated in accordance with JESD Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: SN74LVC1G386

3 Recommended Operating Conditions (1) MIN MAX UNIT SN74LVC1G386 SCES439E APRIL 2003 REVISED DECEMBER 2013 Operating Supply voltage V Data retention only 1.5 = 1.65 V to 1.95 V 0.65 = 2.3 V to 2.7 V 1.7 V IH High-level input voltage V = 3 V to 3.6 V 2 = 4.5 V to 5.5 V = 1.65 V to 1.95 V = 2.3 V to 2.7 V 0.7 V IL Low-level input voltage V = 3 V to 3.6 V 0.8 = 4.5 V to 5.5 V 0.3 V I Input voltage V V O Output voltage 0 V = 1.65 V 4 = 2.3 V 8 I OH High-level output current 16 ma = 3 V 24 = 4.5 V 32 = 1.65 V 4 = 2.3 V 8 I OL Low-level output current 16 ma = 3 V 24 = 4.5 V 32 = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 Δt/Δv Input transition rise or fall rate = 3.3 V ± 0.3 V 10 ns/v = 5 V ± 0.5 V 5 T A Operating free-air temperature C (1) All unused inputs of the device must be held at or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Copyright , Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN74LVC1G386

4 SN74LVC1G386 SCES439E APRIL 2003 REVISED DECEMBER 2013 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) V OH V OL 40 C to 85 C 40 C to 125 C PARAMETER TEST CONDITIONS UNIT MIN TYP (1) MAX MIN TYP (1) MAX 1.65 V to I OH = 100 µa V I OH = 4 ma 1.65 V I OH = 8 ma 2.3 V I OH = 16 ma V I OH = 24 ma I OH = 32 ma 4.5 V V to I OL = 100 µa V I OL = 4 ma 1.65 V I OL = 8 ma 2.3 V I OL = 16 ma V I OL = 24 ma I OL = 32 ma 4.5 V I I All inputs V I = 5.5 V or GND 0 to 5.5 V ±5 ±5 µa I off V I or V O = 5.5 V 0 ±10 ±10 µa 1.65 V to I CC V I = 5.5 V or GND, I O = µa 5.5 V One input at 0.6 V, ΔI CC 3 V to 5.5 V µa Other inputs at or GND C i V I = or GND 3.3 V 3.5 pf (1) All typical values are at = 3.3 V, T A = 25 C. V V 4 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: SN74LVC1G386

5 SN74LVC1G386 SCES439E APRIL 2003 REVISED DECEMBER 2013 Switching Characteristics over recommended operating free-air temperature range, C L = 15 pf (unless otherwise noted) (see Figure 1) PARAMETER 40 C to 85 C FROM TO = 1.8 V = 2.5 V = 3.3 V = 5 V (INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX t pd A, B, or C Y ns Switching Characteristics over recommended operating free-air temperature range, C L = 30 pf or 50 pf (unless otherwise noted) (see Figure 2) PARAMETER 40 C to 85 C FROM TO = 1.8 V = 2.5 V = 3.3 V = 5 V (INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX t pd A, B, or C Y ns Switching Characteristics over recommended operating free-air temperature range, C L = 30 pf or 50 pf (unless otherwise noted) (see Figure 2) PARAMETER 40 C to 125 C FROM TO = 1.8 V = 2.5 V = 3.3 V = 5 V (INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX t pd A, B, or C Y ns Operating Characteristics T A = 25 C = 1.8 V = 2.5 V = 3.3 V = 5 V PARAMETER TEST CONDITIONS UNIT TYP TYP TYP TYP C pd Power dissipation capacitance f = 10 MHz pf Copyright , Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN74LVC1G386

6 SN74LVC1G386 SCES439E APRIL 2003 REVISED DECEMBER 2013 Parameter Measurement Information From Output Under Test CL (see Note A) R L R L S1 V LOAD Open GND TEST S1 V LOAD t PZL (see Notes E and F) t PLZ (see Notes E and G) V LOAD t PHZ/tPZH V LOAD LOAD CIRCUIT INPUTS V I t r/tf V LOAD C L R L V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 3 V 2 ns 2 ns 2.5 ns 2.5 ns VCC/2 /2 1.5 V / V 2 15 pf 15 pf 15 pf 15 pf 1 MΩ 1 MΩ 1 MΩ 1 MΩ 0.15 V 0.15 V 0.3 V 0.3 V Timing Input V I 0 V t W V I t su t h Input VOLTAGE WAVEFORMS PULSE DURATION 0 V Data Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES V I 0 V Input V I 0 V Output Control V I 0 V Output t PLH t PHL V OH V OL Output Waveform 1 S1 at VLOAD (see Note B) t PZL V OL t PLZ + V V LOAD/2 V OL t PHL t PLH t PZH t PHZ Output V OH V OL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING V OH V V OH 0 V NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators have the following characteristics: PRR 10 MHz, Z O = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. Because this device has open-drain outputs, tplz and tpzl are the same as t PD. F. tpzl is measured at V M. G. tplz is measured at V OL + V. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: SN74LVC1G386

7 SN74LVC1G386 SCES439E APRIL 2003 REVISED DECEMBER 2013 Parameter Measurement Information From Output Under Test CL (see Note A) R L R L S1 V LOAD Open GND TEST S1 t PLH/tPHL Open t PLZ/tPZL t PHZ/tPZH V LOAD GND LOAD CIRCUIT INPUTS V I t r/tf V LOAD C L R L V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V 3 V 2 ns 2 ns 2.5 ns 2.5 ns VCC/2 /2 1.5 V / V 2 30 pf 30 pf 50 pf 50 pf 1 k V 0.15 V 0.3 V 0.3 V Timing Input V I 0 V t W V I t su t h Input VOLTAGE WAVEFORMS PULSE DURATION 0 V Data Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES V I 0 V Input V I 0 V Output Control V I 0 V Output t PLH t PHL V OH V OL Output Waveform 1 S1 at VLOAD (see Note B) t PZL V OL t PLZ + V V LOAD/2 V OL t PHL t PLH t PZH t PHZ Output V OH V OL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING V OH V V OH 0 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z O = 50. D. The outputs are measured one at a time, with one transition per measurement. E. tplz and tphz are the same as t dis. F. tpzl and tpzh are the same as t en. G. tplh and tphl are the same as t pd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms Copyright , Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: SN74LVC1G386

8 SN74LVC1G386 SCES439E APRIL 2003 REVISED DECEMBER 2013 REVISION HISTORY Changes from Revision D (July 2006) to Revision E Page Updated document to new TI data sheet format Updated Features Added ESD warning Updated operating temperature range Submit Documentation Feedback Copyright , Texas Instruments Incorporated Product Folder Links: SN74LVC1G386

9 PACKAGE OPTION ADDENDUM 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan 74LVC1G386DCKRG4 ACTIVE SC70 DCK Green (RoHS & no Sb/Br) SN74LVC1G386DBVR ACTIVE SOT-23 DBV Green (RoHS & no Sb/Br) SN74LVC1G386DCKR ACTIVE SC70 DCK Green (RoHS & no Sb/Br) SN74LVC1G386DRYR ACTIVE SON DRY Green (RoHS & no Sb/Br) SN74LVC1G386DSFR ACTIVE SON DSF Green (RoHS & no Sb/Br) SN74LVC1G386YZPR ACTIVE DSBGA YZP Green (RoHS & no Sb/Br) (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking (4/5) CU NIPDAU Level-1-260C-UNLIM -40 to 125 C8R CU NIPDAU Level-1-260C-UNLIM -40 to 125 CC6R CU NIPDAU Level-1-260C-UNLIM -40 to 125 C8R CU NIPDAU Level-1-260C-UNLIM -40 to 125 C8 CU NIPDAU Level-1-260C-UNLIM -40 to 125 C8 SNAGCU Level-1-260C-UNLIM -40 to 85 C8N Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

10 PACKAGE OPTION ADDENDUM 24-Aug-2018 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

11 PACKAGE MATERIALS INFORMATION 7-Oct-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant 74LVC1G386DCKRG4 SC70 DCK Q3 SN74LVC1G386DBVR SOT-23 DBV Q3 SN74LVC1G386DCKR SC70 DCK Q3 SN74LVC1G386DRYR SON DRY Q1 SN74LVC1G386DSFR SON DSF Q2 SN74LVC1G386YZPR DSBGA YZP Q1 Pack Materials-Page 1

12 PACKAGE MATERIALS INFORMATION 7-Oct-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74LVC1G386DCKRG4 SC70 DCK SN74LVC1G386DBVR SOT-23 DBV SN74LVC1G386DCKR SC70 DCK SN74LVC1G386DRYR SON DRY SN74LVC1G386DSFR SON DSF SN74LVC1G386YZPR DSBGA YZP Pack Materials-Page 2

17 MECHANICAL DATA DSF (S-PX2SON-N6) PLASTIC SMALL OUTLINE NO-LEAD A B PIN 1 INDEX AREA MAX C SEATING PLANE 0.05 C (0.11) TYP 3 4 2X 0.7 4X (0.1) PIN 1 ID 6X X C A B 0.05 C /F 10/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MO-287, variation X2AAF.

19 SCALE YZP0006 PACKAGE OUTLINE DSBGA mm max height DIE SIZE BALL GRID ARRAY B E A BALL A1 CORNER D 0.5 MAX C BALL TYP SEATING PLANE 0.05 C 0.5 TYP C B 0.5 TYP 1 TYP D: Max = mm, Min = mm E: Max = mm, Min = mm A X C A B /A 06/2014 NOTES: NanoFree Is a trademark of Texas Instruments. 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. NanoFree TM package configuration.

20 YZP0006 EXAMPLE BOARD LAYOUT DSBGA mm max height DIE SIZE BALL GRID ARRAY 6X ( 0.225) (0.5) TYP 1 2 A (0.5) TYP B C LAND PATTERN EXAMPLE SCALE:40X ( 0.225) 0.05 MAX METAL 0.05 MIN METAL UNDER MASK SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED ( 0.225) SOLDER MASK OPENING SOLDER MASK DETAILS NOT TO SCALE /A 06/2014 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (/lit/sbva017).

21 YZP0006 EXAMPLE STENCIL DESIGN DSBGA mm max height DIE SIZE BALL GRID ARRAY 6X ( 0.25) A (0.5) TYP 1 2 (R 0.05) TYP (0.5) TYP B METAL TYP C SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X /A 06/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

22 GENERIC PACKAGE VIEW DRY 6 USON mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details /G

23 SCALE DRY0006A PACKAGE OUTLINE USON mm max height PLASTIC SMALL OUTLINE - NO LEAD B A PIN 1 INDEX AREA MAX C SEATING PLANE 0.08 C 3X 0.6 (0.05) TYP (0.127) TYP 2X 1 4X NOTES: PIN 1 ID (OPTIONAL) 6 5X X C A B 0.05 C /A 01/ All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice.

24 EXAMPLE BOARD LAYOUT DRY0006A USON mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.35) 5X (0.3) 1 6 6X (0.2) 4X (0.5) 3 4 (R0.05) TYP (0.6) LAND PATTERN EXAMPLE 1:1 RATIO WITH PKG SOLDER PADS EXPOSED METAL SHOWN SCALE:40X 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND EXPOSED METAL EXPOSED METAL SOLDER MASK METAL OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS METAL UNDER SOLDER MASK SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING NOTES: (continued) 3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (/lit/slua271) /A 01/2018

25 DRY0006A EXAMPLE STENCIL DESIGN USON mm max height PLASTIC SMALL OUTLINE - NO LEAD (0.35) 5X (0.3) 1 6 6X (0.2) 4X (0.5) 3 4 (R0.05) TYP (0.6) SOLDER PASTE EXAMPLE BASED ON mm THICK STENCIL SCALE:40X /A 01/2018 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

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SINGLE INVERTER GATE Check for Samples: SN74LVC1G04

1 SN74LVC1G04 www.ti.com SCES214Z APRIL 1999 REVISED NOVEMBER 2012 SINGLE INVERTER GATE Check for Samples: SN74LVC1G04 1FEATURES 2 Available in the Texas Instruments NanoFree I off Supports Live Insertion,