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1 Controlled Baseline One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of 40 C to 25 C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking Typical f max = 60 MHz at V CC = 5 V, C L = 5 pf, T A = 25 C Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. description/ordering information SS550 DECEMBER 2003 Fanout (Over Temperature Range) Standard Outputs... 0 LSTTL Loads Bus Driver Outputs... 5 LSTTL Loads Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs V CC Voltage = 2 V to 6 V High Noise Immunity N IL or N IH = 30% of V CC, V CC = 5 V The CD74HC407 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low. The device can drive up to ten low-power Schottky equivalent loads. TA 40 C to 25 C ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER GND M OR PW PACKAGE (TOP VIEW) TOP-SIDE MARKING SOIC M Tape and reel CD74HC407QM96EP HC407E TSSOP PW Tape and reel CD74HC407QPWREP HC407E Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at V CC MR CP CE TC Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 75265

2 SS550 DECEMBER 2003 logic diagram (positive logic) FUNCTION TABLE INPUTS CP CE MR OUTPUT STATE L X L No change X H L No change X X H 0 = H, 9 = L L L Increments counter X L No change X L No change H L Increments counter NOTE: H = high voltage level, L = low voltage level, X = don t care, = transition from low to high level, = transition from high to low level If n < 5, TC = H, otherwise TC = L 3 0 CP 4 2 CE MR Decoded Decimal Out TC 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 SS550 DECEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC (see Note ) V to 7 V Input clamp current, I IK (V I < 0.5 V or V I > V CC V) ±20 ma Output clamp current, I OK (V O < 0.5 V or V O > V CC V) ±20 ma Source or sink current per output pin, I O (V O > 0.5 V or V O < V CC V) ±25 ma Continuous current through V CC or GND ±50 ma Package thermal impedance, θ JA (see Note 2): M package C/W PW package C/W Maximum junction temperature, T J C Lead temperature (during soldering): At distance /6 ± /32 inch (,59 ± 0,79 mm) from case for 0 s max C Storage temperature range, T stg C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. All voltages referenced to GND unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 5-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 2 6 V VCC = 2 V.5 VIH High-level input voltage VCC = 4.5 V 3.5 V VCC = 6 V 4.2 VCC = 2 V 0.5 VIL Low-level input voltage VCC = 4.5 V.35 V VCC = 6 V.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2 V tt Input transition (rise and fall) time VCC = 4.5 V ns VCC = 6 V TA Operating free-air temperature C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX DALLAS, TEXAS

4 SS550 DECEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL VI = VIH or VIL VI = VIH or VIL TEST CONDITIONS IO (ma) VCC TA = 25 C MIN MAX V.9.9 CMOS loads V TTL loads MIN MAX UNIT V V V V V CMOS loads V TTL loads V V V V II VI = VCC or GND 6 V ±0. ± µa ICC VI = VCC or GND 0 6 V 8 60 µa CIN = 50 pf 0 0 pf timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure ) PARAMETER VCC TA = 25 C MIN MAX 2 V 6 4 MIN MAX UNIT fmax Maximum clock frequency 4.5 V MHz 6 V tw tsu Pulse duration Setup time 2 V CP 4.5 V V V MR 4.5 V V V 75 0 CE to CP 4.5 V V V 5 5 MR inactive 4.5 V V V 0 0 th Hold time, CE to CP 4.5 V 0 0 ns 6 V 0 0 ns ns 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 SS550 DECEMBER 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure ) PARAMETER tpd FROM TO LOAD (INPUT) (OUTPUT) CAPACITANCE CP CE MR Decade out TC Decade out TC Decade out TC VCC TA = 25 C MIN TYP MAX MIN MAX UNIT 2 V = 50 pf 4.5 V V = 5 pf 5 V 9 2 V = 50 pf 4.5 V V = 5 pf 5 V 9 2 V = 50 pf 4.5 V V = 5 pf 5 V 2 2 V = 50 pf 4.5 V V = 5 pf 5 V 2 2 V = 50 pf 4.5 V V = 5 pf 5 V 9 2 V = 50 pf 4.5 V V = 5 pf 5 V 9 2 V 75 0 tt TC, Decade out = 50 pf 4.5 V 5 22 ns 6 V 3 9 fmax CP = 5 pf 5 V 60 MHz ns operating characteristics, V CC = 5 V, T A = 25 C, input t r, t f = 6 ns, C L = 5 pf PARAMETER TYP UNIT Cpd Power dissipation capacitance (see Note 4) 39 pf NOTE 4: Cpd is used to determine the dynamic power consumption per package. PD = (Cpd VCC 2 fi) + Σ( VCC 2 fo) fi = input frequency fo = output frequency = output load capacitance VCC = supply voltage POST OFFICE BOX DALLAS, TEXAS

6 SS550 DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point = 50 pf (see Note A) High-Level Pulse Low-Level Pulse 50% tw 50% 50% 50% VCC 0 V VCC 0 V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input 50% 50% VCC 0 V tplh tphl Reference Input Data Input 50% 0% 50% tsu th 90% 90% tr VCC 0 V VCC 50% 0% 0 V tf In-Phase Output Out-of-Phase Output 50% 0% tphl 90% 90% 90% tr 50% 50% 0% 0% tf tplh VOH 50% 0% VOL tf VOH 90% VOL tr VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tplh and tphl are the same as tpd. Figure. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 SS550 DECEMBER 2003 D P N P N Q C P N P N Q R Figure 2. Flip-Flop Detail CP MR CE TC Figure 3. Timing Diagram POST OFFICE BOX DALLAS, TEXAS

8 PACKAGE OPTION ADDENDUM 3-May-204 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan CD74HC407QM96EP ACTIVE SOIC D Green (RoHS & no Sb/Br) CD74HC407QPWREP ACTIVE TSSOP PW Green (RoHS & no Sb/Br) V62/ XE ACTIVE SOIC D Green (RoHS & no Sb/Br) V62/ YE ACTIVE TSSOP PW Green (RoHS & no Sb/Br) (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) Device Marking (4/5) CU NIPDAU Level--260C-UNLIM -40 to 25 HC407E CU NIPDAU Level--260C-UNLIM -40 to 25 HC407E CU NIPDAU Level--260C-UNLIM -40 to 25 HC407E CU NIPDAU Level--260C-UNLIM -40 to 25 HC407E Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page

9 PACKAGE OPTION ADDENDUM 3-May-204 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD74HC407-EP : Catalog: CD74HC407 Automotive: CD74HC407-Q Military: CD54HC407 NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Automotive - Q00 devices qualified for high-reliability automotive applications targeting zero defects Military - QML certified for Military and Defense Applications Addendum-Page 2

10 PACKAGE MATERIALS INFORMATION 4-Jul-202 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant CD74HC407QM96EP SOIC D Q CD74HC407QPWREP TSSOP PW Q Pack Materials-Page

11 PACKAGE MATERIALS INFORMATION 4-Jul-202 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC407QM96EP SOIC D CD74HC407QPWREP TSSOP PW Pack Materials-Page 2

14 SCALE PW006A PACKAGE OUTLINE TSSOP -.2 mm max height SMALL OUTLINE PACKAGE A 6.6 TYP 6.2 PIN INDEX AREA 6 4X 0.65 C SEATING PLANE 0. C 2X NOTE B NOTE 4 9 6X C A B.2 MAX SEE DETAIL A (0.5) TYP 0.25 GAGE PLANE A 20 DETAIL A TYPICAL /A 02/207 NOTES:. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y4.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.5 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-53.

15 5.000 PW006A EXAMPLE BOARD LAYOUT TSSOP -.2 mm max height SMALL OUTLINE PACKAGE 6X (.5) SYMM 6X (0.45) 6 (R0.05) TYP SYMM 4X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 0X SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS SOLDER MASK DEFINED /A 02/207 NOTES: (continued) 6. Publication IPC-735 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

16 PW006A EXAMPLE STENCIL DESIGN TSSOP -.2 mm max height SMALL OUTLINE PACKAGE 6X (0.45) 6X (.5) SYMM 6 (R0.05) TYP SYMM 4X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.25 mm THICK STENCIL SCALE: 0X /A 02/207 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

17 IMPORTANT NOTICE AND DISAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INUDING DATASHEETS), DESIGN RESOURCES (INUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES AS IS AND WITH ALL FAULTS, AND DISAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for () selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI s products are provided subject to TI s Terms of Sale ( or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI s provision of these resources does not expand or otherwise alter TI s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box , Dallas, Texas Copyright 208, Texas Instruments Incorporated

SN74LVC138A-Q1 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS708B SEPTEMBER 2003 REVISED FEBRUARY 2008

SN74LVC138A-Q1 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS708B SEPTEMBER 2003 REVISED FEBRUARY 2008 1 1FEATURES Qualified for Automotive Applications ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pf, R = 0) Operates From 2 V to 3.6 V Inputs Accept