description/ordering information

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1 Qualified for Automotive Applications ESD Protection Exceeds 1500 V Per MI-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pf, R = 0) Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 STT oads ow Power Consumption, 80-µA Max I CC Typical t pd = 13 ns ±4-mA Output Drive at 5 V ow Input Current of 1 µa Max Complementary Outputs Direct Overriding oad (Data) Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion SCS518A AUGUST 2003 REVISED APRI 2008 S/D CK E F G Q GND D OR PW PACKAGE (TOP VIEW) V CC CK IN D C B A SER Q description/ordering information The SN74C165 is an 8-bit parallel-load shift register that, when clocked, shift the data toward a serial (Q ) output. Parallel-in access to each stage is provided by eight individual direct data (A ) inputs that are enabled by a low level at the shift/load (S/D) input. The SN74C165 also features a clock-inhibit (CK IN) function and a complementary serial (Q ) output. Clocking is accomplished by a low-to-high transition of the clock (CK) input while S/D is held high and CK IN is held low. The functions of CK and CK IN are interchangeable. Since a low CK and a low-to-high transition of CK IN also accomplish clocking, CK IN should be changed to the high level only while CK is high. Parallel loading is inhibited when S/D is held high. While S/D is low, the parallel inputs to the register are enabled independently of the levels of the CK, CK IN, or serial (SER) inputs. TA ORDERING INFORMATION PACKAGE ORDERABE PART NUMBER TOP-SIDE MARKING SOIC D Tape and reel SN74C165QDRQ1 C165Q1 40 C to 125 C TSSOP PW Tape and reel SN74C165QPWRQ1 C165Q1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at Package drawings, thermal data, and symbolization are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2008, Texas Instruments Incorporated POST OFFICE BOX DAAS, TEXAS

2 SCS518A AUGUST 2003 REVISED APRI 2008 logic diagram (positive logic) FUNCTION TABE INPUTS S/D CK CK IN FUNCTION X X Parallel load X No change X No change Shift Shift Shift = content of each internal register shifts toward serial output Q. Data at SER is shifted into the first register. S/D 1 A B C D E F G CK IN CK Q SER 10 S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R 7 Q 2 POST OFFICE BOX DAAS, TEXAS 75265

3 SCS518A AUGUST 2003 REVISED APRI 2008 typical shift, load, and inhibit sequence CK CK IN SER S/D A B C Data Inputs D E F G Q Q oad Inhibit Serial Shift POST OFFICE BOX DAAS, TEXAS

4 SCS518A AUGUST 2003 REVISED APRI 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note 1) ±20 ma Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note 1) ±20 ma Continuous output current, I O (V O = 0 to V CC ) ±25 ma Continuous current through V CC or GND ±50 ma Package thermal impedance, θ JA (see Note 2): D package C/W PW package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD recommended operating conditions (see Note 3) MIN NOM MAX UNIT VCC Supply voltage V VCC = 2 V 1.5 VI igh-level input voltage VCC = 4.5 V 3.15 V VCC = 6 V 4.2 VCC = 2 V 0.5 VI ow-level input voltage VCC = 4.5 V 1.35 V VCC = 6 V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2 V 1000 t/ v Input transition rise/fall time VCC = 4.5 V 500 ns VCC = 6 V 400 TA Operating free-air temperature C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VImax = 0.5 V to VImin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CK inputs are not ensured while in the shift, count, or toggle operating modes. 4 POST OFFICE BOX DAAS, TEXAS 75265

5 SCS518A AUGUST 2003 REVISED APRI 2008 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC VO VO VI = VI or VI VI = VI or VI TA = 25 C MIN TYP MAX 2 V IO = 20 µa 4.5 V MIN MAX UNIT 6 V V IO = 4 ma 4.5 V IO = 5.2 ma 6 V V IO = 20 µa 4.5 V V V IO = 4 ma 4.5 V IO = 5.2 ma 6 V II VI = VCC or 0 6 V ±0.1 ±100 ±1000 na ICC VI = VCC or 0, IO = 0 6 V µa Ci 2 V to 6 V pf POST OFFICE BOX DAAS, TEXAS

6 SCS518A AUGUST 2003 REVISED APRI 2008 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC TA = 25 C MIN MAX MIN MAX UNIT 2 V fclock Clock frequency 4.5 V Mz 6 V tw Pulse duration 2 V S/D low 4.5 V V V CK high or low 4.5 V V V S/D high before CK 4.5 V V V SER before CK 4.5 V V V tsu Setup time CK IN low before CK 4.5 V ns th old time 6 V V CK IN high before CK 4.5 V V V Data before S/D 4.5 V V V 5 5 SER data after CK 4.5 V V V 5 5 PAR data after S/D 4.5 V V 5 5 ns ns 6 POST OFFICE BOX DAAS, TEXAS 75265

7 SCS518A AUGUST 2003 REVISED APRI 2008 switching characteristics over recommended operating free-air temperature range, C = 50 pf (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC TA = 25 C MIN TYP MAX 2 V MIN MAX UNIT fmax 4.5 V Mz 6 V V S/D Q or Q 4.5 V V V tpd CK Q or Q 4.5 V ns 6 V V Q or Q 4.5 V V V tt Any 4.5 V ns 6 V operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 75 pf POST OFFICE BOX DAAS, TEXAS

8 SCS518A AUGUST 2003 REVISED APRI 2008 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point C = 50 pf (see Note A) igh-evel Pulse ow-evel Pulse 50% tw 50% 50% 50% VCC 0 V VCC 0 V OAD CIRCUIT VOTAGE WAVEFORMS PUSE DURATIONS Input 50% 50% VCC 0 V tp tp Reference Input Data Input 50% 10% 50% tsu th 90% 90% tr VCC 0 V VCC 50% 10% 0 V tf In-Phase Output Out-of-Phase Output 50% 10% tp 90% 90% 90% tr 50% 50% 10% 10% tf tp VO 50% 10% VO tf VO 90% VO tr VOTAGE WAVEFORMS SETUP AND OD AND INPUT RISE AND FA TIMES VOTAGE WAVEFORMS PROPAGATION DEAY AND OUTPUT TRANSITION TIMES NOTES: A. C includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 Mz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tp and tp are the same as tpd. Figure 1. oad Circuit and Voltage Waveforms 8 POST OFFICE BOX DAAS, TEXAS 75265

9 PACKAGE OPTION ADDENDUM 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan SN74C165QDRQ1 ACTIVE SOIC D Green (RoS & no Sb/Br) SN74C165QPWRG4Q1 ACTIVE TSSOP PW Green (RoS & no Sb/Br) SN74C165QPWRQ1 ACTIVE TSSOP PW Green (RoS & no Sb/Br) (2) ead/ball Finish MS Peak Temp (3) Op Temp ( C) Top-Side Markings (4) CU NIPDAU evel-1-260c-unim -40 to 125 C165QQ1 CU NIPDAU evel-1-260c-unim -40 to 125 C165Q1 CU NIPDAU evel-1-260c-unim -40 to 125 C165Q1 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. IFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoS), Pb-Free (RoS Exempt), or Green (RoS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoS): TI's terms "ead-free" or "Pb-Free" mean semiconductor products that are compatible with the current RoS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoS Exempt): This component has a RoS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoS compatible) as defined above. Green (RoS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MS, Peak Temp. -- The Moisture Sensitivity evel rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

10 PACKAGE OPTION ADDENDUM 11-Apr-2013 OTER QUAIFIED VERSIONS OF SN74C165-Q1 : Catalog: SN74C165 Enhanced Product: SN74C165-EP Military: SN54C165 NOTE: Qualified Version Definitions: Catalog - TI's standard catalog product Enhanced Product - Supports Defense, Aerospace and Medical Applications Military - QM certified for Military and Defense Applications Addendum-Page 2

11 PACKAGE MATERIAS INFORMATION 14-Mar-2013 TAPE AND REE INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74C165QPWRG4Q1 TSSOP PW Q1 SN74C165QPWRQ1 TSSOP PW Q1 Pack Materials-Page 1

12 PACKAGE MATERIAS INFORMATION 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ ength (mm) Width (mm) eight (mm) SN74C165QPWRG4Q1 TSSOP PW SN74C165QPWRQ1 TSSOP PW Pack Materials-Page 2

15 SCAE PW0016A PACKAGE OUTINE TSSOP mm max height SMA OUTINE PACKAGE A TYP 6.2 PIN 1 INDEX AREA 16 14X 0.65 C SEATING PANE 0.1 C 2X NOTE B NOTE X C A B 1.2 MAX SEE DETAI A (0.15) TYP 0.25 GAGE PANE A 20 DETAI A TYPICA /A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO

16 PW0016A EXAMPE BOARD AYOUT TSSOP mm max height SMA OUTINE PACKAGE 16X (1.5) SYMM 1 16X (0.45) 16 (R0.05) TYP SYMM 14X (0.65) 8 9 (5.8) AND PATTERN EXAMPE EXPOSED META SOWN SCAE: 10X SODER MASK OPENING META META UNDER SODER MASK SODER MASK OPENING EXPOSED META EXPOSED META 0.05 MAX A AROUND 0.05 MIN A AROUND NON-SODER MASK DEFINED (PREFERRED) SODER MASK DETAIS SODER MASK DEFINED /A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

17 PW0016A EXAMPE STENCI DESIGN TSSOP mm max height SMA OUTINE PACKAGE 16X (0.45) 1 16X (1.5) SYMM 16 (R0.05) TYP SYMM 14X (0.65) 8 9 (5.8) SODER PASTE EXAMPE BASED ON mm TICK STENCI SCAE: 10X /A 02/2017 NOTES: (continued) 8. aser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

18 IMPORTANT NOTICE AND DISCAIMER TI PROVIDES TECNICA AND REIABIITY DATA (INCUDING DATASEETS), DESIGN RESOURCES (INCUDING REFERENCE DESIGNS), APPICATION OR OTER DESIGN ADVICE, WEB TOOS, SAFETY INFORMATION, AND OTER RESOURCES AS IS AND WIT A FAUTS, AND DISCAIMS A WARRANTIES, EXPRESS AND IMPIED, INCUDING WITOUT IMITATION ANY IMPIED WARRANTIES OF MERCANTABIITY, FITNESS FOR A PARTICUAR PURPOSE OR NON-INFRINGEMENT OF TIRD PARTY INTEECTUA PROPERTY RIGTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI s products are provided subject to TI s Terms of Sale ( or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI s provision of these resources does not expand or otherwise alter TI s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box , Dallas, Texas Copyright 2018, Texas Instruments Incorporated

SN74LVC138A-Q1 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS708B SEPTEMBER 2003 REVISED FEBRUARY 2008

SN74LVC138A-Q1 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS708B SEPTEMBER 2003 REVISED FEBRUARY 2008 1 1FEATURES Qualified for Automotive Applications ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pf, R = 0) Operates From 2 V to 3.6 V Inputs Accept