SN54HC165, SN74HC165 8-BIT PARALLEL-LOAD SHIFT REGISTERS

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1 N5465, N465 8-BIT PAAE-OAD IFT EGITE 16C DECEMBE 1982 EVIED MAY 199 Complementary Outputs Direct Overriding oad (Data) Inputs Gated Clock Inputs Parallel-to-erial Data Conversion Package Options Include Plastic mall-outline (D), Thin hrink mall-outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and tandard Plastic (N) and Ceramic (J) 300-mil DIPs description N J O W PACKAGE N D, N, O PW PACKAGE (TOP VIEW) /D CK E F G Q GND V CC CK IN D C B A E Q The 65 are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (Q ) output. Parallel-in access to each stage is provided by eight individual direct data (A ) inputs that are enabled by a low level at the shift/load (/D) input. The 65 also feature a clock-inhibit (CK IN) function and a complementary serial (Q ) output. Clocking is accomplished by a low-to-high transition of the clock (CK) input while /D is held high and CK IN is held low. The functions of CK and CK IN are interchangeable. ince a low CK and a low-to-high transition of CK IN also accomplish clocking, CK IN should be changed to the high level only while CK is high. Parallel loading is inhibited when /D is held high. While /D is low, the parallel inputs to the register are enabled independently of the levels of the CK, CK IN, or serial (E) inputs. The N5465 is characterized for operation over the full military temperature range of 55 C to 125 C. The N465 is characterized for operation from 40 C to 85 C. FUNCTION TABE INPUT FUNCTION /D CK CK IN X X Parallel load X No change X No change hift hift E F NC G hift = content of each internal register shifts toward serial output Q. Data at E is shifted into the first register. N FK PACKAGE (TOP VIEW) CK /D NC Q V CC E CK IN Q GND NC NC No internal connection D C NC B A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 199, Texas Instruments Incorporated POT OFFICE BOX DAA, TEXA

2 N5465, N465 8-BIT PAAE-OAD IFT EGITE 16C DECEMBE 1982 EVIED MAY 199 logic symbol /D CK IN CK G8 [OAD] 1 C2/ E A B C D E F G D 9 Q Q This symbol is in accordance with ANI/IEEE td and IEC Publication Pin numbers shown are for the D, J, N, PW, and W packages. logic diagram (positive logic) /D 1 A B C D E F G CK IN CK Q E 10 Q Pin numbers shown are for the D, J, N, PW, and W packages. 2 POT OFFICE BOX DAA, TEXA 5265

3 N5465, N465 8-BIT PAAE-OAD IFT EGITE 16C DECEMBE 1982 EVIED MAY 199 typical shift, load, and inhibit sequence CK CK IN E /D A B C Data Inputs D E F G Q Q oad Inhibit erial hift absolute maximum ratings over operating free-air temperature range upply voltage range, V CC V to V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note 1) ±20 ma Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note 1) ±20 ma Continuous output current, I O (V O = 0 to V CC ) ±25 ma Continuous current through V CC or GND ±50 ma Package thermal impedance, θ JA (see Note 2): D package C/W N package C/W PW package C/W torage temperature range, T stg C to 150 C tresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JED 51, except for through-hole packages, which use a trace length of zero. POT OFFICE BOX DAA, TEXA

4 N5465, N465 8-BIT PAAE-OAD IFT EGITE 16C DECEMBE 1982 EVIED MAY 199 recommended operating conditions N5465 N465 MIN NOM MAX MIN NOM MAX upply voltage V = 2 V VI igh-level input voltage = 4.5 V V = 6 V = 2 V VI ow-level input voltage = 4.5 V V = 6 V VI Input voltage 0 0 V VO Output voltage 0 0 V = 2 V tt t Input transition (rise and fall) time = 4.5 V ns = 6 V TA Operating free-air temperature C If this device is used in the threshold region (from VImax = 0.5 V to VImin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and = 2 V does not damage the device; however, functionally, the CK inputs are not ensured while in the shift, count, or toggle operating modes. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TET CONDITION VO VI I = VI or VI VO VI I = VI or VI TA = 25 C N5465 N465 MIN TYP MAX MIN MAX MIN MAX 2 V IO = 20 µa 4.5 V V V IO = 4 ma 4.5 V IO = 5.2 ma 6 V V IO = 20 µa 4.5 V V V IO = 4 ma 4.5 V IO = 5.2 ma 6 V II VI = or 0 6 V ±0.1 ±100 ±1000 ±1000 na ICC VI = or 0, IO = 0 6 V µa Ci 2 V to 6 V pf UNIT UNIT 4 POT OFFICE BOX DAA, TEXA 5265

5 N5465, N465 8-BIT PAAE-OAD IFT EGITE 16C DECEMBE 1982 EVIED MAY 199 timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25 C N5465 N465 MIN MAX MIN MAX MIN MAX 2 V fclock Clock frequency 4.5 V Mz 6 V tw Pulse duration 2 V /D low 4.5 V V V CK high or low 4.5 V V V /D high before CK 4.5 V V V E before CK 4.5 V V V tsu etup time CK IN low before CK 4.5 V ns 6 V th old time 2 V CK IN high before CK 4.5 V V V Data before /D 4.5 V V V E data after CK 4.5 V V V PA data after /D 4.5 V V UNIT ns ns POT OFFICE BOX DAA, TEXA

6 N5465, N465 8-BIT PAAE-OAD IFT EGITE 16C DECEMBE 1982 EVIED MAY 199 switching characteristics over recommended operating free-air temperature range, C = 50 pf (unless otherwise noted) (see Figure 1) PAAMETE FOM (INPUT) TO (OUTPUT) TA = 25 C N5465 N465 MIN TYP MAX MIN MAX MIN MAX 2 V fmax 4.5 V Mz 6 V V /D Q or Q 4.5 V V V tpd CK Q or Q 4.5 V ns 6 V V Q or Q 4.5 V V V ttt Any 4.5 V ns 6 V UNIT operating characteristics, T A = 25 C PAAMETE TET CONDITION TYP UNIT Cpd Power dissipation capacitance No load 5 pf 6 POT OFFICE BOX DAA, TEXA 5265

7 N5465, N465 8-BIT PAAE-OAD IFT EGITE PAAMETE MEAUEMENT INFOMATION 16C DECEMBE 1982 EVIED MAY 199 From Output Under Test Test Point C = 50 pf (see Note A) igh-evel Pulse ow-evel Pulse tw OAD CICUIT VOTAGE WAVEFOM PUE DUATION Input tp tp eference Input Data Input 10% tsu th 90% 90% tr 10% tf In-Phase Output Out-of-Phase Output 10% tp 90% 90% 90% tr 10% 10% tf tp VO 10% VO tf VO 90% VO tr VOTAGE WAVEFOM ETUP AND OD AND INPUT IE AND FA TIME VOTAGE WAVEFOM POPAGATION DEAY AND OUTPUT TANITION TIME NOTE: A. C includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: P 1 Mz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is. D. The outputs are measured one at a time with one input transition per measurement. E. tp and tp are the same as tpd. Figure 1. oad Circuit and Voltage Waveforms POT OFFICE BOX DAA, TEXA 5265

8 IMPOTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. pecific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ( Critical Applications ). TI EMICONDUCTO PODUCT AE NOT DEIGNED, INTENDED, AUTOIZED, O WAANTED TO BE UITABE FO UE IN IFE-UPPOT APPICATION, DEVICE O YTEM O OTE CITICA APPICATION. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local C sales office. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 1996, Texas Instruments Incorporated

SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR Contain Four Flip-Flops With Double-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline