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1 2-V to 6-V V CC Operation ( C190, 191) 4.5-V to 5.5-V V CC Operation ( CT191) Wide Operating Temperature Range of 55 C to 125 C Synchronous Counting and Asynchronous oading Two s for n-bit Cascading ook-ahead Carry for igh-speed Counting Balanced Propagation Delays and Transition Times Standard s Drive Up To 15 S-TT oads Significant Power Reduction Compared to S-TT ogic ICs CD54C190, 191; CD54CT191...F PACKAGE CD74C E, NS, OR PW PACKAGE CD74C191, CD74CT191...E OR M PACKAGE (TOP VIEW) B Q B Q A CTEN Q C Q D GND V CC A MAX/MIN C D description/ordering information The CD54/74C190 are asynchronously presettable BCD decade counters, whereas the CD54/74C191 and CD54/74CT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A D) is accomplished by a low asynchronous parallel load () input. Counting occurs when is high, count enable (CTEN) is low, and the down/up () input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. TA 55 C to 125 C ORDERING INFORMATION PACKAGE ORDERABE PART NUMBER CD74C190E TOP-SIDE MARKING CD74C190E PDIP E Tube of 25 CD74C191E CD74C191E CD74CT191E CD74CT191E Tube of 40 CD74C191M SOIC M Reel of 2500 CD74C191M96 C191M Reel of 250 CD74C191MT Tube of 40 CD74CT191M CT191M SOP NS Reel of 2000 CD74C190NSR C190M Tube of 90 CD74C190PW TSSOP PW Reel of 2000 CD74C190PWR J190 Reel of 250 CD74C190PWT CD54C190F3A CD54C190F3A CDIP F Tube of 25 CD54C191F3A CD54C191F3A CD54CT191F3A CD54CT191F3A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX DAAS, TEXAS

2 description/ordering information (continued) When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock () output, which normally is high, goes low, and remains low for the low-level portion of the clock pulse. These counters can be cascaded using (see Figure 2). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3). FUNCTION TABE INPUTS CTEN FUNCTION Count up Count down X X X Asynchronous preset X X No change or CTEN should be changed only when clock is high. X = Don t care ow-to-high clock transition 2 POST OFFICE BOX DAAS, TEXAS 75265

3 C190 logic diagram A B b 5 11 c d e f g h i DATA T Q Q FF0 DATA T Q Q FF1 j k l m n o 4 CTEN p 3 2 QA QB POST OFFICE BOX DAAS, TEXAS

4 C190 logic diagram (continued) C 10 D 9 b c 13 d e f g 12 MAX/MIN h i j DATA T Q Q FF2 DATA T Q Q FF3 k l m n o p 6 QC 7 QD 4 POST OFFICE BOX DAAS, TEXAS 75265

5 C191, CT191 logic diagram A B 15 1 C b c d e f g DATA T Q Q DATA T Q Q DATA T Q Q h i FF0 FF1 FF2 4 CTEN j k l M N 3 2 QA QB 6 QC POST OFFICE BOX DAAS, TEXAS

6 C191, CT191 logic diagram (continued) D 9 b c 13 d e f g 12 MAX/MIN h i DATA T Q Q FF3 j k l m n 7 QD 6 POST OFFICE BOX DAAS, TEXAS 75265

7 C190 and C191/CT191 flip-flop DATA n p C C p p p n Q n n p n p n CK Q T POST OFFICE BOX DAAS, TEXAS

8 typical load, count, and inhibit sequence for C190 The following sequence is illustrated below: 1. oad (preset) to BCD 7 2. Count up to 8, 9 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 9, 8, and 7 Parallel oad P0 Preset Data P1 P2 P3 Clock Down/Up Clock Enable Q0 Q1 Q2 Q3 Terminal Count Ripple Clock Count Up Inhibit Count Down oad 8 POST OFFICE BOX DAAS, TEXAS 75265

9 typical load, count, and inhibit sequence for C191 and CT191 The following sequence is illustrated below: 1. oad (preset) to binary Count up to 14, 15 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 15, 14, and 13 A Data s B C D CTEN QA Data s QB QC QD MAX/MIN Count Up Inhibit Count Down oad POST OFFICE BOX DAAS, TEXAS

10 Direction Control Enable CE CE CE CP TC CP TC CP TC Clock Figure 1. C190 Synchronous n-stage Counter With Parallel Gated Terminal Count Direction Control Enable RC RC CE CE CE CP CP CP RC Clock Figure 2. C191, CT191 Synchronous n-stage Counter With Parallel Gated Terminal Count Count Up NOTE: Illegal states in BCD counters corrected in one count Count Down NOTE: Illegal states in BCD counters corrected in one or two counts Figure 3. C190 State Diagram 10 POST OFFICE BOX DAAS, TEXAS 75265

11 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V clamp current, I IK (V I < 0 or V I > V CC ) (see Note 1) ±20 ma clamp current, I OK (V O < 0 or V O > V CC ) (see Note 1) ±20 ma Continuous output drain current per output, I O (V O = 0 to V CC ) ±35 ma Continuous output source or sink current per output, I O (V O = 0 to V CC ) ±25 ma Continuous current through V CC or GND ±50 ma Package thermal impedance, θ JA (see Note 2): E package C/W M package C/W NS package C/W PW package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD recommended operating conditions for C190 and C191 (see Note 3) TA = 25 C TA = 55 C TO 125 C TA = 40 C TO 85 C MIN MAX MIN MAX MIN MAX Supply voltage V = 2 V VI igh-level input voltage = 4.5 V V = 6 V = 2 V VI ow-level input voltage = 4.5 V V = 6 V VI voltage V VO voltage V = 2 V tt transition (rise and fall) time = 4.5 V ns = 6 V NOTE 3: All unused inputs of the device must be held at or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS s, literature number SCBA004. recommended operating conditions for CT191 (see Note 4) TA = 25 C TA = 55 C TO 125 C TA = 40 C TO 85 C MIN MAX MIN MAX MIN MAX Supply voltage V VI igh-level input voltage V VI ow-level input voltage V VI voltage V VO voltage V tt transition (rise and fall) time ns NOTE 4: All unused inputs of the device must be held at or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS s, literature number SCBA004. UNIT UNIT POST OFFICE BOX DAAS, TEXAS

12 C190, C191 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VO VO VI = VI or VI VI = VI or VI TA = 25 C TA = 55 C TO 125 C TA = 40 C TO 85 C MIN MAX MIN MAX MIN MAX 2 V IO = 20 µa 4.5 V UNIT 6 V V IO = 4 ma 4.5 V IO = 5.2 ma 6 V V IO = 20 µa 4.5 V V V IO = 4 ma 4.5 V IO = 5.2 ma 6 V II VI = or 0 6 V ±0.1 ±1 ±1 µa ICC VI = or 0, IO = 0 6 V µa Ci pf CT191 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VO VI = VI or VI VO VI = VI or VI IO = 20 µa IO = 4 ma IO = 20 µa IO = 4 ma 4.5 V 4.5 V TA = 25 C TA = 55 C TO 125 C TA = 40 C TO 85 C MIN TYP MAX MIN MAX MIN MAX II VI = to GND 5.5 V ±0.1 ±1 ±1 µa ICC VI = or 0, IO = V µa ICC One input at 2.1 V, Other inputs at 0 or UNIT 4.5 V to 5.5 V µa Ci pf Additional quiescent supply current per input pin, TT inputs high, 1 unit load CT INPUT ING TABE INPUTS UNIT S A-D CTEN 1.5 Unit load is ICC limit specified in electrical characteristics table, (e.g., 360 µa max at 25 C). V V 12 POST OFFICE BOX DAAS, TEXAS 75265

13 C190, C191 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) TA = 55 C TO 125 C TA = 40 C TO 85 C TA = 25 C UNIT MIN MAX MIN MAX MIN MAX 2 V fclock Clock frequency 4.5 V Mz 6 V V low 4.5 V tw Pulse duration 6 V V ns high or low 4.5 V V V Data before 4.5 V V V tsu Setup time CTEN before 4.5 V ns 6 V V before 4.5 V V V Data before 4.5 V V V th old time CTEN before 4.5 V ns 6 V V before 4.5 V V V trec Recovery time inactive before 4.5 V ns 6 V Applies to noncascaded operation only. With cascaded counters, clock-to-terminal count propagation delays, CTEN-to-clock setup times, and CTEN-to-clock hold times determine maximum clock frequency. For example, with these C devices: f max () 1 -to-max MIN propagation delay CTEN-to- setup time CTEN-to- hold time 1 18 Mz POST OFFICE BOX DAAS, TEXAS

14 C190, C191 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4) PARAMETER FROM TO (INPUT) (OUTPUT) CAPACITANCE TA = 25 C TA = 55 C TO 125 C TA = 40 C TO 85 C MIN TYP MAX MIN MAX MIN MAX 2 V fmax 4.5 V Mz 6 V tpd A, B, C, or D CTEN Q Q Q MAX/MIN MAX/MIN 2 V C = 50 pf 4.5 V V C = 15 pf 5 V 16 2 V C = 50 pf 4.5 V V C = 15 pf 5 V 14 2 V C = 50 pf 4.5 V V C = 15 pf 5 V 14 2 V C = 50 pf 4.5 V V C = 15 pf 5 V 10 2 V C = 50 pf 4.5 V V C = 15 pf 5 V 18 2 V C = 50 pf 4.5 V V C = 15 pf 5 V 12 2 V C = 50 pf 4.5 V V C = 15 pf 5 V 13 2 V C = 50 pf 4.5 V V C = 15 pf 5 V 10 2 V tt Any C = 50 pf 4.5 V ns 6 V UNIT ns 14 POST OFFICE BOX DAAS, TEXAS 75265

15 CT191 timing requirements over recommended operating free-air temperature range V CC = 4.5 V (unless otherwise noted) (see Figure 5) TA = 25 C TA = 55 C TO 125 C TA = 40 C TO 85 C MIN MAX MIN MAX MIN MAX fclock Clock frequency Mz tw Pulse duration low high or low Data before tsu Setup time CTEN before ns before Data before th old time CTEN before ns before trec Recovery time inactive before ns UNIT ns CT191 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5) PARAMETER FROM TO (INPUT) (OUTPUT) CAPACITANCE TA = 25 C TA = 55 C TO 125 C TA = 40 C TO 85 C MIN TYP MAX MIN MAX MIN MAX fmax 4.5 V Mz tpd A, B, C, or D CTEN Q Q Q MAX/MIN MAX/MIN C = 50 pf 4.5 V C = 15 pf 5 V 17 C = 50 pf 4.5 V C = 15 pf 5 V 16 C = 50 pf 4.5 V C = 15 pf 5 V 14 C = 50 pf 4.5 V C = 15 pf 5 V 11 C = 50 pf 4.5 V C = 15 pf 5 V 18 C = 50 pf 4.5 V C = 15 pf 5 V 12 C = 50 pf 4.5 V C = 15 pf 5 V 16 C = 50 pf 4.5 V C = 15 pf 5 V 11 tt Any C = 50 pf 4.5 V ns UNIT ns POST OFFICE BOX DAAS, TEXAS

16 operating characteristics, V CC = 5 V, T A = 25 C PARAMETER TYP UNIT C Cpd Power dissipation capacitance C pf CT POST OFFICE BOX DAAS, TEXAS 75265

17 PARAMETER MEASUREMENT INFORMATION C190, C191 PARAMETER S1 S2 From Under Test C (see Note A) Test Point R = 1 kω S1 S2 tpz ten tpz tpz tdis tpz tpd or tt Closed Closed Closed Closed CIRCUIT tw VOTAGE WAVEFORMS PUSE DURATION trec Reference Data 50% 10% tsu th 90% 90% tr 10% tf VOTAGE WAVEFORMS RECOVERY TIME VOTAGE WAVEFORMS SETUP AND OD AND INPUT RISE AND FA TIMES In-Phase Out-of-Phase tp 50% 10% tp 90% 90% 90% VO 10% VO tf VOTAGE WAVEFORMS PROPAGATION DEAY AND OUTPUT TRANSITION TIMES tr tp 50% 10% 10% tf tp 90% VO VO tr Control Waveform 1 (see Note B) Waveform 2 (see Note B) NOTES: A. C includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 Mz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tpz and tpz are the same as tdis. G. tpz and tpz are the same as ten.. tp and tp are the same as tpd. tpz tpz Figure 4. oad Circuit and Voltage Waveforms 10% 90% VOTAGE WAVEFORMS OUTPUT ENABE AND DISABE TIMES tpz tpz VO VO POST OFFICE BOX DAAS, TEXAS

18 PARAMETER MEASUREMENT INFORMATION CT191 PARAMETER S1 S2 From Under Test C (see Note A) Test Point R = 1 kω S1 S2 tpz ten tpz tpz tdis tpz tpd or tt Closed Closed Closed Closed CIRCUIT tw VOTAGE WAVEFORMS PUSE DURATION trec Reference Data 50% 10% tsu th 90% 90% tr 10% tf VOTAGE WAVEFORMS RECOVERY TIME VOTAGE WAVEFORMS SETUP AND OD AND INPUT RISE AND FA TIMES In-Phase Out-of-Phase tp 50% 10% tp 90% 90% 90% VO 10% VO tf VOTAGE WAVEFORMS PROPAGATION DEAY AND OUTPUT TRANSITION TIMES tr tp 50% 10% 10% tf tp 90% VO VO tr Control Waveform 1 (see Note B) Waveform 2 (see Note B) NOTES: A. C includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 Mz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tpz and tpz are the same as tdis. G. tpz and tpz are the same as ten.. tp and tp are the same as tpd. tpz tpz Figure 5. oad Circuit and Voltage Waveforms 10% 90% VOTAGE WAVEFORMS OUTPUT ENABE AND DISABE TIMES tpz tpz VO VO 18 POST OFFICE BOX DAAS, TEXAS 75265

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic