SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS
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1 Dependable Texas Instruments Quality and Reliability description These devices contain six independent inverters. SN404, SN4LS04, SN4S04, SN J PACKAGE SN4LS04, SN4S04... J OR W PACKAGE SN D, N, OR NS PACKAGE SN74LS04... D, DB, N, OR NS PACKAGE SN74S04... D OR N PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y V CC 6A 6Y A Y 4A 4Y SN W PACKAGE (TOP VIEW) 1A 2Y 2A V CC 3A 3Y 4A Y 6A 6Y Y A 4Y SN4LS04, SN4S04... FK PACKAGE (TOP VIEW) 2A 2Y 3A 1Y 1A Y 4Y 4A 6A 6Y A Y No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated On products compliant to MIL-PRF-383, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 6303 DALLAS, TEXAS 726 1
2 TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN7404N SN7404N PDIP N Tube SN74LS04N SN74LS04N Tube SN74S04N SN74S04N Tube SN7404D 7404 Tube SN74LS04D 0 C to 70 C SOIC D Tape and reel SN74LS04DR SOP NS Tube Tape and reel SN74S04D SN74S04DR LS04 S04 Tape and reel SN7404NSR SN7404 Tape and reel SN74LS04NSR 74LS04 SSOP DB Tape and reel SN74LS04DBR LS04 CDIP J Tube SN404J SN404J Tube SNJ404J SNJ404J Tube SN4LS04J SN4LS04J Tube SN4S04J SN4S04J Tube SNJ4LS04J SNJ4LS04J C to 12 C Tube SNJ4S04J SNJ4S04J Tube SNJ404W SNJ404W CFP W Tube SNJ4LS04W SNJ4LS04W Tube SNJ4S04W SNJ4S04W Tube SNJ4LS04FK SNJ4LS04FK LCCC FK Tube SNJ4S04FK SNJ4S04FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at FUTION TABLE (each inverter) INPUT A H L OUTPUT Y L H 2 POST OFFICE BOX 6303 DALLAS, TEXAS 726
3 logic diagram (positive logic) 1A 1Y 2A 2Y 3A 3Y 4A 4Y A Y 6A 6Y Y = A POST OFFICE BOX 6303 DALLAS, TEXAS 726 3
4 schematics (each gate) 04 4 kω 1.6 kω 130 Ω A Y 1 kω LS04 S04 20 kω 8 kω 120 Ω 2.8 kω 900 Ω 0 Ω A 4 kω Y A 3. kω Y 12 kω 3 kω 00 Ω 20 Ω 1. kω Resistor values shown are nominal. 4 POST OFFICE BOX 6303 DALLAS, TEXAS 726
5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note 1) V voltage, V I : 04, S V LS V Package thermal impedance, θ JA (see Note 2): D package C/W DB package C/W N package C/W NS package C/W Storage temperature range, T stg C to 10 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 1-7. recommended operating conditions SN404 SN7404 MIN NOM MAX MIN NOM MAX Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current ma IOL Low-level output current ma TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN404 SN7404 MIN TYP MAX MIN TYP MAX VIK = MIN, II = 12 ma V = MIN, VIL = 0.8 V, IOH = 0.4 ma V = MIN, VIH = 2 V, IOL = 16 ma V II = MAX, VI =. V 1 1 ma IIH = MAX, VI = 2.4 V µa IIL = MAX, VI = 0.4 V ma IOS V CC = MAX ma ICCH = MAX, VI = ma IC = MAX, VI = 4. V ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at = V, TA = 2 C. Not more than one output should be shorted at a time. switching characteristics, V CC = V, T A = 2 C (see Figure 1) FROM TO TEST CONDITIONS (INPUT) (OUTPUT) A Y = 400 Ω, =1pF SN404 SN7404 MIN TYP MAX ns POST OFFICE BOX 6303 DALLAS, TEXAS 726
6 recommended operating conditions SN4LS04 SN74LS04 MIN NOM MAX MIN NOM MAX Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current ma IOL Low-level output current 4 8 ma TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN4LS04 SN74LS04 MIN TYP MAX MIN TYP MAX VIK = MIN, II = 18 ma V = MIN, VIL = MAX, IOH = 0.4 ma V = MIN, VIH =2V IOL = 4 ma IOL = 8 ma II = MAX, VI = 7 V ma IIH = MAX, VI = 2.7 V µa IIL = MAX, VI = 0.4 V ma IOS V CC = MAX ma ICCH = MAX, VI = ma IC = MAX, VI = 4. V ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at = V, TA = 2 C. Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second. switching characteristics, V CC = V, T A = 2 C (see Figure 2) V FROM TO TEST CONDITIONS (INPUT) (OUTPUT) A Y =2kΩ kω, =1pF SN4LS04 SN74LS04 MIN TYP MAX ns 6 POST OFFICE BOX 6303 DALLAS, TEXAS 726
7 recommended operating conditions SN4S04 SN74S04 MIN NOM MAX MIN NOM MAX Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current 1 1 ma IOL Low-level output current ma TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN4S04 SN74S04 MIN TYP MAX MIN TYP MAX VIK = MIN, II = 18 ma V = MIN, VIL = 0.8 V, IOH = 1 ma V = MIN, VIH = 2 V, IOL = 20 ma V II = MAX, VI =. V 1 1 ma IIH = MAX, VI = 2.7 V 0 0 µa IIL = MAX, VI = 0. V 2 2 ma IOS V CC = MAX ma ICCH = MAX, VI = ma IC = MAX, VI = 4. V ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at = V, TA = 2 C. Not more than one output should be shorted at a time and the duration of the short-circuit should not exceed one second. switching characteristics, V CC = V, T A = 2 C (see Figure 1) FROM TO TEST CONDITIONS (INPUT) (OUTPUT) A Y = 280 Ω, =1pF SN4S04 SN74S04 MIN TYP MAX ns A Y = 280 Ω, =0pF 4. ns POST OFFICE BOX 6303 DALLAS, TEXAS 726 7
8 MEASUREMENT INFORMATION SERIES 4/74 AND 4S/74S DEVICES From Under (see Note B) From Under From Under 1 kω S1 (see Note B) S2 FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse tw PULSE DURATIONS Timing Data tsu 1. V th SETUP AND HOLD TIMES Control (low-level enabling) tpzl tplz In-Phase (see Note D) Out-of-Phase (see Note D) PROPAGATION DELAY TIMES Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) tpzh 1. V 1. V + 0. V tphz 1. V 0. V 1. V ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for,, tphz, and tplz; S1 is open and S2 is closed for tpzh; S1 is closed and S2 is open for tpzl. E. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 0 Ω; tr and tf 7 ns for Series 4/74 devices and tr and tf 2. ns for Series 4S/74S devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 6303 DALLAS, TEXAS 726
9 MEASUREMENT INFORMATION SERIES 4LS/74LS DEVICES SN404, SN4LS04, SN4S04, From Under (see Note B) From Under From Under kω S1 (see Note B) S2 FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS High-Level Pulse Low-Level Pulse tw PULSE DURATIONS Timing Data tsu 1. th SETUP AND HOLD TIMES Control (low-level enabling) tpzl tplz In-Phase (see Note D) Out-of-Phase (see Note D) PROPAGATION DELAY TIMES Waveform 1 (see Notes C and D) Waveform 2 (see Notes C and D) NOTES: A. includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for,, tphz, and tplz; S1 is open and S2 is closed for tpzh; S1 is closed and S2 is open for tpzl. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO 0 Ω, tr 1. ns, tf 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. tpzh 1. Figure 2. Load Circuits and Voltage Waveforms V tphz 1. V 0. V 1. V ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS POST OFFICE BOX 6303 DALLAS, TEXAS 726 9
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More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
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Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input exclusive-or
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SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B OCTOBER 1975 REVISED AUGUST 2002 Choice of Eight
More informationSN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B OCTOBER 1975 REVISED AUGUST 2002 Choice of Eight
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Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
More informationSN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
More informationORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
More informationSN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
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Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
More informationSN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B OCTOBER 1975 REVISED AUGUST 2002 Choice of Eight
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Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed
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Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators
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Noninverting Buffers With Open-Collector Outputs description These devices contain six independent noninverting buffers. They perform the Boolean function Y = A. The open-collector outputs require pullup
More informationPRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink
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SN78 Meets or Exceeds the Requirements of ANSI EIA/TIA--B and ITU Recommendation V. Single -V Supply Balanced-Line Operation TTL Compatible High Output Impedance in Power-Off Condition High-Current Active-Pullup
More informationdescription V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
More informationSN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
More informationSN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
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Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
More informationSN5406, SN5416, SN7406, SN7416 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Input Clamping Diodes Simplify System Design Open-Collector Drivers for Indicator Lamps and Relays Inputs Fully Compatible With Most
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Contain Four Flip-Flops With Double-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline
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Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has
More informationORDERING INFORMATION PACKAGE
Operates From.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max t pd of 4.8 ns at 3.3 V Typical V OLP (Output Ground Bounce) 2
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Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS SDLS049B DECEMBER 1983 REVISED FEBRUARY 2002
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SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SDAS113B APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers
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Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same-Frequency
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Operating Range 2-V to 5.5-V V CC Latch-Up Performance Exceeds 250 m Per JESD 17 description The SN74HC1G04 contai one inverter gate. The device performs the Boolean function =. DBV OR DCK PCKGES (TOP
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SNALS2C, SNAS2A, SNALS2C, SNAS2A SDAS2C JUL 9 REISED AUGUST 99 -State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Optio Include Plastic Small-Outline
More informationSN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B OCTOBER 1975 REVISED AUGUST 2002 Choice of Eight
More informationSN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B OCTOBER 1975 REVISED AUGUST 2002 Choice of Eight
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2-V to 5.5-V V CC Operation Typical V OLP (Output Ground Bounce) 2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage
More informationSN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B OCTOBER 1975 REVISED AUGUST 2002 Choice of Eight
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Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Optio Include Plastic Small-Outline
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Eight Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic
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-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,
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Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads Low Power Consumption, 80-µA Max I CC Typical t pd = 10 ns ±6-mA Output Drive at
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Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus Lines in Noisy
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Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in
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Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and
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3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce dc Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT)
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SN Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and RS-8 and ITU Recommendation V.. Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments -State s Common-Mode Voltage
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s Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process
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-A -Current Capability Per Driver Applications Include Half-H and Full-H Solenoid Drivers and Motor Drivers Designed for Positive-Supply Applications Wide Supply-Voltage Range of 4.5 V to 6 V TTL- and
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74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio
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3-State Outputs Interface Directly With System Bus Gated Output-Control LInes for Enabling or Disabling the Outputs Fully Independent Clock Virtually Eliminates Restrictions for Operating in One of Two
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Meets or Exceeds the Requirement of TIA/EIA-232-F and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Maximum Transition Time Through
More informationSN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B OCTOBER 1975 REVISED AUGUST 2002 Choice of Eight
More informationSN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS SDLS165B OCTOBER 1975 REVISED AUGUST 2002 Choice of Eight
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PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility
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Inputs Are TTL-oltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Operation From ery Slow Input Traitio Temperature-Compeated Threshold Levels High Noise Immunity Same Pinouts as AHCT00
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