P54FCT374/74fct374 NON-INVERTING OCTAL D FLIP-FLOP WITH 3-STATE OUTPUTS FEATURES DESCRIPTION

Transcription

1 FEATURES Function, Pinout and Drive Compatible with the FCT and F ogic FCT-A speed at 7.2ns max (MI) Output levels compatible with TT and CMOS Edge-rate control circuitry for significantly improved noise characteristics P54FCT374/74fct374 NON-INVERTING OCTA D FIP-FOP WIT 3-STATE OUTPUTS ESD protection exceeds 2000V Power-off disable feature Matched rise and fall times Fully compatible with TT input and output logic levels 32 ma sink current, 12 ma source current (MI) DESCRIPTION The P54/74FCT374 is a noninverting octal D flip-flop with a buffered common clock and buffered 3-state output control. When the output enable (OE) is low, the eight outputs are enabled. When the OE input is high, the outputs are in high-impedance state. Input data meeting the set-up and hold time requirements of the D inputs is transferred to the O outputs on the low-to-high transition of the clock input. Functional Block Diagram Pin ConfigurationS DIP (D2) CC (2) Document # OGIC115 REV OR Created April 2016

2 P54FCT374 / P74FCT374 - OCTA D FIP-FOP WIT 3-STATE OUTPUTS Maximum Ratings (1,2) Sym Parameter Value Unit T STG Storage Temperature -65 to +150 C T A Ambient Temperature Under Bias -65 to +135 C Potentional to Ground -0.5 to +7.0 V P T Power Dissipation 0.5 W I OUTPUT Current Applied to Output 120 ma Input Voltage -0.5 to +7.0 V V OUT Voltage Applied to Output -0.5 to +7.0 V RECOMMENDED OPERATING CONDITIONS Grade Ambient Temp GND Military -55 C to +125 C 0V 5.0V ± 10% Industrial -40 C to +85 C 0V 5.0V ± 5% CAPACITANCES ( = 5.0V, T A = 25 C, f = 1.0Mz) Sym Parameter Conditions Typ Unit C IN Input Capacitance = 0V 6 pf C OUT Output Capacitance V OUT = 0V 8 pf DC EECTRICA CARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Sym Parameter Test Conditions Min Max Unit V O V O igh evel Output Voltage ow evel Output Voltage (Min) V I = 2.0 V, V I = 0.8 V (Min) V I = 2.0 V, V I = 0.8 V I O = -300 µa 4.3 I O = -12 ma 2.4 I O = 300 µa 0.2 I O = 32 ma 0.5 V IK Input Clamp Voltage (Min), I IN = -18mA -1.2 V I I igh evel Input Current (Max), V 5.0 µa I I ow evel Input Current (Max), = GND -5.0 µa I O igh Impedence Output Current (Max), V 10 I O (Max), = GND -10 I OS Short Circuit Output Current (Max) -60 ma V V µa I CCQ Quiescent Power Supply Current (CMOS inputs) 0.2 V or V (Max) f i = f CP = 0 Mz 1.5 ma I CC Quiescent Power Supply Current (TT inputs) (Max) = 3.4 V 2.0 ma I CCD Dynamic Power Supply Current OE = GND Outputs open One bit toggling 50% duty cycle V or 0.2 V 0.4 ma/ Mz Notes: 1. Operation beyond the limits set forth in the above table may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. 2. Unused inputs must always be connected to an appropriate logic voltage level, preferably either or ground. Document # OGIC115 REV OR 3. Per TT driven input ( =3.4V); all other inputs at or GND. Page 2

3 P54FCT374 / P74FCT374 - OCTA D FIP-FOP WIT 3-STATE OUTPUTS Sym Parameter Test Conditions Min Max Unit I CCT Total Power Supply Current (Max) Outputs open, OE = GND 50% duty cycle f CP = 10 Mz f i = 5 Mz One bit toggling f i = 2.5 Mz Eight bits toggling V or 0.2 V = 3.4 V or = GND V or 0.2 V = 3.4 V or = GND 5.5 ma 6.0 ma 7.8 ma 16.8 ma C IN Input Capacitance T C = +25 C, = GND, F = 1 Mz 10 pf C OUT Output Capacitance T C = +25 C, = GND, F = 1 Mz 12 pf AC CARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Sym Parameter Condition 54/74FCT374 54/74FCT374A Ind Mil Ind Mil Min Max Min Max Min Max Min Max Unit t P t P Propagation Delay Clock to Output ns t P t P Output Enable Time OE to Output ns t SU t Set-up Time IG or OW Data to CP old Time IG or OW Data to CP C = 50pF R = 500Ω ns ns t W Clock Pulse Width IG or OW ns t P t P Output Disable Time OE to Output ns Test Open Drain Disable ow Enable ow All Other Tests Switch Closed Open Document # OGIC115 REV OR Page 3

4 P54FCT374 / P74FCT374 - OCTA D FIP-FOP WIT 3-STATE OUTPUTS SET-UP, OD AND REEASE TIMES PUSE WIDT PROPAGATION DEAY ENABE/DISABE TIMES PIN DESCRIPTION FUNCTION TABE Pin Names D N Description Data Inputs Function Inputs Outputs OE CP D N O N OE CP O N Output Enable Inputs (Active ow) Clock Pulse Input (Active Rising Edge) Data Outputs igh- oad Register X X = IG voltage level X = Don't Care = OW voltage level = IG impedance = OW-to-IG clock transition Document # OGIC115 REV OR Page 4

5 P54FCT374 / P74FCT374 - OCTA D FIP-FOP WIT 3-STATE OUTPUTS ORDERING INFORMATION Document # OGIC115 REV OR Page 5

6 P54FCT374 / P74FCT374 - OCTA D FIP-FOP WIT 3-STATE OUTPUTS Pkg # D2 # Pins 20 (300 mil) Symbol Min Max A b b c D E ea e BSC BSC Q S S α 0 15 SIDEBRAED DUA ININE PACKAGE Pkg # 2 # Pins 20 Symbol Min Max A A B D/E D1/E BSC D2/E BSC D3/E e BSC h REF j REF ND 5 NE 5 SQUARE EADESS CIP CARRIER Document # OGIC115 REV OR Page 6

7 P54FCT374 / P74FCT374 - OCTA D FIP-FOP WIT 3-STATE OUTPUTS REVISIONS DOCUMENT NUMBER DOCUMENT TITE OGIC115 P54FCT374 - OCTA D FIP-FOP WIT 3-STATE OUTPUTS REV ISSUE DATE ORIGINATOR DESCRIPTION OF CANGE OR Apr 2016 JDB New Data Sheet Document # OGIC115 REV OR Page 7