10 U.L. 5 (2.5) U.L. LOGIC SYMBOL LS90 LS92 LS VCC = PIN 5 GND = PIN 10 NC = PINS 4, 13 GND = PIN 10 NC = PINS 2, 3, 4, 13

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1 DECADE COUNTER; DIVIDE-BY-TWEVE COUNTER; -BIT BINARY COUNTER The SN/S, SN/S and SN/S are high-speed -bit ripple type counters partitioned into two sectio. Each counter has a divide-by-two section and either a divide-by-five (S), divide-by-six (S) or divide-by-eight (S) section which are triggered by a IG-to-OW traition on the clock inputs. Each section can be used separately or tied together (Q to ) to form B, bi-quinary, modulo-, or modulo- counters. All of the counters have a -input gated Master Reset (Clear), and the S also has a -input gated Master Set (Preset ). ow Power Coumption...Typically mw igh Rates...Typically Mz Choice of ing Modes... B, Bi-Quinary, Divide-by-Twelve, Binary Input Clamp Diodes imit igh Speed Termination Effects SN/S SN/S SN/S DECADE COUNTER; DIVIDE-BY-TWEVE COUNTER; -BIT BINARY COUNTER OW POWER SCOTTKY J SUFFI CERAMIC CASE - PIN NAMES OADING (Note a) IG OW Clock (Active OW going edge) Input to. U... U.. Section Clock (Active OW going edge) Input to. U... U.. Section (S), Section (S) Clock (Active OW going edge) Input to. U... U.. Section (S) MR, MR Master Reset (Clear) Inputs. U... U.. MS, MS Master Set (Preset-, S) Inputs. U... U.. Q Output from Section (Notes b & c) U.. (.) U.. Q, Q, Q Outputs from (S), (S), (S) Sectio (Note b) U.. (.) U.. NOTES: a. TT Unit oad (U..) = µa IG/. ma OW. b. The Output OW drive factor is. U.. for Military, () and U.. for commercial () b. Temperature Ranges. c. The Q Outputs are guaranteed to drive the full fan-out plus the input of the device. d. To iure proper operation the rise (t r ) and fall time (t f ) of the clock must be less than. N SUFFI PASTIC CASE - ORDERING INFORMATION SNSJ SNSN SNSD D SUFFI SOIC CASE A- Ceramic Plastic SOIC OGIC SYMBO S S S MS MR Q Q Q Q MR Q Q Q Q MR Q Q Q Q GND = PIN = PINS, GND = PIN = PINS,,, GND = PIN = PIN,,, FAST AND S TT DATA -

2 SN/S SN/S SN/S OGIC DIAGRAM MS MS MR MR J SD Q J SD Q S J SD Q R S D Q S Q Q Q Q Q = PIN NUMBERS GND = PIN CONNECTION DIAGRAM DIP (TOP VIEW) MR MR VCC MS MS Q Q GND Q Q = NO INTERNA CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. OGIC DIAGRAM MR MR S Q Q Q Q = PIN NUMBERS GND = PIN CONNECTION DIAGRAM DIP (TOP VIEW) VCC MR MR Q Q GND Q Q = NO INTERNA CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. OGIC DIAGRAM S CONNECTION DIAGRAM DIP (TOP VIEW) MR MR Q Q MR MR Q Q Q Q VCC GND Q Q = PIN NUMBERS GND = PIN = NO INTERNA CONNECTION NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-ine Package. FAST AND S TT DATA -

3 SN/S SN/S SN/S FUTIONA DESCRIPTION The S, S, and S are -bit ripple type Decade, Divide-By-Twelve, and Binary ers respectively. Each device coists of four master/slave flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five (S), divide-by-six (S), or divide-by-eight (S) section. Each section has a separate clock input which initiates state changes of the counter on the IG-to-OW clock traition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. The Q output of each device is designed and specified to drive the rated fan-out plus the input of the device. A gated AND asynchronous Master Reset (MR MR) is provided on all counters which overrides and clocks and resets (clears) all the flip-flops. A gated AND asynchronous Master Set (MS MS) is provided on the S which overrides the clocks and the MR inputs and sets the outputs to nine (). Since the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may be operated in various counting modes. S A. B Decade () er The input must be externally connected to the Q output. The input receives the incoming count and a B count sequence is produced. B. Symmetrical Bi-quinary Divide-By-Ten er The Q output must be externally connected to the input. The input count is then applied to the input and a divide-byten square wave is obtained at output Q. C. Divide-By-Two and Divide-By-Five er No external interconnectio are required. The first flip-flop is used as a binary element for the divide-by-two function ( as the input and Q as the output). The input is used to obtain binary divide-by-five operation at the Q output. S A. Modulo, Divide-By-Twelve er The input must be externally connected to the Q output. The input receives the incoming count and Q produces a symmetrical divide-by-twelve square wave output. B. Divide-By-Two and Divide-By-Six er No external interconnectio are required. The first flip-flop is used as a binary element for the divide-by-two function. The input is used to obtain divide-by-three operation at the Q and Q outputs and divide-by-six operation at the Q output. S A. -Bit Ripple er The output Q must be externally connected to input. The input count pulses are applied to input. Simultaneous divisio of,,, and are performed at the Q, Q, Q, and Q outputs as shown in the truth table. B. -Bit Ripple er The input count pulses are applied to input. Simultaneous frequency divisio of,, and are available at the Q, Q, and Q outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the -bit ripple-through counter. FAST AND S TT DATA -

4 SN/S SN/S SN/S S MODE SEECTION RESET/ SET INPUTS OUTPUTS MR MR MS MS Q Q Q Q = IG Voltage evel = OW Voltage evel = Don t Care S AND S MODE SEECTION RESET OUTPUTS INPUTS MR MR Q Q Q Q = IG Voltage evel = OW Voltage evel = Don t Care S B COUNT SEQUEE COUNT OUTPUT Q Q Q Q NOTE: Output Q is connected to Input for B count. COUNT S TRUT TABE OUTPUT Q Q Q Q NOTE: Output Q is connected to Input. COUNT S TRUT TABE OUTPUT Q Q Q Q NOTE: Output Q is connected to Input. FAST AND S TT DATA -

5 SN/S SN/S SN/S GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage V TA Operating Ambient Temperature Range C IO Output Current igh,. ma IO Output Current ow.. ma DC CARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) imits Symbol Parameter Min Typ Max Unit Test Conditio VI Input IG Voltage. V VI Input OW Voltage.. V Guaranteed Input IG Voltage for All Inputs Guaranteed Input OW Voltage for All Inputs VIK Input Clamp Diode Voltage.. V VCC = MIN, IIN = ma VO VO Output IG Voltage Output OW Voltage.. V VCC = MIN, IO = MA, VIN = VI.. V or VI per Truth Table,.. V IO =. ma VCC = VCC MIN, VIN =VI or VI.. V IO =. ma per Truth Table II II Input IG Current Input OW Current MS, MR (S, S) (S) µa VCC = MA, VIN =. V. ma VCC = MA, VIN =. V.... IOS Short Circuit Current (Note ) ma VCC = MA ICC Power Supply Current ma VCC = MA Note : Not more than one output should be shorted at a time, nor for more than second. ma VCC = MA, VIN =. V FAST AND S TT DATA -

6 SN/S SN/S SN/S AC CARACTERISTICS (TA = C, VCC =. V, C = pf) imits S S S Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Unit fma Input Clock Frequency Mz fma Input Clock Frequency Mz tp tp Propagation Delay, Input to Q Output tp tp Input to Q Output tp tp Input to Q Output tp tp Input to Q Output tp tp Input to Q Output tp MS Input to Q and Q Outputs tp MS Input to Q and Q Outputs tp MR Input to Any Output AC SETUP REQUIREMENTS (TA = C, VCC =. V) imits S S S Symbol Parameter Min Max Min Max Min Max Unit tw Pulse Width tw Pulse Width tw MS Pulse Width tw MR Pulse Width trec Recovery Time MR to RECOVERY TIME (t rec ) is defined as the minimum time required between the end of the reset pulse and the clock traition from IG-to-OW in order to recognize and trafer IG data to the Q outputs AC WAVEFORMS *. V. V. V tp tw tp Q. V. V Figure *The number of Clock Pulses required between the t P and t P measurements can be determined from the appropriate Truth Tables. MR & MS. V. V MS. V. V tw trec tw trec. V. V Q tp. V Q Q (S) tp. V Figure Figure FAST AND S TT DATA -