74F160A*, 74F161A, 74F162A*, 74F163A 4-bit binary counter INTEGRATED CIRCUITS. Product specification 1996 Jan 29 IC15 Data Handbook

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1 INTEGRATE CIRCUITS 4F16A*, 4F161A, 4F16A*, 4F163A 4-bit binary counter * iscontinued part. Please see the iscontinued Product List in Section 1, page Jan IC15 ata Handbook

2 4F161A, 4F163A FEATURES Synchronous counting and loading Two count enable inputs for n-bit cascading Positive edge-triggered clock Asynchronous Master Reset (4F161A) Synchronous Reset (4F163A) High speed synchronous expaion Typical count rate of 13MHz Industrial range ( 4 C to +85 C) available ESCRIPTION feature an internal carry look-ahead and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the Parallel Enable () input disables the counting action and causes the data at the 3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for are met). Preset takes place regardless of the levels at Count Enable (, ) inputs. A Low level at the Master Reset (MR) input sets all the four outputs of the flip-flops ( 3) in 4F161A to Low levels, regardless of the levels at,, and inputs (thus providing an asynchronous clear function). For the 4F163A, the clear function is synchronous. A Low level at the Synchronous Reset () input sets all four outputs of the flip-flops ( 3) to Low levels after the next positive-going traition on the clock () input (provided that the setup and hold time requirements for are met). This action occurs regardless of the levels at,, and inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAN gate (see Figure 1). The carry look-ahead simplifies serial cascading of the counters. Both Count Enable ( and ) inputs must be High to count. The input is fed forward to enable the output. The output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of. This pulse can be used to enable the next cascaded stage (see Figure ). The output is subjected to decoding spikes due to internal race conditio. Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters. TY 4F161A 4F163A TYPICAL f MAX 13MHz TYPICAL SUPPLY CURRENT (TOTAL) 46mA ORERING INFORMATION ESCRIPTION COMMERCIAL RANGE V CC = 5V ±1%, T amb = C to + C ORER COE INUSTRIAL RANGE V CC = 5V ±1%, T amb = 4 C to +85 C RAWING NUMBER 16-pin plastic IP N4F161AN, N4F163AN I4F161AN, I4F163AN SOT pin plastic SO N4F161A, N4F163A I4F161A, I4F163A SOT1-1 INPUT AN OUTPUT LOAING AN FAN-OUT TABLE PINS ESCRIPTION 4F (U.L.) HIGH/LOW LOA VALUE HIGH/LOW 3 ata inputs 1./1. µa/.6ma Count Enable Parallel input 1./1. µa/.6ma Count Enable Trickle input 1./. µa/1.ma Clock input (active rising edge) 1./1. µa/.6ma Parallel Enable input (active Low) 1./. µa/1.ma MR Asynchronous Master Reset input (active Low) for 4F161A Synchronous Reset input (active Low) for 4F163A 1./1. µa/.6ma 1./1. µa/.6ma Terminal count output 5/33 1.mA/mA 3 Flip-flop outputs 5/33 1.mA/mA NOTE: One (1.) FAST unit load is defined as: µa in the High state and.6ma in the Low state. 16 Jan

3 4F161A, 4F163A 4F161A PIN CONFIGURATION 4F163A PIN CONFIGURATION MR 1 16 V CC 1 16 V CC GN 8 GN 8 SF656 SF65 4F161A LOGIC SYMBOL 4F163A LOGIC SYMBOL MR V CC = Pin 16 GN = Pin SF658 V CC = Pin 16 GN = Pin SF65 4F161A LOGIC SYMBOL (IEEE/IEC) 4F163A LOGIC SYMBOL (IEEE/IEC) 1 1 CTR IV 16 R M1 G3 G4 C /1,3, CTR IV 16 R M1 G3 G4 C /1,3,4+ 3 1, , CT= CT=15 15 SF66 SF Jan 3

4 4F161A, 4F163A STATE IAGRAM APPLICATIONS +V CC F163A 14 6 CLOCK SF664 SF665 Figure 1. Maximum count modifying scheme Terminal count = 6 H H = Enable count or L L = isable count F163A 4F163A 4F163A 4F163A 4F163A SF666 Figure. Synchronous multistage counting scheme 4F161A MOE SELECT FUNCTION TABLE INPUTS OUTPUTS MR n n ORATING MOE L X X X X X L L Reset (clear) H X X l l L L H X X l h H (1) Parallel load H h h h X count (1) Count H X l X h X q n (1) H X X l h X q n L Hold (do nothing) 16 Jan 4

5 4F161A, 4F163A 4F163A MOE SELECT FUNCTION TABLE INPUTS OUTPUTS n n ORATING MOE l X X X X L L Reset (clear) h X X l l L L h X X l h H () h h h h X count () Count h X l X h X q n () h X X l h X q n L Parallel load Hold (do nothing) H = High voltage level h = High voltage level one setup prior to the Low-to-High clock traition L = Low voltage level l = Low voltage level one setup prior to the Low-to-High clock traition q n = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock traition X = on t care = Low-to-High clock traition (1) = The output is High when is High and the counter is at Terminal Count (HHHH for 4F161A) () = The output is High when is High and the counter is at Terminal Count (HHHH for 4F163A) 4F161A LOGIC IAGRAM MR R 14 4 R R R V CC = Pin 16 GN = Pin 8 SF66 16 Jan 5

6 4F161A, 4F163A 4F163A LOGIC IAGRAM V CC = Pin 16 GN = Pin 8 SF663 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage.5 to +. V V IN Input voltage.5 to +. V I IN Input current 3 to +5 ma V OUT Voltage applied to output in High output state.5 to V CC V I OUT Current applied to output in Low output state 4 ma T amb Operating free-air temperature range Commercial range to + C Industrial range 4 to +85 C T stg Storage temperature range 65 to +15 C 16 Jan 6

7 4F161A, 4F163A RECOMMENE ORATING CONITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX UNIT V CC Supply voltage V V IH High-level input voltage. V V IL Low-level input voltage.8 V I IK Input clamp current 18 ma I OH High-level output current 1 ma I OL Low-level output current ma T amb Operating free-air temperature range Commercial range + C Industrial range C C ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) LIMITS SYMBOL PARAMETER TEST CONITIONS 1 MIN TYP MAX UNIT V = MIN, V = MAX, V OH High-level output voltage CC IL V IH = MIN V = MIN, V = MAX, V OL Low-level output voltage CC IL V IH = MIN ±1%V CC.5 V I OH = MAX ±5%V CC. 3.4 V ±1%V CC.3.5 V I OL = MAX ±5%V CC.3.5 V V IK Input clamp voltage V CC = MIN, I I = I IK.3 1. V I I Input current at maximum input voltage V CC = MAX, V I =.V 1 µa I IH High-level input current V CC = MAX, V I =.V µa I IL Low-level input current, others V CC = MAX, V I =5V.5V 1. ma.6 ma I OS Short-circuit output current 3 V CC = MAX ma I CCH 4 55 ma I CC Supply current (total) V CC = MAX I CCL 4 65 ma NOTES: 1. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type.. All typical values are at V CC = 5V, T amb = 5 C. 3. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I OS tests should be performed last. 16 Jan

8 4F161A, 4F163A AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONITION T amb = +5 C V CC = +5.V C L = 5pF R L = 5Ω LIMITS T amb = C to + C V CC = +5.V ± 1% C L = 5pF R L = 5Ω T amb = 4 C to +85 C V CC = +5.V ± 1% C L = 5pF R L = 5Ω MIN TYP MAX MIN MAX MIN MAX f max Maximum clock frequency Waveform MHz t PLH t PLH t PLH t PLH Propagation delay to n ( = High) Propagation delay to n ( = Low) Propagation delay to Propagation delay to Propagation delay MR to n Propagation delay MR to AC SETUP REUIREMENTS SYMBOL t s (H) t s (L) t h (H) t h (L) t s (H) t s (L) t h (H) t h (L) t s (H) t s (L) t h (H) t h (L) t w (H) t w (L) t w (H) t w (L) t w (L) t REC PARAMETER Setup time, High or Low n to Hold time, High or Low n to Setup time, High or Low or to Hold time, High or Low or to Setup time, High or Low or to Hold time, High or Low or to pulse width (Load) High or Low pulse width (Count) High or Low MR pulse width Low Recovery time MR to Waveform 1 Waveform 1 Waveform 1 Waveform F161A Waveform F161A Waveform TEST CONITION Waveform 6 Waveform 6 Waveform 5 or 6 Waveform 5 or 6 Waveform 4 Waveform 4 Waveform 1 Waveform 1 T amb = +5 C V CC = +5.V C L = 5pF R L = 5Ω LIMITS T amb = C to + C V CC = +5.V ± 1% C L = 5pF R L = 5Ω. 8. T amb = 4 C to +85 C V CC = +5.V ± 1% C L = 5pF R L = 5Ω MIN TYP MIN MIN F161A Waveform F161A Waveform UNIT UNIT 16 Jan 8

9 4F161A, 4F163A AC WAVEFORMS For all waveforms, = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/f MAX t w (H) t w (L) t PLH t PLH n, SF66 Waveform 1. Propagation elay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency SF668 Waveform. Propagation elay, Input to Output t w (L) MR t REC t s (H) t h (H) t s (L) t h (L) n, SF66 Waveform 3. Master Reset Pulse Width, Master Reset to Output elay, and Master Reset to Recovery Time SF6 Waveform 4. and Reset Setup and Hold Times n t s t h t s (L) t h (L) t s (H) t h (H) t s (L) t h (L) t s (H) t h (H) SF61 Waveform 5. Synchronous Reset Setup and Hold Times Waveform 6. Parallel ata and Parallel Enable Setup and Hold Times SF6 16 Jan

10 4F161A, 4F163A TEST CIRCUIT AN WAVEFORMS PULSE GENERATOR V IN V CC.U.T. V OUT NEGATIVE PULSE % 1% t THL ( t f ) t w t TLH ( t r ) 1% % AMP (V) V R T C L R L Test Circuit for Totem-Pole Outputs POSITIVE PULSE 1% % t TLH ( t r ) t w t THL ( t f ) % 1% AMP (V) V EFINITIONS: R L = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 4F Input Pulse efinition INPUT PULSE REUIREMENTS amplitude rep. rate t w t TLH t THL 3.V 1.5V 1MHz SF6 16 Jan 1

11 4F16A*, 4F161A, 4F16A*, 4F163A IP16: plastic dual in-line package; 16 leads (3 mil) SOT38-4 * iscontinued part. Please see the iscontinued Product List in Section 1, page Jan 11

12 4F16A*, 4F161A, 4F16A*, 4F163A SO16: plastic small outline package; 16 leads; body width 3. mm SOT1-1 * iscontinued part. Please see the iscontinued Product List in Section 1, page Jan 1

13 4F16A*, 4F161A, 4F16A*, 4F163A NOTES * iscontinued part. Please see the iscontinued Product List in Section 1, page Jan 13

14 4-bit binary counter 4F16A*, 4F161A, 4F16A*, 4F163A ata sheet status ata sheet status Product status efinition [1] Objective specification Preliminary specification Product specification evelopment ualification Production This data sheet contai the design target or goal specificatio for product development. Specification may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contai final specificatio. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please coult the most recently issued datasheet before initiating or completing a design. efinitio Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditio above those given in the Characteristics sectio of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. isclaimers Life support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 34 Sunnyvale, California Telephone Copyright Philips Electronics North America Corporation 18 All rights reserved. Printed in U.S.A. print code ate of release: 1-8 ocument order number: * iscontinued part. Please see the iscontinued Product List in Section 1, page 1. yyyy mmm dd 14

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