The data sheets contained in this book were the most current available as of the date of publication, April 1998.

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2 Product Preview This heading on a data sheet indicates that the device is in the formative stages or in design (under development). The disclaimer at the bottom of the first page reads: This document contai information on a product under development. Motorola reserves the right to change or discontinue this product without notice. Advance Information This heading on a data sheet indicates that the device is in sampling, pre-production, or first production stages. The disclaimer at the bottom of the first page reads: This document contai information on a new product. Specificatio and information herein are subject to change without notice. Fully Released A fully released data sheet contai neither a classification heading nor a disclaimer at the bottom of the first page. This document contai information on a product in full production. Guaranteed limits will not be changed without written notice to your Motorola Semiconductor Sales Office. The data sheets contained in this book were the most current available as of the date of publication, April 199. A more current version of data sheets designated Product Preview or Advance Information may be available. Please visit our website for the most up to date information. Our website can be found at iterature can be accessed directly at bin/dlsrch

3 ery igh Speed CMOS Data Formerly Titled Advanced igh Speed CMOS Data Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation coequential or incidental damages. Typical parameters can and do vary in different applicatio. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any licee under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola, Inc. 199 Previous Edition July 199 as Advanced igh Speed CMOS Data All Rights Reserved Printed in U.S.A. i

4 Mfax is a trademark of Motorola, Inc. The brands or product names mentioned are trademarks or registered trademarks of their respective holders. ii

5 Table of Contents An Introduction to C Device Datasheets MC4C00 uad 2 Input NAND Gate MC4CT00A uad 2 Input NAND Gate (TT Compatible) MC4C02 uad 2 Input NOR Gate MC4C04 ex Inverter MC4CU04 ex Inverter (Unbuffered) MC4CT04A ex Inverter (TT Compatible) MC4C0 uad 2 Input AND Gate MC4C14 ex Schmitt Inverter MC4C32 uad 2 Input OR Gate MC4C4 Dual D Type Flip Flop MC4CT4A* Dual D Type Flip Flop (TT Compatible) MC4C6 uad 2 Input XOR Gate MC4C125 uad Bus Buffer MC4C126 uad Bus Buffer MC4C132 uad 2 Input NAND Schmitt Trigger MC4C13 3 to ine Decoder MC4CT13A 3 to ine Decoder (TT Compatible) MC4C139 Dual 2 to 4 Decoder/Demultiplexer MC4C15 uad 2 Channel Multiplexer MC4C240 Octal Bus Buffer/ine Driver MC4CT240A Octal Bus Buffer/ine Driver (TT Compatible) MC4C244 Octal Bus Buffer MC4CT244A Octal Bus Buffer (TT Compatible) MC4C245 Octal Bus Traceiver MC4CT245A Octal Bus Traceiver (TT Compatible) MC4C33 Octal D Type atch MC4CT33A Octal D Type atch (TT Compatible) MC4C34 Octal D Type Flip Flop MC4CT34A Octal D Type Flip Flop (TT Compatible) MC4C393 Dual 4 Bit Binary Ripple Counter MC4C540 Octal Bus Buffer MC4C541 Octal Bus Buffer MC4CT541A Octal Bus Buffer (TT Compatible) MC4C53 Octal D Type atch MC4CT53A Octal D Type atch (TT Compatible) MC4C54 Octal D Type Flip Flop MC4CT54A Octal D Type Flip Flop (TT Compatible) MC4C595 Bit Shift Register MC4C4051* Analog Multiplexer/Demultiplexer MC4C4052* Analog Multiplexer/Demultiplexer MC4C4053* Analog Multiplexer/Demultiplexer MC4C4066* uad Analog Switch/Multiplexer/Demultiplexer MC4C4316* uad Analog Switch/Mux/Demux w/ Separate Analog/Digital Power Supplies MC4C4351* Analog Multiplexer/Demultiplexer with Address atch Ordering Information Device Nomenclature Case Outlines ow to Reach Us Motorola Distributors and Worldwide Sales Offices * = Represents information that has not appeared in previous issues of this publication. Italics represent documents that have been revised since the last issue of this publication. iii

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7 SEMICONDUCTOR TECNICA DATA The C (ery igh Speed CMOS) logic family is designed for operation from = When operating at supply voltages less than the 5 range the C family features 5 tolerant inputs to aid 3 5 mixed system desig. ow power, low switching noise and fast switching speeds make this family perfect for low power, low cost portable applicatio. The CT products offer TT compatibility with CMOS low power performance. CT accepts TT level inputs and delivers full swing (4.5 to 5.5) outputs. The supply voltage range for CT is = The C/CT family pioneers a new cost/performance frontier. With typical speeds of less than 10, C/CT is the perfect logic family to take the low cost, low power desig well into the future. Excellent noise performance makes C/CT simple to use, with no need to sacrifice speed. C/CT can also improve system performance by drastically reducing static and dynamic power coumption which extends battery life for portable and handheld applicatio. Customers can also utilize C/CT to simplify system design in mixed voltage environments, as well as expedite development of low voltage systems. The 5 tolerant input capability helps simplify mixed system desig. The Motorola C/CT family is available in industry standard JEDEC SOIC, EIAJ SOIC, and the popular TSSOP packages. C/CT temperature specificatio range from 40 C to +5 C. The C/CT family is second sourced (specification compatible) by two other major semiconductor suppliers for ease of use and availability. Fastest propagation delays in their class C244 Tpd =.5 maximum compared to C244A Tpd = 23 max, and AC244 Tpd =.5 max; at 4.5, 40 C to +5 C operating temperature, 50pF loads C/CT also offers a light load 15pF specification for point to point applicatio Specified for 5 and 3 operation (C) AC and DC tables ease design for either 3 or 5 systems ery low noise guaranteed noise specificatio (olp, olv, ihd, ild) Inputs tolerate voltages from 0 to When the voltage on the input exceeds the supply voltage, no current path to the supply exists. Guaranteed not to exceed ±1µA. This feature facilitates 3 5 interface. A 3 to 5/5 to 3 level shifter can be easily designed by using a combination of C and CT product ow static ICC 20µA maximum for gates, 40µA maximum for MSI and octals. Typical static current is in the te of nanoamps Industry standard packaging SOIC, EIAJ SOIC, TSSOP packages. The TSSOP package is footprint compatible with competitio SSOP type I package. The TSSOP package is thinner than the SSOP type I package ma sink/source current at = 4.5; 4mA at = 3.0 (C) Good drive capability atch up immunity >±300mA Exceeds the industry standard ESD immunity > 2k BM; >200 MM Reliable operation. Industry standard performance Motorola pla to expand the C/CT family portfolio to around 0 popular functio. Customer input is always welcome. ery igh Speed CMOS ogic C Data D203 Rev 2 1 MOTOROA

8 An Introduction to C MOTOROA 2 ery igh Speed CMOS ogic C Data D203 Rev 2

9 SEMICONDUCTOR TECNICA DATA The MC4C00 is an advanced high speed CMOS 2 input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3. (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 32 FETs or Equivalent Gates OGIC DIAGRAM D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE A1 B1 A2 B2 A3 B Y1 6 Y2 Y = AB Y3 ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM FUNCTION TABE Inputs SOIC TSSOP SOIC EIAJ Output A4 B Y4 A B Y Pinout: 14 ead Packages (Top iew) B4 A4 Y4 B3 A3 Y A1 B1 Y1 A2 B2 Y2 6/9 Motorola, Inc RE 1

10 MC4C00 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I igh evel Input oltage to x x Î I ow evel Input Î oltage 3.0 to Î x 0.3 x 5.5 Î O igh evel Output in = I or I oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O ow evel Output in = I or I 2.0 Î oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 4 ery igh Speed CMOS ogic C Data D203 Rev 2

11 MC4C00 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Î Iin Input eakage Current in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa ICC uiescent Supply in = or 5.5 Î Current Î µa AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) Î TA = 40 to 5 C Î Symbol Test Conditio Min Typ Max Min Max Unit tp, Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A or B to Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Cin Input Capacitance pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 19 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 4 (per gate). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0, Measured in SOIC Package) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 TEST POINT A or B 50% tp tp DEICE UNDER TEST OUTPUT C* Y 50% * Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit INPUT Figure 3. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 5 MOTOROA

12 SEMICONDUCTOR TECNICA DATA The MC4CT00A is an advanced high speed CMOS 2 input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT00A input structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. The output structures also provide protection when = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: tpd = 5.0 (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 4 FETs or 12 Equivalent Gates D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION A1 B1 1 2 OGIC DIAGRAM 3 Y1 MC4CTXXAD MC4CTXXADT MC4CTXXAM SOIC TSSOP SOIC EIAJ A2 B2 A3 B3 A4 B Y2 Y = AB Y3 11 Y4 A FUNCTION TABE Inputs B Output Y Pinout: 14 ead Packages (Top iew) B4 A4 Y4 B3 A3 Y A1 B1 Y1 A2 B2 Y2 6/9 Motorola, Inc RE 0

13 MC4CT00A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage = to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage = 0 Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î ICC Maximum uiescent in = or 5.5 Supply Current µa ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = µa Current ery igh Speed CMOS ogic C Data D203 Rev 2 MOTOROA

14 MC4CT00A Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Propagation Delay, A or B to Y tp Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Input Capacitance pf Cin 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 1 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 4 (per gate). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0, Measured in SOIC Package) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. TEST POINT A or B 1.5 tp tp 3 DEICE UNDER TEST OUTPUT C* Y 1.5 O O * Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit MOTOROA ery igh Speed CMOS ogic C Data D203 Rev 2

15 SEMICONDUCTOR TECNICA DATA The MC4C02 is an advanced high speed CMOS 2 input NOR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3.6 (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 40 FETs or 10 Equivalent Gates A1 B1 A2 B2 A3 B3 A4 B OGIC DIAGRAM 1 Y1 4 Y2 10 Y3 13 Y4 Y = A + B D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM PIN ASSIGNMENT Y1 A1 B1 Y SOIC TSSOP SOIC EIAJ Y4 B4 A4 A Y3 FUNCTION TABE Inputs Output B2 6 9 B3 A3 A B Y 6/9 Motorola, Inc RE 1

16 MC4C02 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 10 ery igh Speed CMOS ogic C Data D203 Rev 2

17 MC4C02 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp Input A or B to Output Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Cin Maximum Input Capacitance Î pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 15 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 4 (per gate). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 TEST POINT A or B 50% tp tp DEICE UNDER TEST OUTPUT C* Y 50% * Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit INPUT Figure 3. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 11 MOTOROA

18 SEMICONDUCTOR TECNICA DATA The MC4C04 is an advanced high speed CMOS inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3. (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 36 FETs or 9 Equivalent Gates OGIC DIAGRAM D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE A1 A Y1 Y2 ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM SOIC TSSOP SOIC EIAJ A3 A Y3 Y4 Y = A FUNCTION TABE Inputs Outputs A Y A Y5 A Y6 Pinout: 14 ead Packages (Top iew) A6 Y6 A5 Y5 A4 Y A1 Y1 A2 Y2 A3 Y3 6/9 Motorola, Inc RE 1

19 MC4C04 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = 3.3 ± / = 5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î ery igh Speed CMOS ogic C Data D203 Rev 2 13 MOTOROA

20 MC4C04 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 0.1 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A or B to Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î Cin Maximum Input Capacitance Î pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Per Inverter) (Note 1.) 1 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 6 (per buffer). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 TEST POINT A 50% tp tp DEICE UNDER TEST OUTPUT C* Y 50% Figure 1. Switching Waveforms * Includes all probe and jig capacitance Figure 2. Test Circuit INPUT Figure 3. Input Equivalent Circuit MOTOROA 14 ery igh Speed CMOS ogic C Data D203 Rev 2

21 SEMICONDUCTOR TECNICA DATA The MC4CU04 is an advanced high speed CMOS unbuffered inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3.5 (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 10% (Min.) Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 12 FETs or 3 Equivalent Gates OGIC DIAGRAM D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE A1 A Y1 Y2 ORDERING INFORMATION MC4CUXXD MC4CUXXDT MC4CUXXM SOIC TSSOP SOIC EIAJ A3 A Y3 Y4 Y = A FUNCTION TABE Inputs Outputs A Y A Y5 A Y6 Pinout: 14 ead Packages (Top iew) A6 Y6 A5 Y5 A4 Y A1 Y1 A2 Y2 A3 Y3 6/9 Motorola, Inc RE 0

22 MC4CU04 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Î Min Typ Max Min Max Unit Î I Minimum igh evel Î Input oltage 3.0 to x 0.Î x 0.Î 5.5 Î I Maximum ow evel Input oltage to x x 0.2 O Minimum igh evel in =I Output oltage IO = 50µA in = IO = 4mA IO = ma Î O Maximum ow evel Î in = I Output oltage IO = 50µA in = I O = 4mA IO = ma MOTOROA 16 ery igh Speed CMOS ogic C Data D203 Rev 2

23 MC4CU04 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A or B to Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Cin Maximum Input Capacitance Î pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Per Inverter) (Note 1.) 9 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 6 (per buffer). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 4.0 ID Maximum ow evel Dynamic Input oltage 1.0 TEST POINT A 50% tp tp DEICE UNDER TEST OUTPUT C* Y 50% Figure 1. Switching Waveforms * Includes all probe and jig capacitance Figure 2. Test Circuit Parasitic Diode INPUT OUTPUT Parasitic Diode Figure 3. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 1 MOTOROA

24 SEMICONDUCTOR TECNICA DATA The MC4CT04A is an advanced high speed CMOS inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT04A input structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. The output structures also provide protection when = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: tpd = 4. (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 1.0 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 4 FETs or 12 Equivalent Gates D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXAD MC4CTXXADT MC4CTXXAM SOIC TSSOP SOIC EIAJ OGIC DIAGRAM A1 1 2 Y1 FUNCTION TABE A2 A3 A Y2 Y3 Y4 Y = A Inputs A Outputs Y A Y5 A Y6 Pinout: 14 ead Packages (Top iew) A6 Y6 A5 Y5 A4 Y A1 Y1 A2 Y2 A3 Y3 6/9 Motorola, Inc RE 0

25 MC4CT04A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage = to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage = 0 Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î ICC Maximum uiescent in = or 5.5 Supply Current µa ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = µa Current ery igh Speed CMOS ogic C Data D203 Rev 2 19 MOTOROA

26 MC4CT04A Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 5.0 ± 0.5 C = 15pF tp A to Y Î C = 50pF Maximum Input Capacitance pf Cin 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 11 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC/6 (per buffer). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. A 1.5 tp tp Y 1.5 Figure 1. Switching Waveforms 3 O O DEICE UNDER TEST OUTPUT TEST POINT * Includes all probe and jig capacitance Figure 2. Test Circuit C* MOTOROA 20 ery igh Speed CMOS ogic C Data D203 Rev 2

27 SEMICONDUCTOR TECNICA DATA The MC4C0 is an advanced high speed CMOS 2 input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 4.3 (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 24 FETs or 6 Equivalent Gates OGIC DIAGRAM D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE A1 B1 A2 B2 A3 B3 A4 B Y1 6 Y2 Y = AB Y3 11 Y4 ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM A FUNCTION TABE Inputs B SOIC TSSOP SOIC EIAJ Output Y Pinout: 14 ead Packages (Top iew) B4 A4 Y4 B3 A3 Y A1 B1 Y1 A2 B2 Y2 6/9 Motorola, Inc RE 1

28 MC4C0 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = 3.3 ± / = 5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 22 ery igh Speed CMOS ogic C Data D203 Rev 2

29 MC4C0 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0 ) TA = 40 to 5 C Symbol Î Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, Î = 3.3 ± 0.3 C = 15pF tp A or B to Y Î C = 50pF = 5.0 ± 0.5 C = 15pF C = 50pF Î Cin Maximum Input Capacitance C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 1 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 4 (per gate). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0 ) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage pf TEST POINT A or B tp 50% tp DEICE UNDER TEST OUTPUT C* Y 50% Figure 1. Switching Waveforms *Includes all probe and jig capacitance Figure 2. Test Circuit INPUT Figure 3. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 23 MOTOROA

30 SEMICONDUCTOR TECNICA DATA The MC4C14 is an advanced high speed CMOS Schmitt inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. Pin configuration and function are the same as the MC4C04, but the inputs have hysteresis and, with its Schmitt trigger function, the C14 can be used as a line receiver which will receive slow input signals. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 5.5 (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 60 FETs or 15 Equivalent Gates D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE OGIC DIAGRAM ORDERING INFORMATION A1 1 2 Y1 MC4CXXD MC4CXXDT MC4CXXM SOIC TSSOP SOIC EIAJ A2 3 4 Y2 A3 5 6 Y3 FUNCTION TABE Inputs Outputs A4 9 Y4 Y = A A Y A Y5 A Y6 Pinout: 14 ead Packages (Top iew) A6 Y6 A5 Y5 A4 Y A1 Y1 A2 Y2 A3 Y3 6/9 Motorola, Inc RE 1

31 MC4C14 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Î Min Typ Max Min Max Unit Î T+ Positive Threshold Î oltage (Figure 3) 4.5Î Î T Negative Threshold Î oltage (Figure 3) ysteresis oltage (Figure 3) Î O Minimum igh evel in = I or I Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma Î 3.0Î O Maximum ow evel in = I or I 2.0 Output oltage IO = 50µA in = I or I I O = 4mA IO = ma ery igh Speed CMOS ogic C Data D203 Rev 2 25 MOTOROA

32 MC4C14 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Typ Max Max Symbol Test Conditio Min Min Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current Î ± 0.1 ± 1.0 µa ICC Maximum uiescent in = or Supply Current Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A or B to Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î Cin Maximum Input Capacitance Î pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 21 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 6 (per buffer). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0 ) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 MOTOROA 26 ery igh Speed CMOS ogic C Data D203 Rev 2

33 MC4C14 TEST POINT A 50% tp tp DEICE UNDER TEST OUTPUT C* Y 50% * Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit T, TYPICA INPUT TRESOD OTAGE (OTS) (T+) (T ) , POWER SUPPY OTAGE (OTS) typ = (T+ typ) (T typ) typ Figure 3. Typical Input Threshold, T+, T versus Power Supply oltage (a) A Schmitt Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt Trigger Offers Maximum Noise Immunity in T+ T in T+ T O O out out O Figure 4. Typical Schmitt Trigger Applicatio O INPUT Figure 5. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 2 MOTOROA

34 SEMICONDUCTOR TECNICA DATA The MC4C32 is an advanced high speed CMOS 2 input OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3. (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 4 FETs or 12 Equivalent Gates OGIC DIAGRAM D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE A1 B Y1 ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM SOIC TSSOP SOIC EIAJ A2 B2 A3 B3 A4 B Y2 Y = A+B Y3 11 Y4 A FUNCTION TABE Inputs B Output Y Pinout: 14 ead Packages (Top iew) B4 A4 Y4 B3 A3 Y A1 B1 Y1 A2 B2 Y2 6/9 Motorola, Inc RE 1

35 MC4C32 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î ery igh Speed CMOS ogic C Data D203 Rev 2 29 MOTOROA

36 MC4C32 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A or B to Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Cin Maximum Input Capacitance Î pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 14 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 4 (per gate). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 TEST POINT A or B tp 50% tp DEICE UNDER TEST OUTPUT C* Y 50% Figure 1. Switching Waveforms *Includes all probe and jig capacitance Figure 2. Test Circuit INPUT Figure 3. Input Equivalent Circuit MOTOROA 30 ery igh Speed CMOS ogic C Data D203 Rev 2

37 SEMICONDUCTOR TECNICA DATA The MC4C4 is an advanced high speed CMOS D type flip flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The signal level applied to the D input is traferred to output during the positive going traition of the Clock pulse. Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input ow. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: fmax = 10Mz (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 12 FETs or 32 Equivalent Gates OGIC DIAGRAM D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM SOIC TSSOP SOIC EIAJ RD1 D1 CP RD2 D2 CP PIN ASSIGNMENT RD D RD2 SD1 4 SD2 10 CP1 SD D2 CP SD FUNCTION TABE 2 Inputs Outputs SD RD CP D X X X X X X * * X No Change X No Change X No Change * Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. 6/9 Motorola, Inc RE 1

38 MC4C4 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 32 ery igh Speed CMOS ogic C Data D203 Rev 2

39 MC4C4 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp CP to or Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp SD or RD to or C = 50pF Î Î = 5.0 ± 0.5 C = 15pF C = 50pF fmax Maximum Clock Frequency Î = 3.3 ± 0.3 C = 15pF 0 (50% Duty Cycle) Î C = 50pF Mz = 5.0 ± 0.5 C = 15pF Î C = 50pF Maximum Input Capacitance pf Cin 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 25 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 2 (per flip flop). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. TIMING REUIREMENTS (Input tr = tf = 3.0) Î Guaranteed imit Î TA = 40 to Symbol Î Î TA = 25 C Î 5 C Unit tw Minimum Pulse Width, CP Î 3.3 ± 0.3 Î 6.0 Î ± Î tw Minimum Pulse Width, RD or SD 3.3 ± ± 0.5 Î 5.0 Î 5.0 tsu Minimum Setup Time, D to CP Î 3.3 ± 0.3 Î 6.0 Î ± Î th Minimum old Time, D to CP 3.3 ± ± 0.5 Î 0.5 Î 0.5 trec Minimum Recovery Time, SD or RD to CP Î 3.3 ± Î 5.0 Î 5.0 ± ery igh Speed CMOS ogic C Data D203 Rev 2 33 MOTOROA

40 MC4C4 SWITCING WAEFORMS CP 50% tw 1/fmax SD or RD or tw 50% tp 50% tp 50% or tp tp or CP 50% trec 50% Figure 1. Figure 2. TEST POINT CP D 50% tsu AID th 50% DEICE UNDER TEST OUTPUT C* * Includes all probe and jig capacitance Figure 3. Figure 4. INPUT Figure 5. Input Equivalent Circuit MOTOROA 34 ery igh Speed CMOS ogic C Data D203 Rev 2

41 SEMICONDUCTOR TECNICA DATA The MC4CT4A is an advanced high speed CMOS D type flip flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The signal level applied to the D input is traferred to output during the positive going traition of the Clock pulse. Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input ow. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT4A input structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. The output structures also provide protection when =0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: fmax = 60Mz (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 12 FETs or 32 Equivalent Gates D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXAD MC4CTXXADT MC4CTXXAM PIN ASSIGNMENT SOIC TSSOP SOIC EIAJ RD1 1 OGIC DIAGRAM RD2 13 RD1 D1 CP RD2 D2 D1 CP D2 CP SD CP2 SD2 2 SD1 4 SD FUNCTION TABE Inputs Outputs SD RD CP D X X X X X X * * X No Change X No Change X No Change * Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. 3/9 Motorola, Inc RE 0

42 MC4CT4A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage = to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage = 0 Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î ICC Maximum uiescent in = or 5.5 Supply Current µa ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = µa Current MOTOROA 36 ery igh Speed CMOS ogic C Data D203 Rev 2

43 MC4CT4A Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 5.0 ± 0.5 C = 15pF tp CP to or Î C = 50pF tp, Maximum Propagation Delay, Î = 5.0 ± 0.5 C = 15pF tp SD or RD to or C = 50pF Î fmax Maximum Clock Frequency = 5.0 ± 0.5 C = 15pF Î Mz (50% Duty Cycle) C = 50pF Maximum Input Capacitance pf Cin 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 24 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 2 (per flip flop). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. TIMING REUIREMENTS (Input tr = tf = 3.0) Î Guaranteed imit TA = 40 to Symbol Î Î TA = 25 C Î 5 C Unit tw Minimum Pulse Width, CP Î 5.0 ± 0.5 Î 5.0 Î 5.0 tw Minimum Pulse Width, RD or SD 5.0 ± Î tsu Minimum Setup Time, D to CP 5.0 ± Î th Minimum old Time, D to CP 5.0 ± Î Minimum Recovery Time, SD or RD to CP 5.0 ± trec ery igh Speed CMOS ogic C Data D203 Rev 2 3 MOTOROA

44 MC4CT4A SWITCING WAEFORMS CP or 1.5 tw 1/fmax tp 1.5 tp 3 O O SD or RD or or CP tw 1.5 tp 1.5 tp 1.5 trec Figure 1. Figure 2. TEST POINT CP D 1.5 tsu AID th DEICE UNDER TEST OUTPUT C* * Includes all probe and jig capacitance Figure 3. Figure 4. INPUT Figure 5. Input Equivalent Circuit MOTOROA 3 ery igh Speed CMOS ogic C Data D203 Rev 2

45 SEMICONDUCTOR TECNICA DATA The MC4C6 is an advanced high speed CMOS 2 input Exclusive OR gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 4. (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 56 FETs or 14 Equivalent Gates A1 B1 A2 B2 A3 B3 A4 B OGIC DIAGRAM 3 Y1 6 Y2 Y = AB Y3 11 Y4 Pinout: 14 ead Packages (Top iew) D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM A FUNCTION TABE Inputs B SOIC TSSOP SOIC EIAJ Output Y B4 A4 Y4 B3 A3 Y A1 B1 Y1 A2 B2 Y2 6/9 Motorola, Inc RE 0

46 MC4C6 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ±0.3 Î =5.0 ± / 0 20 Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit Î I igh evel Input Î oltage to x x Î I ow evel Input Î oltage 3.0 to Î x 0.3 x O igh evel Output in = I or I oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O ow evel Output in = I or I Î oltage IO = 50µA in = I or I IO = 4mA 3.0 IO = ma Iin Input eakage Current in = 5.5 or 0 to 5.5Î ± 0.1 ± 1.0 µa ICC uiescent Supply in = or 5.5 Î Current Î Î µa MOTOROA 40 ery igh Speed CMOS ogic C Data D203 Rev 2

47 MC4C6 Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Propagation Delay, A or B to Y tp Î = 3.3 ± 0.3 C = 15pF Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î Cin Input Capacitance Î pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 1 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 4 (per gate). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0, Measured in SOIC Package) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 TEST POINT A or B 50% tp tp DEICE UNDER TEST OUTPUT C* Y 50% * Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit INPUT Figure 3. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 41 MOTOROA

48 SEMICONDUCTOR TECNICA DATA The MC4C125 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4C125 requires the 3 state control input (OE) to be set igh to place the output into the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3. (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 2 FETs or 1 Equivalent Gates OGIC DIAGRAM Active ow Output Enables A1 OE1 A2 OE2 A3 OE3 A4 OE Y1 Y2 Y3 Y4 D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM OE1 PIN ASSIGNMENT A1 Y1 OE2 A2 Y SOIC TSSOP SOIC EIAJ OE4 A4 Y4 OE3 A3 Y3 FUNCTION TABE C125 Inputs Output A OE Y X Z 6/9 Motorola, Inc RE 1

49 MC4C125 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î IOZ Maximum Three State in = I or I 5.5 Î ± 0.25 ± 2.50 µa eakage Current out = or ery igh Speed CMOS ogic C Data D203 Rev 2 43 MOTOROA

50 MC4C125 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tpî A to Y Î C = 50pF Î Î Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tpz, Î Maximum Output Enable TIme, Î = 3.3 ± 0.3 C = 15pF tpz OE to Y R = 1kΩ C = 50pF Î Î Î Î = 5.0 ± 0.5 C = 15pF R = 1kΩ C = 50pF tpz, Î Maximum Output Disable Time, Î = 3.3 ± 0.3 C = 50pF tpzî OE to Y Î R = 1kΩ Î = 5.0 ± 0.5 C = 50pF R = 1kΩ tos, Output to Output Skew = 3.3 ± 0.3 C = 50pF tos Î Î (Note 1.) Î Î Î = 5.0 ± 0.5 C = 50pF Î (Note 1.) Î C inî Maximum Input Capacitance pf CoutÎ Maximum Three State OutputÎ Capacitance (Output in igh 6 pf Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 14 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 4 (per buffer). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 MOTOROA 44 ery igh Speed CMOS ogic C Data D203 Rev 2

51 MC4C125 SWITCING WAEFORMS Y A OE 50% 50% tpz tpz tp tp Y 50% 50% tpz tpz Y 50% Figure 1. Figure 2. IG IMPEDANCE O 0.3 O +0.3 IG IMPEDANCE DEICE UNDER TEST OUTPUT TEST POINT C* DEICE UNDER TEST TEST POINT 1 kω OUTPUT C * CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance Figure 3. Test Circuit * Includes all probe and jig capacitance Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 45 MOTOROA

52 SEMICONDUCTOR TECNICA DATA The MC4C126 is a high speed CMOS quad bus buffer fabricated with silicon gate CMOS technology. It achieves noninverting high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4C126 requires the 3 state control input (OE) to be set ow to place the output into high impedance. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3. (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 2 FETs or 1 Equivalent Gates OGIC DIAGRAM Active igh Output Enables A1 OE Y1 D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM SOIC TSSOP SOIC EIAJ A2 OE2 A3 OE3 A4 OE Y2 Y3 Y4 PIN ASSIGNMENT OE A OE4 Y A4 OE Y4 A OE3 Y2 6 9 A3 Y3 FUNCTION TABE C126 Inputs Output A OE Y X Z 6/9 Motorola, Inc RE 0

53 MC4C126 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î IOZ Maximum Three State in = I or I 5.5 Î ± 0.25 ± 2.50 µa eakage Current out = or ery igh Speed CMOS ogic C Data D203 Rev 2 4 MOTOROA

54 MC4C126 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tpî A to Y Î C = 50pF Î Î Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tpz, Î Maximum Output Enable TIme, Î = 3.3 ± 0.3 C = 15pF tpz OE to Y R = 1kΩ C = 50pF Î Î Î Î = 5.0 ± 0.5 C = 15pF R = 1kΩ C = 50pF tpz, Î Maximum Output Disable Time, Î = 3.3 ± 0.3 C = 50pF tpzî OE to Y Î R = 1kΩ Î = 5.0 ± 0.5 C = 50pF R = 1kΩ tos, Output to Output Skew = 3.3 ± 0.3 C = 50pF tos Î Î (Note 1.) Î Î Î = 5.0 ± 0.5 C = 50pF Î (Note 1.) Î C inî Maximum Input Capacitance pf CoutÎ Maximum Three State OutputÎ Capacitance (Output in igh 6 pf Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 15 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 4 (per buffer). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 MOTOROA 4 ery igh Speed CMOS ogic C Data D203 Rev 2

55 MC4C126 SWITCING WAEFORMS Y A OE 50% 50% tpz tpz tp tp Y 50% 50% tpz tpz Y 50% Figure 1. Figure 2. IG IMPEDANCE O 0.3 O +0.3 IG IMPEDANCE DEICE UNDER TEST OUTPUT TEST POINT C* DEICE UNDER TEST TEST POINT 1 kω OUTPUT C * CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance Figure 3. Test Circuit * Includes all probe and jig capacitance Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 49 MOTOROA

56 SEMICONDUCTOR TECNICA DATA The MC4C132 is an advanced high speed CMOS Schmitt NAND trigger fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. Pin configuration and function are the same as the MC4C00, but the inputs have hysteresis and, with its Schmitt trigger function, the C132 can be used as a line receiver which will receive slow input signals. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 4.9 (Typ) at = 5 ow Power Dissipation: ICC = 2µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 2 FETs or 1 Equivalent Gates Pinout: 14 ead Packages (Top iew) B4 A4 Y4 B3 A3 Y D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXD MC4CXXDT MC4CXXM SOIC TSSOP SOIC EIAJ FUNCTION TABE A1 B1 Y1 A2 B2 Y2 Inputs Output A B Y OGIC DIAGRAM A1 B Y1 A3 B Y3 A2 B Y2 A4 B Y4 6/9 Motorola, Inc RE 0

57 MC4C132 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Î Min Typ Max Min Max Unit Î T+ Positive Threshold Î oltage (Figure 3) 4.5Î Î T Negative Threshold Î oltage (Figure 3) ysteresis oltage (Figure 3) Î O Minimum igh evel in = I or I Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma Î 3.0Î O Maximum ow evel in = I or I 2.0 Output oltage IO = 50µA in = I or I I O = 4mA IO = ma ery igh Speed CMOS ogic C Data D203 Rev 2 51 MOTOROA

58 MC4C132 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Typ Max Max Symbol Test Conditio Min Min Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current Î ± 0.1 ± 1.0 µa ICC Maximum uiescent in = or Supply Current Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A or B to Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î Cin Maximum Input Capacitance Î pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 16 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 4 (per gate). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0 ) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 MOTOROA 52 ery igh Speed CMOS ogic C Data D203 Rev 2

59 MC4C132 TEST POINT A 50% tp tp DEICE UNDER TEST OUTPUT C* Y 50% * Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit T, TYPICA INPUT TRESOD OTAGE (OTS) (T+) (T ) , POWER SUPPY OTAGE (OTS) typ = (T+ typ) (T typ) typ Figure 3. Typical Input Threshold, T+, T versus Power Supply oltage (a) A Schmitt Trigger Squares Up Inputs With Slow Rise and Fall Times (b) A Schmitt Trigger Offers Maximum Noise Immunity in T+ T in T+ T O O out out O Figure 4. Typical Schmitt Trigger Applicatio O INPUT Figure 5. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 53 MOTOROA

60 SEMICONDUCTOR TECNICA DATA The MC4C13 is an advanced high speed CMOS 3 to decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. When the device is enabled, three Binary Select inputs (A0 A2) determine which one of the outputs (Y0 Y) will go ow. When enable input E3 is held ow or either E2 or E1 is held igh, decoding function is inhibited and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade connection and for use as an address decoder for memory systems. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 5. (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 122 FETs or 30.5 Equivalent Gates FUNCTION TABE Inputs Outputs E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y X X X X X X X X X X X X X X X = high level (steady state); = low level (steady state); X = don t care D SUFFIX 16 EAD SOIC PACKAGE CASE 51B 05 DT SUFFIX 16 EAD TSSOP PACKAGE CASE 94F 01 M SUFFIX 16 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXD MC4CXXXDT MC4CXXXM PIN ASSIGNMENT A0 A1 A2 E1 E2 E3 Y SOIC TSSOP SOIC EIAJ Y0 Y1 Y2 Y3 Y4 Y5 Y6 SEECT INPUTS ENABE INPUTS A0 A1 A2 E3 E2 E Y0 Y1 Y2 Y3 Y4 Y5 9 Y6 Y OGIC DIAGRAM ACTIE OW OUTPUTS 6/9 Motorola, Inc RE 1

61 MC4C13 EXPANDED OGIC DIAGRAM 15 Y0 14 Y1 A Y2 A Y3 A Y4 E2 E Y5 Y6 Y E3 6 ery igh Speed CMOS ogic C Data D203 Rev 2 55 MOTOROA

62 MC4C13 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µ in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 56 ery igh Speed CMOS ogic C Data D203 Rev 2

63 MC4C13 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A to Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp E3 to Y C = 50pF Î Î = 5.0 ± 0.5 C = 15pF C = 50pF tp, Maximum Propagation Delay, Î = 3.3 ± 0.3 C = 15pF tp E2 or E1 to Y Î C = 50pF = 5.0 ± 0.5 C = 15pF C = 50pF Maximum Input Capacitance pf Cin 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 34 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC. CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. ery igh Speed CMOS ogic C Data D203 Rev 2 5 MOTOROA

64 MC4C13 SWITCING WAEFORMS A tp 50% AID AID tp E3 tp 50% tp Y 50% Y 50% Figure 1. Figure 2. TEST POINT E2 or E1 50% tp tp DEICE UNDER TEST OUTPUT C* Y 50% Figure 3. * Includes all probe and jig capacitance Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit MOTOROA 5 ery igh Speed CMOS ogic C Data D203 Rev 2

65 SEMICONDUCTOR TECNICA DATA The MC4CT13A is an advanced high speed CMOS 3 to decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. When the device is enabled, three Binary Select inputs (A0 A2) determine which one of the outputs (Y0 Y) will go ow. When enable input E3 is held ow or either E2 or E1 is held igh, decoding function is inhibited and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade connection and for use as an address decoder for memory systems. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because they have full 5 CMOS level output swings. The CT13A input structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. The output structures also provide protection when = 0. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: tpd =.6 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 122 FETs or 30.5 Equivalent Gates D SUFFIX 16 EAD SOIC PACKAGE CASE 51B 05 DT SUFFIX 16 EAD TSSOP PACKAGE CASE 94F 01 M SUFFIX 16 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXXAD MC4CTXXXADT MC4CTXXXAM PIN ASSIGNMENT SOIC TSSOP SOIC EIAJ A A Y0 A Y1 E Y2 E Y3 E Y4 Y 10 Y5 9 Y6 FUNCTION TABE Inputs Outputs E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y X X X X X X X X X X X X X X X SEECT INPUTS ENABE INPUTS A0 A1 A2 E3 E2 E Y0 Y1 Y2 Y3 Y4 Y5 9 Y6 Y OGIC DIAGRAM ACTIE OW OUTPUTS = high level (steady state); = low level (steady state); X = don t care 6/9 Motorola, Inc RE 0

66 MC4CT13A EXPANDED OGIC DIAGRAM 15 Y0 14 Y1 A Y2 A Y3 A Y4 E2 E Y5 Y6 Y E3 6 MOTOROA 60 ery igh Speed CMOS ogic C Data D203 Rev 2

67 MC4CT13A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage = to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage = 0 Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î ICC Maximum uiescent in = or 5.5 Supply Current µa ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = µa Current ery igh Speed CMOS ogic C Data D203 Rev 2 61 MOTOROA

68 MC4CT13A Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 5.0 ± 0.5 C = 15pF tp A to Y Î C = 50pF tp, Maximum Propagation Delay, Î = 5.0 ± 0.5 C = 15pF tp E3 to Y C = 50pF Î tp, Maximum Propagation Delay, = 5.0 ± 0.5 C = 15pF tp E2 or E1 to Y C = 50pF Maximum Input Capacitance pf Cin 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 49 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC. CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. SWITCING WAEFORMS A Y tp AID AID tp 3 E3 1.5 tp O Y 1.5 O tp 3 O O Figure 1. Figure 2. E2 or E1 Y 1.5 tp 1.5 tp 3 O O Figure 3. TEST CIRCUIT TEST POINT DEICE UNDER TEST OUTPUT C* * Includes all probe and jig capacitance Figure 4. Test Circuit MOTOROA 62 ery igh Speed CMOS ogic C Data D203 Rev 2

69 SEMICONDUCTOR TECNICA DATA The MC4C139 is an advanced high speed CMOS 2 to 4 decoder/ demultiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. When the device is enabled (E = low), it can be used for gating or as a data input for demultiplexing operatio. When the enable input is held high, all four outputs are fixed high, independent of other inputs. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 5.0 (Typ) at = 5 ow Power Dissipation: ICC = 4µΑ (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 100 FETs or 25 Equivalent Gates OGIC DIAGRAM D SUFFIX 16 EAD SOIC PACKAGE CASE 51B 05 DT SUFFIX 16 EAD TSSOP PACKAGE CASE 94F 01 M SUFFIX 16 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXD MC4CXXXDT MC4CXXXM SOIC TSSOP SOIC EIAJ ADDRESS INPUTS A0a A1a Ea Y0a Y1a Y2a Y3a ACTIE OW OUTPUTS PIN ASSIGNMENT Ea A0a A1a Y0a Y1a Eb A0b A1b Y0b Y2a 6 11 Y1b ADDRESS A0b 14 INPUTS A1b Y0b Y1b Y2b Y3b ACTIE OW OUTPUTS Y3a 10 FUNCTION TABE 9 Y2b Y3b Eb 15 Inputs Outputs E A1 A0 Y0 Y1 Y2 Y3 X X 6/9 Motorola, Inc RE 0

70 MC4C139 EXPANDED OGIC DIAGRAM (1/2 OF DEICE) En Y0 A0 Y1 Y2 A1 Y3 INPUT Figure 1. Input Equivalent Circuit MOTOROA 64 ery igh Speed CMOS ogic C Data D203 Rev 2

71 MC4C139 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = 3.3 ± / (Figure 1) =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î ery igh Speed CMOS ogic C Data D203 Rev 2 65 MOTOROA

72 MC4C139 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A to Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp E to Y C = 50pF Î Î = 5.0 ± 0.5 C = 15pF C = 50pF Maximum Input Capacitance pf Cin 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 26 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC/2 (per decoder). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. SWITCING WAEFORMS A tp 50% tp Y 50% Figure 2. TEST POINT E 50% tp tp DEICE UNDER TEST OUTPUT C* Y 50% Figure 3. * Includes all probe and jig capacitance Figure 4. Test Circuit MOTOROA 66 ery igh Speed CMOS ogic C Data D203 Rev 2

73 SEMICONDUCTOR TECNICA DATA The MC4C15 is an advanced high speed CMOS quad 2 channel multiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. It coists of four 2 input digital multiplexers with common select (S) and enable (E) inputs. When E is held igh, selection of data is inhibited and all the outputs go ow. The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 4.1 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 2 FETs or 20 Equivalent Gates NIBBE INPUTS E S A0 B0 A1 B1 A2 B2 A3 B EXPANDED OGIC DIAGRAM Y0 Y1 Y2 Y3 DATA OUTPUTS D SUFFIX 16 EAD SOIC PACKAGE CASE 51B 05 DT SUFFIX 16 EAD TSSOP PACKAGE CASE 94F 01 M SUFFIX 16 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXD MC4CXXXDT MC4CXXXM PIN ASSIGNMENT S A0 B0 Y0 A1 B1 Y SOIC TSSOP SOIC EIAJ E A3 B3 Y3 A2 B2 Y2 FUNCTION TABE Inputs Outputs E S Y0 Y3 X A0 A3 B0 B3 A0 A3, B0 B3 = the levels of the respective Data Word Inputs. 6/9 Motorola, Inc RE 1

74 MC4C15 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = / = Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 6 ery igh Speed CMOS ogic C Data D203 Rev 2

75 MC4C15 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A or B to Y Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp S to Y C = 50pF Î Î = 5.0 ± 0.5 C = 15pF C = 50pF tp, Maximum Propagation Delay, Î = 3.3 ± 0.3 C = 15pF tp E to Y Î C = 50pF = 5.0 ± 0.5 C = 15pF C = 50pF Maximum Input Capacitance pf Cin 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) 20 pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC. CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 ery igh Speed CMOS ogic C Data D203 Rev 2 69 MOTOROA

76 MC4C15 SWITCING WAEFORMS A, B or S tp 50% tp E tp 50% tp Y 50% Y 50% Figure 1. Switching Waveform Figure 2. Inverting Switching TEST POINT DEICE UNDER TEST OUTPUT C* * Includes all probe and jig capacitance Figure 3. Test Circuit INPUT Figure 4. Input Equivalent Circuit MOTOROA 0 ery igh Speed CMOS ogic C Data D203 Rev 2

77 SEMICONDUCTOR TECNICA DATA The MC4C240 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4C240 is an inverting 3 state buffer, and has two active low output enables. This device is designed to drive bus lines or buffer memory address registers. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3.6 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0.9 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 120 FETs or 30 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION A1 OGIC DIAGRAM 2 1 YA1 MC4CXXXDW MC4CXXXDT MC4CXXXM SOIC WIDE TSSOP SOIC EIAJ A YA2 PIN ASSIGNMENT A YA3 OEA 1 20 DATA INPUTS A4 B YA4 YB1 INERTING OUTPUTS A1 YB4 A OEB YA1 B4 B2 13 YB2 YB3 5 A YA2 B3 B YB3 YB2 A YA3 B2 B4 1 3 YB4 YB YA B1 OUTPUT ENABES OEA OEB 1 19 FUNCTION TABE INPUTS OUTPUTS OEA, OEB A, B YA, YB X Z 4/9 Motorola, Inc RE 1

78 MC4C240 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î Iin Maximum Input in = 5.5 or 0 to 5.5Î ± 0.1 ± 1.0 µa eakage Current MOTOROA 2 ery igh Speed CMOS ogic C Data D203 Rev 2

79 MC4C240 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit IOZ Maximum Three State in = I or I 5.5 Î eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A to YA or B to YB Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tpz, Output Enable Time Î = 3.3 ± 0.3 C = 15pF tpz OEA to YA or OEB to YB R = 1kΩ C = 50pF Î Î = 5.0 ± 0.5 C = 15pF R = 1kΩ C = 50pF tpz, Output Disable Time Î = 3.3 ± 0.3 C = 50pF tpz OEA to YA or OEB to YB Î R = 1kΩ Î = 5.0 ± 0.5 C = 50pF R = 1kΩ tos, Output to Output Skew = 3.3 ± 0.3 C = 50pF tos (Note 1.) Î = 5.0 ± 0.5 C = 50pF Î (Note 1.) Î Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in 6 pf igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 1 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per bit). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 ery igh Speed CMOS ogic C Data D203 Rev 2 3 MOTOROA

80 MC4C240 SWITCING WAEFORMS A or B YA or YB tp 50% 50% tp OEA or OEB YA or YB YA or YB 50% tpz 50% tpz 50% tpz tpz IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE Figure 1. Figure 2. TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit MOTOROA 4 ery igh Speed CMOS ogic C Data D203 Rev 2

81 SEMICONDUCTOR TECNICA DATA The MC4CT240A is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4CT240A is an inverting 3 state buffer, and has two active low output enables. This device is designed to be used with 3 state memory address drivers, etc. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT240A input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: tpd = 5.6 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 1.1 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 110 FETs or 2.5 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXXADW MC4CTXXXADT MC4CTXXXAM SOIC WIDE TSSOP SOIC EIAJ A1 OGIC DIAGRAM 2 1 YA1 PIN ASSIGNMENT OEA 1 20 A YA2 A OEB A YA3 YB4 A YA1 B4 DATA INPUTS A4 B YA4 YB1 INERTING OUTPUTS YB3 5 A3 6 YB YA2 B3 YA3 B2 13 YB2 A4 YB B2 YA4 B YB B1 B4 1 3 YB4 FUNCTION TABE INPUTS OUTPUTS OUTPUT ENABES OEA OEB 1 19 OEA, OEB A, B YA, YB X Z 4/9 Motorola, Inc RE 1

82 MC4CT240A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage Output in 3 State 0.5 to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage Output in 3 State Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î IOZ Maximum 3 State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 µa ICC Maximum uiescent in = or 5.5 Supply Current Î µa MOTOROA 6 ery igh Speed CMOS ogic C Data D203 Rev 2

83 MC4CT240A Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Max Symbol Test Conditio Min Unit Î ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay = 5.0 ± 0.5 C = 15pF tp A to YA or B to YB Î C = 50pF tpz, Output Enable Time Î = 5.0 ± 0.5 C = 15pF tpz OEA to YA or OEB to YB R = 1kΩ C = 50pF Î tpz, Output Disable Time = 5.0 ± 0.5 C = 50pF Î tpz OEA to YA or OEB to YB R = 1kΩ tos, Output to Output Skew = 5.0 ± 0.5 C = 50pF tos (Note 1.) Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in Î 9 pf igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 19 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per bit). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. ery igh Speed CMOS ogic C Data D203 Rev 2 MOTOROA

84 MC4CT240A SWITCING WAEFORMS A or B YA or YB tp OEA or OEB 1.5 tp tpz tpz O YA or YB O tpz tpz YA or YB 1.5 Figure 1. Figure 2. 3 IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit MOTOROA ery igh Speed CMOS ogic C Data D203 Rev 2

85 SEMICONDUCTOR TECNICA DATA The MC4C244 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4C244 is a noninverting 3 state buffer, and has two active low output enables. This device is designed to be used with 3 state memory address drivers, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3.9 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0.9 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 136 FETs or 34 Equivalent Gates A1 A2 4 OGIC DIAGRAM YA1 YA2 DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXDW MC4CXXXDT MC4CXXXM SOIC WIDE TSSOP SOIC EIAJ DATA INPUTS A3 A4 B1 B YA3 YA4 YB1 YB2 NONINERTING OUTPUTS PIN ASSIGNMENT OEA 1 20 A OEB YB4 3 1 YA1 A2 4 1 B4 B YB3 YB3 5 A YA2 B3 B4 1 3 YB4 YB2 14 YA3 A4 13 B2 YB YA4 OUTPUT ENABES OEA OEB B1 FUNCTION TABE INPUTS OUTPUTS OEA, OEB A, B YA, YB X Z 4/9 Motorola, Inc RE 2

86 MC4C244 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î Iin Maximum Input in = 5.5 or 0 to 5.5Î ± 0.1 ± 1.0 µa eakage Current MOTOROA 0 ery igh Speed CMOS ogic C Data D203 Rev 2

87 MC4C244 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit IOZ Maximum Three State in = I or I 5.5 Î eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A to YA or B to YB Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tpz, Output Enable Time Î = 3.3 ± 0.3 C = 15pF tpz OEA to YA or OEB to YB R = 1kΩ C = 50pF Î Î = 5.0 ± 0.5 C = 15pF R = 1kΩ C = 50pF tpz, Output Disable Time Î = 3.3 ± 0.3 C = 50pF tpz OEA to YA or OEB to YB Î R = 1kΩ Î = 5.0 ± 0.5 C = 50pF R = 1kΩ tos, Output to Output Skew = 3.3 ± 0.3 C = 50pF tos (Note 1.) Î = 5.0 ± 0.5 C = 50pF Î (Note 1.) Î Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in 6 pf igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 19 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per bit). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 ery igh Speed CMOS ogic C Data D203 Rev 2 1 MOTOROA

88 MC4C244 SWITCING WAEFORMS A or B YA or YB tp 50% 50% tp OEA or OEB YA or YB YA or YB 50% tpz 50% tpz 50% tpz tpz IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE Figure 1. Figure 2. TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit INPUT Figure 5. Input Equivalent Circuit MOTOROA 2 ery igh Speed CMOS ogic C Data D203 Rev 2

89 SEMICONDUCTOR TECNICA DATA The MC4CT244A is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4CT244A is a noninverting 3 state buffer, and has two active low output enables. This device is designed to be used with 3 state memory address drivers, etc. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT244A input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: tpd = 5.6 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 1.1 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 112 FETs or 2 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXXADW MC4CTXXXADT MC4CTXXXAM SOIC WIDE TSSOP SOIC EIAJ A1 OGIC DIAGRAM 2 1 YA1 PIN ASSIGNMENT OEA 1 20 A YA2 A OEB A YA3 YB4 A YA1 B4 DATA INPUTS A4 B YA4 YB1 NONINERTING OUTPUTS YB3 5 A3 6 YB YA2 B3 YA3 B2 13 YB2 A4 YB B2 YA4 B YB B1 B4 1 3 YB4 FUNCTION TABE INPUTS OUTPUTS OUTPUT ENABES OEA OEB 1 19 OEA, OEB A, B YA, YB X Z 4/9 Motorola, Inc RE 1

90 MC4CT244A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage Output in 3 State 0.5 to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage Output in 3 State Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î IOZ Maximum 3 State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 µa ICC Maximum uiescent in = or 5.5 Supply Current Î µa MOTOROA 4 ery igh Speed CMOS ogic C Data D203 Rev 2

91 MC4CT244A Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Max Symbol Test Conditio Min Unit Î ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay = 5.0 ± 0.5 C = 15pF tp A to YA or B to YB Î C = 50pF tpz, Output Enable Time Î = 5.0 ± 0.5 C = 15pF tpz OEA to YA or OEB to YB R = 1kΩ C = 50pF Î tpz, Output Disable Time = 5.0 ± 0.5 C = 50pF Î tpz OEA to YA or OEB to YB R = 1kΩ tos, Output to Output Skew = 5.0 ± 0.5 C = 50pF tos (Note 1.) Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in Î 9 pf igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 1 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per bit). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. ery igh Speed CMOS ogic C Data D203 Rev 2 5 MOTOROA

92 MC4CT244A SWITCING WAEFORMS A or B YA or YB tp OEA or OEB 1.5 tp tpz tpz O YA or YB 1.5 O 1.5 tpz tpz YA or YB 1.5 Figure 1. Figure 2. 3 IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit MOTOROA 6 ery igh Speed CMOS ogic C Data D203 Rev 2

93 SEMICONDUCTOR TECNICA DATA The MC4C245 is an advanced high speed CMOS octal bus traceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. It is intended for two way asynchronous communication between data buses. The direction of data tramission is determined by the level of the DIR input. The output enable pin (OE) can be used to disable the device, so that the buses are effectively isolated. All inputs are equipped with protection circuits agait static discharge. igh Speed: tpd = 4.0 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 1.2 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 30 FETs or Equivalent Gates APPICATION NOTES 1. Do not force a signal on an I/O pin when it is an active output, damage may occur. 2. All floating (high impedence) input or I/O pi must be fixed by mea of pull up or pull down resistors or bus terminator ICs. 3. A parasitic diode is formed between the bus and terminals. Therefore, the C245 cannot be used to interface 5 to 3 systems directly. DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXDW MC4CXXXDT MC4CXXXM SOIC WIDE TSSOP SOIC EIAJ OGIC DIAGRAM PIN ASSIGNMENT A DATA PORT A1 A2 A3 A4 A5 A6 A A DIR OE B1 1 B2 16 B3 15 B4 14 B5 13 B6 12 B 11 B B DATA PORT DIR A1 1 2 A2 3 A3 4 A4 5 A5 6 A6 A A OE B1 B2 B3 B4 B5 B6 B B FUNCTION TABE Control Inputs OE DIR Operation Data Tramitted from Bus B to Bus A Data Tramitted from Bus A to Bus B X Buses Isolated (igh Impedance State) 4/9 Motorola, Inc. 199 RE 2

94 MC4C245 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î Iin Maximum Input in = 5.5 or 0 to 5.5Î ± 0.1 ± 1.0 µa eakage Current (DIR, OE) MOTOROA ery igh Speed CMOS ogic C Data D203 Rev 2

95 MC4C245 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit IOZ Maximum Three State in = I or I 5.5 Î eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp A to B or B to A Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tpz, Output Enable Time Î = 3.3 ± 0.3 C = 15pF tpz OE to A or B R = 1 kω C = 50pF Î Î = 5.0 ± 0.5 C = 15pF R = 1 kω C = 50pF tpz, Output Disable Time Î = 3.3 ± 0.3 C = 50pF tpz OE to A or B Î R = 1 kω Î = 5.0 ± 0.5 C = 50pF R = 1 kω tos, Output to Output Skew = 3.3 ± 0.3 C = 50pF tos (Note 1.) Î = 5.0 ± 0.5 C = 50pF Î (Note 1.) Î Cin Maximum Input Capacitance pf DIR, OE CI/O Maximum Three State pf I/O Capacitance 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 21 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per bit). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 ery igh Speed CMOS ogic C Data D203 Rev 2 9 MOTOROA

96 MC4C245 SWITCING WAEFORMS DIR 50% A or B B or A tp 50% 50% tp OE A or B A or B 50% tpz 50% tpz 50% tpz tpz 50% IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE Figure 1. Figure 2. TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance Figure 3. * Includes all probe and jig capacitance Figure 4. MOTOROA 90 ery igh Speed CMOS ogic C Data D203 Rev 2

97 MC4C245 EXPANDED OGIC DIAGRAM A1 A2 A3 A4 A5 A6 A A B1 B2 B3 B4 B5 B6 B B DIR 1 OE 19 INPUT EUIAENT CIRCUIT BUS TERMINA EUIAENT CIRCUIT DIR, OE A, B INPUT I/O ery igh Speed CMOS ogic C Data D203 Rev 2 91 MOTOROA

98 SEMICONDUCTOR TECNICA DATA The MC4CT245A is an advanced high speed CMOS octal bus traceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. It is intended for two way asynchronous communication between data buses. The direction of data tramission is determined by the level of the DIR input. The output enable pin (OE) can be used to disable the device, so that the buses are effectively isolated. All inputs are equipped with protection circuits agait static discharge. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT245A input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: tpd = 4.9 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 1.6 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 304 FETs or 6 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXXADW MC4CTXXXADT MC4CTXXXAM SOIC WIDE TSSOP SOIC EIAJ APPICATION NOTES 1. Do not force a signal on an I/O pin when it is an active output, damage may occur. 2. All floating (high impedence) input or I/O pi must be fixed by mea of pull up or pull down resistors or bus terminator ICs. PIN ASSIGNMENT DIR 1 20 A OE A2 3 1 B1 OGIC DIAGRAM A3 4 1 B2 A DATA PORT A1 A2 A3 A4 A5 A6 A A B1 1 B2 16 B3 15 B4 14 B5 13 B6 12 B 11 B B DATA PORT A4 5 A5 6 A6 A A 9 10 FUNCTION TABE B3 B4 B5 B6 B B DIR OE 1 19 Control Inputs OE DIR Operation X Data Tx from Bus B to Bus A Data Tx from Bus A to Bus B Buses Isolated (igh Z State) 4/9 Motorola, Inc RE 1

99 MC4CT245A MAXIMUM RATINGS* DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 I/O DC Output oltage Outputs in 3 State 0.5 to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit Î DC Supply oltage Î in DC Input oltage Î I/O DC Output oltage Outputs in 3 StateÎ Î igh or ow State TA Operating Temperature C tr, tf Input Rise and Fall Time =5.0 ± / Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage 4.5 to I Maximum ow evel 4.5 to Input oltage 5.5 O Minimum igh evel IO = 50µA 4.5 Output oltage in = I or I IO = ma Î 3.0 Î O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 eakage Current ± 0.1 ± 1.0 µa IOZ Maximum 3 State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or µa Supply Current Î ICCT uiescent Supply Per Input: IN = Current Other Input: or ma IOPD Output eakage OUT = Current Î µa ery igh Speed CMOS ogic C Data D203 Rev 2 93 MOTOROA

100 MC4CT245A Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay = 5.0 ± 0.5 C = 15pF tp A to B or B to A Î C = 50pF tpz, Output Enable Time Î = 5.0 ± 0.5 C = 15pF tpz OE to A or B R = 1kΩ C = 50pF Î tpz, Output Disable Time = 5.0 ± 0.5 C = 50pF Î tpz OE to A or B R = 1kΩ tos, Output to Output Skew = 5.0 ± 0.5 C = 50pF tos (Note 1.) Î Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in 13 pf igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 16 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per bit). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. SWITCING WAEFORMS DIR A or B B or A tp tp 3 OE 1.5 tpz O O A or B 1.5 tpz A or B 1.5 tpz tpz IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE Figure 1. Figure 2. MOTOROA 94 ery igh Speed CMOS ogic C Data D203 Rev 2

101 MC4CT245A TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance Figure 3. * Includes all probe and jig capacitance Figure 4. EXPANDED OGIC DIAGRAM A1 2 1 B1 A2 3 1 B2 A B3 A B4 A B5 A6 13 B6 A 12 B A 9 11 B DIR 1 OE 19 ery igh Speed CMOS ogic C Data D203 Rev 2 95 MOTOROA

102 SEMICONDUCTOR TECNICA DATA The MC4C33 is an advanced high speed CMOS octal latch with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This bit D type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 5.0 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0.9 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 16 FETs or 46.5 Equivalent Gates OGIC DIAGRAM DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXDW MC4CXXXDT MC4CXXXM SOIC WIDE TSSOP SOIC EIAJ DATA INPUTS 3 D0 4 D1 D2 D3 13 D4 14 D5 1 D6 D NONINERTING OUTPUTS PIN ASSIGNMENT OE D0 3 1 D D1 4 1 D E OE 11 1 D2 D D5 D E FUNCTION TABE INPUTS OUTPUT OE E D X X X No Change Z 4/9 Motorola, Inc RE 2

103 MC4C33 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = / = Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µ in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î Iin Maximum Input in = 5.5 or 0 to 5.5Î ± 0.1 ± 1.0 µa eakage Current ery igh Speed CMOS ogic C Data D203 Rev 2 9 MOTOROA

104 MC4C33 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit IOZ Maximum Three State in = I or I 5.5 Î eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp D to Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp E to C = 50pF Î Î = 5.0 ± 0.5 C = 15pF C = 50pF tpz, Output Enable Time, Î = 3.3 ± 0.3 C = 15pF tpz OE to Î R = 1kΩ C = 50pF = 5.0 ± 0.5 C = 15pF R = 1kΩ C = 50pF tpz, Output Disable Time, = 3.3 ± 0.3 C = 50pF tpz OE to Î R = 1kΩ Î = 5.0 ± 0.5 C = 50pF Î R = 1kΩ Î tos, Output to Output Skew Î = 3.3 ± 0.3 C = 50pF Î tos (Note 1.) Î Î = 5.5 ± 0.5 C = 50pF (Note 1.) Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in Î 6 pf igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 2 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per latch). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50 pf, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 MOTOROA 9 ery igh Speed CMOS ogic C Data D203 Rev 2

105 MC4C33 TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Typ imit imit Unit tw(h) Minimum Pulse Width, E = 3.3 ± 0.3 = 5.0 ± tsu Minimum Setup Time, D to E = 3.3 ± 0.3 = 5.0 ± th Minimum old Time, D to E = 3.3 ± 0.3 = 5.0 ± SWITCING WAEFORMS D tp 50% tp E 50% tw tp tp 50% 50% Figure 1. Figure 2. OE 50% tpz 50% tpz O +0.3 IG IMPEDANCE D 50% tsu AID th tpz 50% tpz O 0.3 IG IMPEDANCE E 50% Figure 3. Figure 4. ery igh Speed CMOS ogic C Data D203 Rev 2 99 MOTOROA

106 MC4C33 TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 5. Figure 6. EXPANDED OGIC DIAGRAM D0 3 D1 4 D2 D3 D4 13 D5 14 D6 1 D 1 D D D D D D D D E E E E E E E E E 11 OE INPUT EUIAENT CIRCUIT INPUT MOTOROA 100 ery igh Speed CMOS ogic C Data D203 Rev 2

107 SEMICONDUCTOR TECNICA DATA The MC4CT33A is an advanced high speed CMOS octal latch with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This bit D type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT33A input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: tpd =. (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 1.6 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 196 FETs or 49 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXXADW MC4CTXXXADT MC4CTXXXAM PIN ASSIGNMENT SOIC WIDE TSSOP SOIC EIAJ OGIC DIAGRAM OE 1 20 DATA INPUTS D0 D1 D2 D3 D D5 1 D6 D 1 E OE NONINERTING OUTPUTS 0 2 D0 3 D D2 D D D6 6 5 D5 D4 4 E FUNCTION TABE INPUTS OUTPUT OE E D X X X No Change Z 6/9 Motorola, Inc RE 0

108 MC4CT33A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage Outputs in 3 State 0.5 to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage Outputs in 3 State Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î IOZ Maximum 3 State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 µa ICC Maximum uiescent in = or 5.5 Supply Current Î µa MOTOROA 102 ery igh Speed CMOS ogic C Data D203 Rev 2

109 MC4CT33A Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Max Symbol Test Conditio Min Unit Î ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 5.0 ± 0.5 C = 15pF tp E to Î C = 50pF tp, Maximum Propagation Delay, Î = 5.0 ± 0.5 C = 15pF tp D to C = 50pF Î tpz, Output Enable Time, Î = 5.0 ± 0.5 C = 15pF tpz OE to R = 1kΩ C = 50pF tpz, Output Disable Time, = 5.0 ± 0.5 C = 50pF tpz OE to Î R = 1kΩ tos, Output to Output Skew Î = 5.5 ± 0.5 C = 50pF tos (Note 1.) Î Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in igh Impedance State) Î 6 pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 25 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per latch). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50 pf, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Typ imit imit Unit tw(h) Minimum Pulse Width, E = 5.0 ± tsu Minimum Setup Time, D to E = 5.0 ± th Minimum old Time, D to E = 5.0 ± ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

110 MC4CT33A SWITCING WAEFORMS D tp 1.5 tp 3 E tw 1.5 tp tp O O 1.5 O O Figure 1. Figure 2. OE tpz tpz tpz tpz 3 IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE Figure 3. Figure 4. D E 1.5 tsu AID th TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 5. Figure 6. MOTOROA 104 ery igh Speed CMOS ogic C Data D203 Rev 2

111 MC4CT33A EXPANDED OGIC DIAGRAM D0 3 D1 4 D2 D3 D4 13 D5 14 D6 1 D 1 D D D D D D D D E E E E E E E E E 11 OE ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

112 SEMICONDUCTOR TECNICA DATA The MC4C34 is an advanced high speed CMOS octal flip flip with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This bit D type flip flop is controlled by a clock input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: fmax = 15Mz (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0.9 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 266 FETs or 66.5 Equivalent Gates DATA INPUTS 3 D0 4 D1 D2 D3 13 D4 14 D5 1 D6 D 1 CP OE 11 1 FUNCTION TABE OGIC DIAGRAM NONINERTING OUTPUTS DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXDW MC4CXXXDT MC4CXXXM PIN ASSIGNMENT OE 0 D0 D1 2 D2 D SOIC WIDE TSSOP SOIC EIAJ D D6 6 5 D5 D4 4 CP INPUTS OUTPUT OE CP D,, X X X No Change Z 4/9 Motorola, Inc RE 2

113 MC4C34 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = / = Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î ery igh Speed CMOS ogic C Data D203 Rev 2 10 MOTOROA

114 MC4C34 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa IOZ Maximum Three State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or 5.5 Î µa Supply Current Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Î Test Conditio Min Typ Max Min Max Unit fmax Maximum Clock Frequency Î = 3.3 ± 0.3 C = 15pF 0 (50% Duty Cycle) C = 50pF = 5.0 ± 0.5 C = 15pF Î C = 50pF tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp CP to Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF tpz, Output Enable Time, Î = 3.3 ± 0.3 C = 15pF tpz OE to R = 1kΩ C = 50pF Î Î = 5.0 ± 0.5 C = 15pF R = 1kΩ C = 50pF tpz, Output Disable Time, Î = 3.3 ± 0.3 C = 50pF tpz OE to Î R = 1kΩ Î = 5.0 ± 0.5 C = 50pF R = 1kΩ tos, Output to Output Skew = 3.3 ± 0.3 C = 50pF tos (Note 1.) Î = 5.0 ± 0.5 C = 50pF Î (Note 1.) Î Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in 6 pf igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 32 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per flip flop). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. MOTOROA 10 ery igh Speed CMOS ogic C Data D203 Rev 2

115 MC4C34 NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Typ imit imit Unit tw Minimum Pulse Width, CP = 3.3 ± 0.3 = 5.0 ± tsu Minimum Setup Time, D to CP = 3.3 ± 0.3 = 5.0 ± th Minimum old Time, D to CP = 3.3 ± 0.3 = 5.0 ± tr, tf Maximum Input Rise and Fall Times = 3.3 ± 0.3 = 5.0 ± 0.5 SWITCING WAEFORMS CP 50% tw 1/fmax tp tp OE 50% tpz 50% tpz tpz tpz O +0.3 IG IMPEDANCE 50% Figure 1. 50% Figure 2. O 0.3 IG IMPEDANCE AID D 50% tsu th CP 50% Figure 3. ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

116 MC4C34 TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance Figure 4. * Includes all probe and jig capacitance Figure 5. EXPANDED OGIC DIAGRAM D0 3 D1 4 D2 D3 D4 13 D5 14 D6 1 D 1 D D D D D D D D C C C C C C C C CP 11 OE INPUT EUIAENT CIRCUIT INPUT MOTOROA 110 ery igh Speed CMOS ogic C Data D203 Rev 2

117 SEMICONDUCTOR TECNICA DATA The MC4CT34A is an advanced high speed CMOS octal flip flop with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This bit D type flip flop is controlled by a clock input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT34A input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: fmax = 140Mz (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 1.6 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 26 FETs or 69 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXXADW MC4CTXXXADT MC4CTXXXAM PIN ASSIGNMENT SOIC WIDE TSSOP SOIC EIAJ DATA INPUTS D0 D1 D2 D3 D D5 1 D6 D 1 11 CP OGIC DIAGRAM NONINERTING OUTPUTS OE D0 3 D D2 D D D6 6 5 D5 D4 4 OE CP FUNCTION TABE INPUTS OUTPUT OE CP D,, X X X No Change Z 6/9 Motorola, Inc RE 0

118 MC4CT34A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage Outputs in 3 State 0.5 to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage Outputs in 3 State Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î IOZ Maximum 3 State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 µa ICC Maximum uiescent in = or 5.5 Supply Current Î µa MOTOROA 112 ery igh Speed CMOS ogic C Data D203 Rev 2

119 MC4CT34A Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Max Symbol Test Conditio Min Unit Î ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit fmax Maximum Clock Frequency = 5.0 ± 0.5 C = 15pF 90 (50% Duty Cycle) Î C = 50pF Mz tp, Maximum Propagation Delay, Î = 5.0 ± 0.5 C = 15pF tp CP to C = 50pF Î tpz, Output Enable Time, Î = 5.0 ± 0.5 C = 15pF tpz OE to R = 1kΩ C = 50pF tpz, Output Disable Time = 5.0 ± 0.5 C = 50pF tpz OE to Î R = 1kΩ tos, Output to Output Skew Î = 5.0 ± 0.5 C = 50pF tos (Note 1.) Î Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in igh Impedance State) Î 9 pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 25 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per flip flop). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Typ imit imit Unit tw Minimum Pulse Width, CP = 5.0 ± tsu Minimum Setup Time, D to CP = 5.0 ± th Minimum old Time, D to CP = 5.0 ± ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

120 MC4CT34A SWITCING WAEFORMS CP 1.5 tw 1/fmax tp tp 1.5 Figure 1. 3 O O OE 1.5 tpz tpz 1.5 tpz tpz 1.5 Figure 2. 3 O +0.3 O 0.3 IG IMPEDANCE IG IMPEDANCE AID 3 D 1.5 tsu th CP Figure 3. TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance Figure 4. * Includes all probe and jig capacitance Figure 5. EXPANDED OGIC DIAGRAM D0 3 D1 4 D2 D3 D4 13 D5 14 D6 1 D 1 D D D D D D D D C C C C C C C C CP 11 OE MOTOROA 114 ery igh Speed CMOS ogic C Data D203 Rev 2

121 SEMICONDUCTOR TECNICA DATA The MC4C393 is an advanced high speed CMOS dual 4 bit binary ripple counter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This device coists of two independent 4 bit binary ripple counters with parallel outputs from each counter stage. A 256 counter can be obtained by cascading the two binary counters. Internal flip flops are triggered by high to low traitio of the clock input. Reset for the counters is asynchronous and active high. State changes of the outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the C393. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: fmax = 10Mz (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 0. (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 236 FETs or 59 Equivalent Gates D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 M SUFFIX 14 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXD MC4CXXXDT MC4CXXXM SOIC TSSOP SOIC EIAJ OGIC DIAGRAM PIN ASSIGNMENT CP CPn RDn 1, 13 2, 12 BINARY COUNTER 3, 11 4, 10 5, 9 6, na nb nc nd RD1 1A 1B 1C 1D CP2 RD2 2A 2B 2C 2D FUNCTION TABE Inputs Clock Reset Outputs X No Change No Change No Change Next State 4/9 Motorola, Inc RE 1

122 MC4C393 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = / = Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 116 ery igh Speed CMOS ogic C Data D203 Rev 2

123 MC4C393 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit fmax Maximum Clock Frequency = 3.3 ± 0.3 C = 15pF 5 (50% Duty Cycle) Î C = 50pF Î = 5.0 ± 0.5 C = 15pF 125 Î C = 50pF tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp CP to A C = 50pF Î Î = 5.0 ± 0.5 C = 15pF C = 50pF tp, Maximum Propagation Delay, Î = 3.3 ± 0.3 C = 15pF tp CP to B Î C = 50pF = 5.0 ± 0.5 C = 15pF C = 50pF tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp CP to C Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF tp, Maximum Propagation Delay, Î = 3.3 ± 0.3 C = 15pF tp CP to D C = 50pF Î Î = 5.0 ± 0.5 C = 15pF C = 50pF tp Maximum Propagation Delay, Î = 3.3 ± 0.3 C = 15pF RD to n Î C = 50pF = 5.0 ± 0.5 C = 15pF C = 50pF tos, Output to Output Skew = 3.3 ± 0.3 C = 50pF tos (Note 1.) Î Î = 5.0 ± 0.5 C = 50pF (Note 1.) Î Maximum Input Capacitance pf Cin 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 23 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / 2 (per 4 bit counter). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. ery igh Speed CMOS ogic C Data D203 Rev 2 11 MOTOROA

124 MC4C393 NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Typ imit imit Unit tw Minimum Pulse Width, CP = 3.3 ± 0.3 = 5.0 ± tw Minimum Pulse Width, RD = 3.3 ± 0.3 = 5.0 ± trec Minimum Recovery Time, RD to CP = 3.3 ± 0.3 = 5.0 ± tr, tf Minimum Input Rise and Fall Times = 3.3 ± 0.3 = 5.0 ± SWITCING WAEFORMS CP 50% tw 1/fmax tp tp RD n tw 50% tp 50% n 50% CP trec 50% Figure 1. Figure 2. TEST POINT DEICE UNDER TEST OUTPUT C* * Includes all probe and jig capacitance Figure 3. Test Circuit MOTOROA 11 ery igh Speed CMOS ogic C Data D203 Rev 2

125 MC4C393 EXPANDED OGIC DIAGRAM CP 1, 13 C D 3, 11 A C D 4, 10 B C D 5, 9 C C D 6, D RD 2, 12 ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

126 MC4C393 TIMING DIAGRAM CP RD A B C D COUNT SEUENCE Outputs Count D C B A MOTOROA 120 ery igh Speed CMOS ogic C Data D203 Rev 2

127 SEMICONDUCTOR TECNICA DATA The MC4C540 is an advanced high speed CMOS inverting octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4C540 features inputs and outputs on opposite sides of the package and two AND ed active low output enables. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3. (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 1.2 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 124 FETs or 31 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXDW MC4CXXXDT MC4CXXXM SOIC WIDE TSSOP SOIC EIAJ OGIC DIAGRAM A1 2 1 Y1 PIN ASSIGNMENT A2 3 1 Y2 OE A Y3 A1 A OE2 Y1 DATA INPUTS A4 A Y4 14 Y5 INERTING OUTPUTS A3 4 A4 5 A Y2 Y3 Y4 A6 13 Y6 A6 A Y5 Y6 A 12 Y A 9 12 Y A 9 11 Y Y OUTPUT ENABES OE1 OE FUNCTION TABE Inputs OE1 OE2 A Output Y X X X X Z Z 4/9 Motorola, Inc RE 1

128 MC4C540 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / (Figure 1) =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 122 ery igh Speed CMOS ogic C Data D203 Rev 2

129 MC4C540 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa IOZ Maximum Three State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or 5.5 Î µa Supply Current Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Î Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, Î = 3.3 ± 0.3 C = 15pF tp A to Y C = 50pF Î (Figures 1 and 3) = 5.0 ± 0.5 C = 15pF C = 50pF tpz, Output Enable TIme, = 3.3 ± 0.3 C = 15pF tpz OEn to Y Î R = 1kΩ C = 50pF (Figures 2 and 4) Î = 5.0 ± 0.5 C = 15pF R = 1kΩ C = 50pF tpz, Output Disable Time, Î = 3.3 ± 0.3 C = 50pF 11.2 tpz OEn to Y R = 1kΩ (Figures 2 and 4) = 5.0 ± 0.5 C = 50pF R = 1kΩ tos, Output to Output Skew Î = 3.3 ± 0.3 C = 50pF tos (Note 1.) 1.5 = 5.0 ± 0.5 C = 50pF Î 1.0 (Note 1.) Î Cin Maximum Input Capacitance pf Î Cout Maximum Three State Output 6 pf Capacitance (Output in igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 1 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per bit). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

130 MC4C540 SWITCING WAEFORMS A tp 50% tp OE1 or OE2 50% 50% Y tpz 50% tpz O +0.3 IG IMPEDANCE Y 50% Figure 1. Y tpz tpz 50% Figure 2. O 0.3 IG IMPEDANCE TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1kΩ C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 3. Figure 4. INPUT EUIAENT CIRCUIT INPUT MOTOROA 124 ery igh Speed CMOS ogic C Data D203 Rev 2

131 SEMICONDUCTOR TECNICA DATA The MC4C541 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4C541 is a noninverting type. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 3. (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 1.2 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 134 FETs or 33.5 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE OGIC DIAGRAM ORDERING INFORMATION A1 A Y1 1 Y2 MC4CXXXDW MC4CXXXDT MC4CXXXM SOIC WIDE TSSOP SOIC EIAJ A Y3 PIN ASSIGNMENT DATA INPUTS A4 A5 A Y4 14 Y5 13 Y6 NONINERTING OUTPUTS OE1 A1 A2 A OE2 Y1 Y2 A 12 Y A4 5 A Y3 Y4 OUTPUT ENABES 9 A OE1 OE Y A6 A A Y5 Y6 Y Y FUNCTION TABE Inputs OE1 OE2 A Output Y X X Z X X Z 4/9 Motorola, Inc RE 2

132 MC4C541 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 126 ery igh Speed CMOS ogic C Data D203 Rev 2

133 MC4C541 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa IOZ Maximum Three State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or 5.5 Î µa Supply Current Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Î Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, Î = 3.3 ± 0.3 C = 15pF tp A to Y C = 50pF Î = 5.0 ± 0.5 C = 15pF C = 50pF tpz, Output Enable TIme, = 3.3 ± 0.3 C = 15pF tpz OE to Y Î R = 1kΩ C = 50pF Î = 5.0 ± 0.5 C = 15pF Î R = 1kΩ C = 50pF tpz, Output Disable Time, Î = 3.3 ± 0.3 C = 50pF 11.2 tpz OE to Y R = 1kΩ Î Î = 5.0 ± 0.5 C = 50pF R = 1kΩ tos, Output to Output Skew Î = 3.3 ± 0.3 C = 50pF tos (Note 1.) Î = 5.0 ± 0.5 C = 50pF Î (Note 1.) Î Cin Maximum Input Capacitance pf Î Cout Maximum Three State Output 6 pf Capacitance (Output in igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 1 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per bit). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 ery igh Speed CMOS ogic C Data D203 Rev 2 12 MOTOROA

134 MC4C541 SWITCING WAEFORMS A tp 50% tp OE1 or OE2 50% 50% Y tpz 50% tpz O +0.3 IG IMPEDANCE Y 50% Figure 1. Y tpz tpz 50% Figure 2. O 0.3 IG IMPEDANCE TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1kΩ C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 3. Figure 4. INPUT EUIAENT CIRCUIT INPUT MOTOROA 12 ery igh Speed CMOS ogic C Data D203 Rev 2

135 SEMICONDUCTOR TECNICA DATA The MC4CT541A is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4CT541A is a noninverting, 3 state, buffer/line driver/line receiver. When either OE1 or OE2 is high, the terminal outputs are in the high impedance state. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT541A input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: tpd = 5.4 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 1.6 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 134 FETs or 33.5 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXXADW MC4CTXXXADT MC4CTXXXAM PIN ASSIGNMENT SOIC WIDE TSSOP SOIC EIAJ OGIC DIAGRAM OE A1 2 1 Y1 A1 A OE2 Y1 A2 A Y2 16 Y3 A3 4 A4 5 A Y2 Y3 Y4 DATA INPUTS A4 A Y4 14 Y5 NONINERTING OUTPUTS A6 A A Y5 Y6 Y A6 13 Y Y A 12 Y FUNCTION TABE OUTPUT ENABES 9 A OE1 OE Y X Inputs OE1 OE2 A X X X Output Y Z Z 6/9 Motorola, Inc RE 0

136 MC4CT541A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage Outputs in 3 State 0.5 to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage Outputs in 3 State Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î IOZ Maximum 3 State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 µa ICC Maximum uiescent in = or 5.5 Supply Current Î µa MOTOROA 130 ery igh Speed CMOS ogic C Data D203 Rev 2

137 MC4CT541A Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Max Symbol Test Conditio Min Unit Î ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 5.0 ± 0.5 C = 15pF tp A to Y Î C = 50pF tpz, Output Enable TIme, Î = 5.0 ± 0.5 C = 15pF tpz OE to Y R = 1kΩ C = 50pF Î tpz, Output Disable Time, = 5.0 ± 0.5 C = 50pF Î tpz OE to Y R = 1kΩ tos, Output to Output Skew = 5.0 ± 0.5 C = 50pF tos (Note 1.) Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in igh Î 9 pf Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 19 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per bit). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

138 MC4CT541A SWITCING WAEFORMS A Y tp OE1 or OE2 1.5 tp tpz tpz O Y 1.5 O 1.5 tpz tpz Y 1.5 Figure 1. Figure 2. 3 IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit MOTOROA 132 ery igh Speed CMOS ogic C Data D203 Rev 2

139 SEMICONDUCTOR TECNICA DATA The MC4C53 is an advanced high speed CMOS octal latch with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This bit D type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: tpd = 4.5 (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 1.2 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 21 FETs or 54.5 Equivalent Gates OGIC DIAGRAM DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXDW MC4CXXXDT MC4CXXXM SOIC WIDE TSSOP SOIC EIAJ DATA INPUTS D0 D1 D2 D3 D4 D5 D6 D NONINERTING OUTPUTS PIN ASSIGNMENT OE 1 20 D D D D E OE 11 1 D4 D5 D D 9 12 FUNCTION TABE E INPUTS OUTPUT OE E D X X X No Change Z 4/9 Motorola, Inc RE 2

140 MC4C53 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = / = Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î Iin Maximum Input in = 5.5 or 0 to 5.5Î ± 0.1 ± 1.0 µa eakage Current MOTOROA 134 ery igh Speed CMOS ogic C Data D203 Rev 2

141 MC4C53 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit IOZ Maximum Three State in = I or I 5.5 Î eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or 5.5 Supply Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp E to Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF Î tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp D to C = 50pF Î Î = 5.0 ± 0.5 C = 15pF C = 50pF tpz, Output Enable Time, Î = 3.3 ± 0.3 C = 15pF tpz OE to Î R = 1kΩ C = 50pF = 5.0 ± 0.5 C = 15pF R = 1kΩ C = 50pF tpz, Output Disable Time, = 3.3 ± 0.3 C = 50pF tpz OE to Î R = 1kΩ Î = 5.0 ± 0.5 C = 50pF Î R = 1kΩ Î tos, Output to Output Skew Î = 3.3 ± 0.3 C = 50pF Î tos (Note 1.) Î Î = 5.5 ± 0.5 C = 50pF (Note 1.) Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in Î 6 pf igh Impedance State) 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 29 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per latch). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50 pf, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

142 MC4C53 TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Typ imit imit Unit tw(h) Minimum Pulse Width, E = 3.3 ± 0.3 = 5.0 ± tsu Minimum Setup Time, D to E = 3.3 ± 0.3 = 5.0 ± th Minimum old Time, D to E = 3.3 ± 0.3 = 5.0 ± SWITCING WAEFORMS D tp 50% tp E 50% tw tp tp 50% 50% Figure 1. Figure 2. OE 50% tpz 50% tpz O +0.3 IG IMPEDANCE D 50% tsu AID th tpz 50% tpz O 0.3 IG IMPEDANCE E 50% Figure 3. Figure 4. MOTOROA 136 ery igh Speed CMOS ogic C Data D203 Rev 2

143 MC4C53 TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 5. Figure 6. EXPANDED OGIC DIAGRAM D0 2 D E 19 0 D1 3 D E 1 1 D2 4 D E 1 2 D3 5 D E 16 3 D4 6 D E 15 4 D5 D E 14 5 D6 D E 13 6 D 9 D E 12 E 11 OE 1 INPUT Figure. Input Equivalent Circuit ery igh Speed CMOS ogic C Data D203 Rev 2 13 MOTOROA

144 SEMICONDUCTOR TECNICA DATA The MC4CT53A is an advanced high speed CMOS octal latch with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This bit D type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT53A input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: tpd =. (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 1.6 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 234 FETs or 5.5 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXXADW MC4CTXXXADT MC4CTXXXAM PIN ASSIGNMENT SOIC WIDE TSSOP SOIC EIAJ OE 1 20 OGIC DIAGRAM D DATA INPUTS D0 D1 D2 D3 D4 D5 D6 D NONINERTING OUTPUTS D1 3 D2 4 D3 5 D4 6 D5 D6 D E E 11 OE 1 FUNCTION TABE INPUTS OUTPUT OE E D X X X No Change Z 6/9 Motorola, Inc RE 0

145 MC4CT53A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage Outputs in 3 State 0.5 to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage Outputs in 3 State Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î IOZ Maximum 3 State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 µa ICC Maximum uiescent in = or 5.5 Supply Current Î µa ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

146 MC4CT53A Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Max Symbol Test Conditio Min Unit Î ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit tp, Maximum Propagation Delay, = 5.0 ± 0.5 C = 15pF tp E to Î C = 50pF tp, Maximum Propagation Delay, Î = 5.0 ± 0.5 C = 15pF tp D to C = 50pF Î tpz, Output Enable Time, Î = 5.0 ± 0.5 C = 15pF tpz OE to R = 1kΩ C = 50pF tpz, Output Disable Time, = 5.0 ± 0.5 C = 50pF tpz OE to Î R = 1kΩ tos, Output to Output Skew Î = 5.5 ± 0.5 C = 50pF tos (Note 1.) Î Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance (Output in igh Impedance State) Î 6 pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 25 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per latch). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50 pf, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Typ imit imit Unit tw(h) Minimum Pulse Width, E = 5.0 ± tsu Minimum Setup Time, D to E = 5.0 ± th Minimum old Time, D to E = 5.0 ± MOTOROA 140 ery igh Speed CMOS ogic C Data D203 Rev 2

147 MC4CT53A SWITCING WAEFORMS D tp 1.5 tp 3 E tw 1.5 tp tp O O 1.5 O O Figure 1. Figure 2. OE tpz tpz tpz tpz 3 IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE Figure 3. Figure 4. D E 1.5 tsu AID th TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 5. Figure 6. ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

148 MC4CT53A EXPANDED OGIC DIAGRAM D0 2 D E 19 0 D1 3 D E 1 1 D2 4 D E 1 2 D3 5 D E 16 3 D4 6 D E 15 4 D5 D E 14 5 D6 D E 13 6 D 9 D E 12 E 11 1 OE MOTOROA 142 ery igh Speed CMOS ogic C Data D203 Rev 2

149 SEMICONDUCTOR TECNICA DATA The MC4C54 is an advanced high speed CMOS octal flip flip with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This bit D type flip flop is controlled by a clock input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: fmax = 10Mz (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 1.2 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 266 FETs or 66.5 Equivalent Gates DATA INPUTS 2 D0 3 D1 4 D2 5 D3 6 D4 D5 D6 D 9 CP OE 11 1 OGIC DIAGRAM NONINERTING OUTPUTS DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXDW MC4CXXXDT MC4CXXXM PIN ASSIGNMENT OE D0 D1 D2 D4 D5 D6 D D SOIC WIDE TSSOP SOIC EIAJ CP FUNCTION TABE INPUTS OUTPUT OE CP D,, X X X No Change Z 4/9 Motorola, Inc RE 2

150 MC4C54 MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage 0.5 to I IK Input Diode Current 20 ma I OK Output Diode Current ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature C tr, tf Input Rise and Fall Time = / = Î DC EECTRICA CARACTERISTICS Î TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel Input oltage to x x Î I Maximum ow evel Î Input oltage 3.0 to Î x 0.3 x 5.5 Î O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel in = I or I 2.0 Î Output oltage IO = 50µA Î in = I or I IO = 4mA IO = ma 4.5 Î MOTOROA 144 ery igh Speed CMOS ogic C Data D203 Rev 2

151 MC4C54 Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Min Max Symbol Test Conditio Unit Iin Maximum Input in = 5.5 or 0 to 5.5 Î eakage Current ± 0.1 ± 1.0 Î µa IOZ Maximum Three State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 Î µa ICC Maximum uiescent in = or 5.5 Î µa Supply Current Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Î Test Conditio Min Typ Max Min Max Unit fmax Maximum Clock Frequency Î = 3.3 ± 0.3 C = 15pF 0 (50% Duty Cycle) C = 50pF Î = 5.0 ± 0.5 C = 15pF C = 50pF Î tp, Maximum Propagation Delay, = 3.3 ± 0.3 C = 15pF tp CP to Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF tpz, Output Enable Time, Î = 3.3 ± 0.3 C = 15pF tpz OE to R = 1kΩ C = 50pF Î Î = 5.0 ± 0.5 C = 15pF R = 1kΩ C = 50pF tpz, Output Disable Time, Î = 3.3 ± 0.3 C = 50pF tpz OE to Î R = 1kΩ Î = 5.0 ± 0.5 C = 50pF R = 1kΩ Î tos, Output to Output Skew = 3.3 ± 0.3 C = 50pF tos (Note 1.) Î Î = 5.0 ± 0.5 C = 50pF Î (Note 1.) Î Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance, Output in 6 pf igh Impedance State 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 2 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per flip flop). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

152 MC4C54 NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Typ imit imit Unit tsu Minimum Setup Time, D to CP = 3.3 ± 0.3 = 5.0 ± th Minimum old Time, CP to D = 3.3 ± 0.3 = 5.0 ± tw Minimum Pulse Width, CP = 3.3 ± 0.3 = 5.0 ± SWITCING WAEFORMS CP 50% OE 50% tw tpz tpz 1/fmax tp tp 50% tpz tpz 50% 50% Figure 1. Figure 2. IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE MOTOROA 146 ery igh Speed CMOS ogic C Data D203 Rev 2

153 MC4C54 D 50% tsu AID th D0 2 EXPANDED OGIC DIAGRAM C D 19 0 CP 50% D1 3 C D 1 1 Figure 3. D2 4 C D 1 2 DEICE UNDER TEST OUTPUT TEST POINT C* D3 D4 5 6 C D C D D5 C D 14 5 * Includes all probe and jig capacitance Figure 4. D6 C D 13 6 TEST POINT D 9 C D 12 DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. CP OE 11 1 * Includes all probe and jig capacitance Figure 5. Test Circuit INPUT EUIAENT CIRCUIT INPUT ery igh Speed CMOS ogic C Data D203 Rev 2 14 MOTOROA

154 SEMICONDUCTOR TECNICA DATA The MC4CT54A is an advanced high speed CMOS octal flip flop with 3 state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. This bit D type flip flop is controlled by a clock input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state. The CT inputs are compatible with TT levels. This device can be used as a level converter for interfacing 3.3 to 5.0, because it has full 5 CMOS level output swings. The CT54A input and output (when disabled) structures provide protection when voltages between 0 and 5.5 are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage input/output voltage mismatch, battery backup, hot iertion, etc. igh Speed: fmax = 140Mz (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at TT Compatible Inputs: I = 0.; I = 2.0 Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5 to 5.5 Operating Range ow Noise: OP = 1.6 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 26 FETs or 1.5 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 M SUFFIX 20 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CTXXXADW MC4CTXXXADT MC4CTXXXAM SOIC WIDE TSSOP SOIC EIAJ DATA INPUTS D0 D1 D2 D3 D D5 D6 D 9 CP OE 11 1 FUNCTION TABE OGIC DIAGRAM NONINERTING OUTPUTS PIN ASSIGNMENT OE D D D D D D D D CP INPUTS OUTPUT OE CP D,, X X X No Change Z 6/9 Motorola, Inc RE 0

155 MC4CT54A MAXIMUM RATINGS* SymbolÎ alue Unit DC Supply oltage 0.5 to +.0 in DC Input oltage 0.5 to +.0 out DC Output oltage Outputs in 3 State 0.5 to +.0 igh or ow State 0.5 to IIK Input Diode Current 20 ma IOK Output Diode Current (OUT < ; OUT > ) ± 20 ma Iout DC Output Current, per Pin ± 25 ma ICC DC Supply Current, and Pi ± 5 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 Î T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit DC Supply oltage in DC Input oltage out DC Output oltage Outputs in 3 State Î igh or ow State TA Operating Temperature C Î Input Rise and Fall Time =5.0 ± / tr, tf Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit I Minimum igh evel 4.5 to 2.0 Î 2.0 Î Input oltage 5.5 I Maximum ow evel Input oltage 4.5 to O Minimum igh evel IO = 50µA Î Output oltage Î in = I or I IO = ma O Maximum ow evel IO = 50µA Output oltage in = I or I IO = ma Iin Maximum Input in = 5.5 or 0 to 5.5 ± 0.1 ± 1.0 µa eakage Current Î IOZ Maximum 3 State in = I or I 5.5 eakage Current out = or ± 0.25 ± 2.5 µa ICC Maximum uiescent in = or 5.5 Supply Current Î µa ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

156 MC4CT54A Î DC EECTRICA CARACTERISTICS T A = 40 to 5 C Min Typ Max Max Symbol Test Conditio Min Unit Î ICCT uiescent Supply Per Input: IN = Current Other Input: or Î ma IOPD Output eakage OUT = Current Î Î µa Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Min Typ Max Min Max Unit fmax Maximum Clock Frequency = 5.0 ± 0.5 C = 15pF 90 (50% Duty Cycle) Î C = 50pF Mz tp, Maximum Propagation Delay, Î = 5.0 ± 0.5 C = 15pF tp CP to C = 50pF Î tpz, Output Enable Time, Î = 5.0 ± 0.5 C = 15pF tpz OE to R = 1kΩ C = 50pF tpz, Output Disable Time, = 5.0 ± 0.5 C = 50pF tpz OE to Î R = 1kΩ tos, Output to Output Skew Î = 5.0 ± 0.5 C = 50pF tos (Note 1.) Î Cin Maximum Input Capacitance pf Cout Maximum Three State Output Î Capacitance, Output in igh Impedance State Î 9 pf 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 2.) 25 pf 1. guaranteed by design. tos = tpm tpn, tos = tpm tpn. 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC / (per flip flop). CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 2.0 ID Maximum ow evel Dynamic Input oltage 0. TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to 5 C Symbol Test Conditio Typ imit imit Unit tsu Minimum Setup Time, D to CP = 5.0 ± th Minimum old Time, CP to D = 5.0 ± tw Minimum Pulse Width, CP = 5.0 ± MOTOROA 150 ery igh Speed CMOS ogic C Data D203 Rev 2

157 MC4CT54A SWITCING WAEFORMS CP 1.5 tw 1/fmax tp tp 1.5 Figure 1. 3 O O OE 1.5 tpz tpz 1.5 tpz tpz 1.5 Figure 2. 3 O +0.3 O 0.3 IG IMPEDANCE IG IMPEDANCE D CP 1.5 tsu AID 1.5 th 3 3 D0 D1 2 3 EXPANDED OGIC DIAGRAM C D C D Figure 3. D2 4 C D 1 2 DEICE UNDER TEST TEST POINT OUTPUT C* D3 D4 5 6 C D C D D5 C D 14 5 * Includes all probe and jig capacitance Figure 4. D6 C D 13 6 TEST POINT D 9 C D 12 DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. CP OE 11 1 * Includes all probe and jig capacitance Figure 5. Test Circuit ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

158 SEMICONDUCTOR TECNICA DATA The MC4C595 is an advanced high speed bit shift register with an output storage register fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TT while maintaining CMOS low power dissipation. The MC4C595 contai an bit static shift register which feeds an bit storage register. Shift operation is accomplished on the positive going traition of the Shift Clock input (SCK). The output register is loaded with the contents of the shift register on the positive going traition of the Register Clock input (RCK). Since the RCK and SCK signals are independent, parallel outputs can be held stable during the shift operation. And, since the parallel outputs are 3 state, the C595 can be directly connected to an bit bus. This register can be used in serial to parallel conversion, data receivers, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to, allowing the interface of 5 systems to 3 systems. igh Speed: fmax = 15Mz (Typ) at = 5 ow Power Dissipation: ICC = 4µA (Max) at igh Noise Immunity: NI = NI = 2% Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 to 5.5 Operating Range ow Noise: OP = 1.0 (Max) Pin and Function Compatible with Other Standard ogic Families atchup Performance Exceeds 300mA ESD Performance: BM > 2000; Machine Model > 200 Chip Complexity: 32 FETs or 2 Equivalent Gates SERIA DATA INPUT SI 14 SIFT REGISTER OGIC DIAGRAM STORAGE REGISTER 15 A 1 B 2 C 3 D 4 E 5 F 6 G PARAE DATA OUTPUTS D SUFFIX 16 EAD SOIC PACKAGE CASE 51B 05 DT SUFFIX 16 EAD TSSOP PACKAGE CASE 94F 01 M SUFFIX 16 EAD SOIC EIAJ PACKAGE CASE ORDERING INFORMATION MC4CXXXD MC4CXXXDT MC4CXXXM PIN ASSIGNMENT B C D E F G SOIC TSSOP SOIC EIAJ A SI OE RCK SCK SCR S SCK SCR RCK S SERIA DATA OUTPUT OE 13 6/9 Motorola, Inc RE 1

159 MC4C595 Operation Reset (SCR) Serial Input (SI) Inputs Shift Clock (SCK) FUNCTION TABE Reg Clock (RCK) Output Enable (OE) Shift Register Contents Resulting Function Storage Register Contents Serial Output (S) Parallel Outputs (A ) Clear shift register X X,, U U Shift data into shift register D,, D SRA; SRN SRN+1 Registers remai unchanged Trafer shift register contents to storage register Storage register remai unachanged U SRG SR U X,, X U ** U ** X,, U SRNSTRN * SRN X X X,, * U * U Enable parallel outputs X X X X * ** * Enabled Force outputs into high X X X X * ** * Z impedance state SR = shift register contents D = data (, ) logic level = igh to ow * = depends on Reset and Shift Clock inputs STR = storage register contents U = remai unchanged = ow to igh ** = depends on Register Clock input MAXIMUM RATINGS* Symbol alue Unit DC Supply oltage 0.5 to +.0 Î in DC Input oltage 0.5 to +.0 Î out DC Output oltage 0.5 to I Î IK Input Diode Current 20 ma I Î OK Output Diode Current ± 20 ma I Î out DC Output Current, per Pin ± 25 ma I Î CC DC Supply Current, and Pi ± 50 ma P D Power Dissipation in Still Air, SOIC Packages 500 mw TSSOP Package 450 T stg Storage Temperature 65 to C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditio or conditio beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditio is not implied. Derating SOIC Packages: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol DC Supply oltage Min Max Unit in DC Input oltage out DC Output oltage 0 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = 3.3 ± / =5.0 ± ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

160 MC4C595 Î DC EECTRICA CARACTERISTICS TA = 40 to 5 C Symbol Test Conditio Î Min Typ Max Min Max Unit Î I Minimum igh evel Î Input oltage 3.0 to x 0.Î x 0.Î 5.5 Î I Maximum ow evel Input oltage to x x 0.3 O Minimum igh evel in = I or I Output oltage IO = 50µA in = I or I IO = 4mA IO = ma Î O Maximum ow evel Î Output oltage in = I or I IO = 50µA in = I or I IO = 4mA 3.0 IO = ma Î IOZ Three State Output in = I or I 5.5 Î Off State Current out = or ± 0.25 ± 2.50 Î µa Iin Maximum Input in = 5.5 or 0 to 5.5Î ± 0.1 ± 1.0 µa eakage Current Î ICC Maximum uiescent Î in = or µa Supply Current Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0 ) TA = 40 to 5 C Symbol Î Test Conditio Min Typ Max Min Max Unit fmax Maximum Clock Frequency Î = 3.3 ± 0.3 C = 15pF Î Mz (50% Duty Cycle) R = 1kΩ C = 50pF Î Î Î = 5.0 ± 0.5 C = 15pF 135 R = 1kΩ C = 50pF tp, Propagation Delay, = 3.3 ± 0.3 C = 15pF tp SCK to S Î C = 50pF Î = 5.0 ± 0.5 C = 15pF Î C = 50pF tp Propagation Delay, = 3.3 ± 0.3 C = 15pF SCR to S C = 50pF Î Î = 5.0 ± 0.5 C = 15pF C = 50pF tp, Propagation Delay, Î = 3.3 ± 0.3 C = 15pF tp RCK to A C = 50pF Î = 5.0 ± 0.5 C = 15pF C = 50pF tpz, Output Enable Time, = 3.3 ± 0.3 C = 15pF tpz OE to A Î R = 1kΩ C = 50pF Î = 5.0 ± 0.5 C = 15pF Î R = 1kΩ C = 50pF MOTOROA 154 ery igh Speed CMOS ogic C Data D203 Rev 2

161 MC4C595 Î AC EECTRICA CARACTERISTICS (Input tr = tf = 3.0 ) T A = 40 to 5 C Î Symbol Test Conditio Min Typ Max Min Max Unit tpz, Output Disable Time, = 3.3 ± 0.3 C = 50pF tpz OE to A Î R = 1kΩ Î = 5.0 ± 0.5 C = 50pF Î R = 1kΩ Cin Input Capacitance Î pf Cout Three State Output Capacitance (Output in igh Impedance State), A Î 6 10 Î 25 C, = 5.0 CPD Power Dissipation Capacitance (Note 1.) pf 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current coumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD fin + ICC. CPD is used to determine the no load dynamic power coumption; PD = CPD 2 fin + ICC. NOISE CARACTERISTICS (Input tr = tf = 3.0, C = 50pF, = 5.0) Symbol Characteristic Typ Max Unit OP uiet Output Maximum Dynamic O O uiet Output Minimum Dynamic O ID Minimum igh evel Dynamic Input oltage 3.5 ID Maximum ow evel Dynamic Input oltage 1.5 TIMING REUIREMENTS (Input tr = tf = 3.0) TA = 40 to TA = 25 C 5 C Symbol Typ imit imit Unit Î tsu Setup Time, SI to SCK Î Î tsu() Setup Time, SCK to RCK Î tsu() Setup Time, SCR to RCK Î th old Time, SI to SCK Î Î th() old Time, SCR to RCK trec Recovery Time, SCR to SCK Î Î tw Pulse Width, SCK or RCK Î Î tw() Pulse Width, SCR ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

162 MC4C595 SWITCING WAEFORMS tw SCK 50% tw SCR tp 50% S tp 1/fmax 50% tp S SCK 50% trec 50% Figure 1. Figure 2. RCK A 50% tp 50% tp OE A A 50% tpz 50% tpz 50% tpz tpz IG IMPEDANCE O +0.3 O 0.3 IG IMPEDANCE Figure 3. Figure 4. SCR 50% AID SI 50% tsu th SCK or RCK 50% SCK RCK 50% tsu() 50% tw Figure 5. Figure 6. TEST CIRCUITS TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C* DEICE UNDER TEST OUTPUT 1 kω C* CONNECT TO WEN TESTING tpz AND tpz. CONNECT TO WEN TESTING tpz AND tpz. * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure. Figure. MOTOROA 156 ery igh Speed CMOS ogic C Data D203 Rev 2

163 MC4C595 EXPANDED OGIC DIAGRAM OE 13 RCK 12 SI 14 D D 15 A SRA STRA R D D 1 B SRB STRB R D D 2 C SRC STRC R D D 3 D SRD R D STRD D 4 E PARAE DATA OUTPUTS SRE STRE R D D 5 F SRF STRF R D D 6 G SRG STRG R SCK 11 D SR D STR R SCR 10 9 S ery igh Speed CMOS ogic C Data D203 Rev 2 15 MOTOROA

164 MC4C595 TIMING DIAGRAM SCK SI SCR RCK OE A B C D E F G S NOTE: output is in a high impedance state. INPUT EUIAENT CIRCUIT INPUT MOTOROA 15 ery igh Speed CMOS ogic C Data D203 Rev 2

165 SEMICONDUCTOR TECNICA DATA igh Performance Silicon Gate CMOS The MC4C4051, MC4C4052 and MC4C4053 utilize silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/ demultiplexers control analog voltages that may vary across the complete power supply range (from to EE). The C4051, C4052 and C4053 are identical in pinout to the high speed C4051A, C4052A and C4053A, and the metal gate MC14051B, MC14052B and MC14053B. The Channel Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by mea of an analog switch, to the Common Output/Input. When the Enable pin is IG, all analog switches are turned off. The Channel Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with STT outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal gate CMOS analog switches. For a multiplexer/demultiplexer with channel select latches, see C4351. Fast Switching and Propagation Speeds ow Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range ( EE) = 2.0 to 12.0 Digital (Control) Power Supply Range ( ) = 2.0 to 6.0 Improved inearity and ower ON Resistance Than Metal Gate Counterparts ow Noise In Compliance With the Requirements of JEDEC Standard No. A Chip Complexity: C FETs or 46 Equivalent Gates C FETs or 42 Equivalent Gates C FETs or 39 Equivalent Gates OGIC DIAGRAM MC4C4051 Single Pole, Position Plus Common Off X0 13 X1 14 X2 15 ANAOG INPUTS/ X3 12 OUTPUTS X4 1 X5 5 X6 2 X 4 A 11 CANNE SEECT B 10 INPUTS C 9 ENABE 6 PIN 16 = PIN = EE PIN = MUTIPEXER/ DEMUTIPEXER 3 X COMMON OUTPUT/ INPUT Pinout: MC4C4051 (Top iew) X2 X1 X0 X3 A B C X4 X6 X X X5 Enable EE This document contai information on a new product. Specificatio and information herein are subject to change without notice. FUNCTION TABE MC4C4051 Control Inputs Select Enable C B A D SUFFIX 16 EAD SOIC PACKAGE CASE 51B 05 DT SUFFIX 16 EAD TSSOP PACKAGE CASE 94F 01 ORDERING INFORMATION MC4CXXXXD MC4CXXXXDT X X X SOIC TSSOP ON Channels X0 X1 X2 X3 X4 X5 X6 X NONE X = Don t Care 12/9 Motorola, Inc RE 0

166 MC4C4051 MC4C4052 MC4C4053 ANAOG INPUTS/OUTPUTS CANNE-SEECT INPUTS OGIC DIAGRAM MC4C4052 Double Pole, 4 Position Plus Common Off X0 12 X1 14 X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4 A 10 B 9 ENABE 6 X SWITC Y SWITC 13 3 X Y PIN 16 = PIN = EE PIN = COMMON OUTPUTS/INPUTS FUNCTION TABE MC4C4052 Enable Control Inputs X = Don t Care Select B A X X ON Channels Y0 Y1 Y2 Y3 NONE Pinout: MC4C4052 (Top iew) X0 X1 X2 X3 X2 X1 X X0 X3 A B Y0 Y2 Y Y3 Y1 Enable EE FUNCTION TABE MC4C4053 OGIC DIAGRAM MC4C4053 Triple Single Pole, Double Position Plus Common Off ANAOG INPUTS/OUTPUTS X0 12 X1 13 Y0 2 Y1 1 Z0 5 Z1 3 A 11 CANNE-SEECT B 10 INPUTS C 9 ENABE 6 X SWITC Y SWITC Z SWITC 14 X PIN 16 = PIN = EE PIN = NOTE: This device allows independent control of each switch. Channel Select Input A controls the X Switch, Input B controls the Y Switch and Input C controls the Z Switch 15 4 Y Z COMMON OUTPUTS/INPUTS Enable Control Inputs X = Don t Care Select C B A X X X Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 ON Channels Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE Pinout: MC4C4053 (Top iew) X0 X1 X0 X1 X0 X1 X0 X1 Y X X1 X0 A B C Y1 Y0 Z1 Z Z0 Enable EE MOTOROA 160 ery igh Speed CMOS ogic C Data D203 Rev 2

167 MC4C4051 MC4C4052 MC4C4053 MAXIMUM RATINGS* SymbolÎ alue Unit Positive DC Supply oltage (Referenced to ) 0.5 to +.0 (Referenced to EE) 0.5 to EE Negative DC Supply oltage (Referenced to ).0 to IS Analog Input oltage EE 0.5 to in Digital Input oltage (Referenced to ) 0.5 to I DC Current, Into or Out of Any Pin ± 25 ma Î P D Power Dissipation in Still Air, SOIC Package 500 mw TSSOP Package 450 T stg Storage Temperature Range 65 to C T ead Temperature, 1 mm from Case for 10 Seconds 260 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. Derating SOIC Package: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit Positive DC Supply oltage (Referenced to ) (Referenced to EE) EE Negative DC Supply oltage, Output (Referenced to 6.0 Î ) Î IS Analog Input oltage EE Î in Digital Input oltage (Referenced to ) IO* Static or Dynamic oltage Across Switch Î 1.2 Î TA Operating Temperature Range, All Package Types C tr, tf Input Rise/Fall Time = Î (Channel Select or Enable Inputs) = = = 6.0 * For voltage drops across switch greater than 1.2 (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

168 MC4C4051 MC4C4052 MC4C4053 DC CARACTERISTICS Digital Section (oltages Referenced to ) EE =, Except Where Noted Symbol Condition I I Iin Minimum igh evel Input oltage, Channel Select or Enable Inputs Maximum ow evel Input oltage, Channel Select or Enable Inputs Maximum Input eakage Current, Channel Select or Enable Inputs Ron = Per Spec Ron = Per Spec in = or, EE = 6.0 Guaranteed imit 55 to 25 C 5 C 125 C Unit ± 0.1 ± 1.0 ± 1.0 µa ICC Maximum uiescent Supply Current (per Package) Channel Select, Enable and IS = or ; EE = IO = 0 EE = µa DC EECTRICA CARACTERISTICS Analog Section Guaranteed imit Symbol Î Î Test Conditio CC EE 55 to 25 C 5 C 125 C Unit RonÎ Maximum ON Resistance Î in = I or I TBD TBD TBD Ω IS = to EE IS 2.0 ma (Figures 1, 2) Î in = I or I TBD TBD TBD IS = or EE (Endpoints) IS 2.0 ma (Figures 1, 2) Î Ron Î Maximum Difference in ON Î in = I or I TBD TBD TBD Ω Resistance Between Any Two IS = 1/2 ( EE) Channels in the Same Package Î IS 2.0 ma Ioff Ion Maximum Off Channel eakage Current, Any One Channel Maximum Off Channel C4051 eakage Current, C4052 Common Channel C4053 Maximum On Channel C4051 eakage Current, C4052 Channel to Channel C4053 in = I or I; IO = EE; Switch Off (Figure 3) in = I or I; IO = EE; Switch Off (Figure 4) in = I or I; Switch to Switch = EE; (Figure 5) µa µa MOTOROA 162 ery igh Speed CMOS ogic C Data D203 Rev 2

169 MC4C4051 MC4C4052 MC4C4053 AC CARACTERISTICS (C = 50 pf, Input tr = tf = 6 ) Symbol tp, tp tp, tp tpz, tpz tpz, tpz Maximum Propagation Delay, Channel Select to Analog Output (Figure 9) Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) Maximum Propagation Delay, Enable to Analog Output (Figure 11) Maximum Propagation Delay, Enable to Analog Output (Figure 11) Guaranteed imit 55 to 25 C 5 C 125 C Unit Cin Maximum Input Capacitance, Channel Select or Enable Inputs pf CI/O Maximum Capacitance Analog I/O pf (All Switches Off) Common O/I: C4051 C4052 C TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Feedthrough C, = 5.0, EE = 0 CPD Power Dissipation Capacitance (Figure 13)* C4051 C4052 C4053 * Used to determine the no load dynamic power coumption: PD = CPD 2 f + ICC pf ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

170 MC4C4051 MC4C4052 MC4C4053 ADDITIONA APPICATION CARACTERISTICS ( = 0 ) Symbol Condition BW Maximum On Channel Bandwidth or Minimum i Frequency Respoe (Figure 6) Off Channel Feedthrough Isolation (Figure ) Feedthrough Noise. Channel Select Input to Common I/O (Figure ) Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to C4051) TD Total armonic Distortion (Figure 14) * imits not tested. Determined by design and verified by qualification. fin = 1Mz Sine Wave; Adjust fin oltage to Obtain 0dBm at OS; Increase fin Frequency Until db Meter Reads 3dB; R = 50Ω, C = 10pF fin = Sine Wave; Adjust fin oltage to Obtain 0dBm at IS f in = 10kz, R = 600Ω, C = 50pF fin = 1.0Mz, R = 50Ω, C = 10pF in 1Mz Square Wave (tr = tf = 6); Adjust R at Setup so that IS = 0A; Enable = R = 600Ω, C = 50pF R = 10kΩ, C = 10pF fin = Sine Wave; Adjust fin oltage to Obtain 0dBm at IS f in = 10kz, R = 600Ω, C = 50pF fin = 1.0Mz, R = 50Ω, C = 10pF fin = 1kz, R = 10kΩ, C = 50pF TD = TDmeasured TDsource IS = 4.0PP sine wave IS =.0PP sine wave IS = 11.0PP sine wave EE imit* 25 C Unit Mz db mpp db % Ron, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C R on, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1a. Typical On Resistance, EE = IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1b. Typical On Resistance, EE = 3.0 MOTOROA 164 ery igh Speed CMOS ogic C Data D203 Rev 2

171 MC4C4051 MC4C4052 MC4C4053 Ron, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C R on, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1c. Typical On Resistance, EE = 4.5 IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1d. Typical On Resistance, EE = Ron, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C Ron, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1e. Typical On Resistance, EE = 9.0 IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1f. Typical On Resistance, EE = 12.0 ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

172 MC4C4051 MC4C4052 MC4C4053 POTTER PROGRAMMABE POWER SUPPY MINI COMPUTER DC ANAYZER + DEICE UNDER TEST ANAOG IN COMMON OUT EE Figure 2. On Resistance Test Set Up MOTOROA 166 ery igh Speed CMOS ogic C Data D203 Rev 2

173 MC4C4051 MC4C4052 MC4C4053 EE A NC OFF OFF 16 COMMON O/I EE ANAOG I/O OFF OFF 16 COMMON O/I I 6 I 6 EE EE Figure 3. Maximum Off Channel eakage Current, Any One Channel, Test Set Up Figure 4. Maximum Off Channel eakage Current, Common Channel, Test Set Up EE A ANAOG I/O ON OFF 16 COMMON O/I N/C fin 0.1µF ON 16 OS C* db METER R I 6 6 EE EE *Includes all probe and jig capacitance Figure 5. Maximum On Channel eakage Current, Channel to Channel, Test Set Up Figure 6. Maximum On Channel Bandwidth, Test Set Up fin 0.1µF IS R OFF 16 OS C* db METER R R ANAOG I/O R ON/OFF OFF/ON 16 COMMON O/I R C* TEST POINT I or I EE 6 CANNE SEECT in 1 Mz tr = tf = 6 EE 6 11 CANNE SEECT *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure. Off Channel Feedthrough Isolation, Test Set Up Figure. Feedthrough Noise, Channel Select to Common Out, Test Set Up ery igh Speed CMOS ogic C Data D203 Rev 2 16 MOTOROA

174 MC4C4051 MC4C4052 MC4C4053 CANNE SEECT 50% ANAOG I/O ON/OFF OFF/ON 16 COMMON O/I C* TEST POINT tp tp ANAOG OUT 50% 6 CANNE SEECT *Includes all probe and jig capacitance Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set Up Channel Select to Analog Out 16 ANAOG IN 50% ANAOG I/O ON COMMON O/I C* TEST POINT tp ANAOG OUT 50% tp 6 *Includes all probe and jig capacitance Figure 10a. Propagation Delays, Analog In to Analog Out Figure 10b. Propagation Delay, Test Set Up Analog In to Analog Out tf ENABE ANAOG OUT tpz 50% tr tpz 90% 50% 10% 10% IG IMPEDANCE O POSITION 1 WEN TESTING tpz AND tpz POSITION 2 WEN TESTING tpz AND tpz ANAOG I/O ON/OFF 16 1kΩ C* TEST POINT ANAOG OUT tpz 50% tpz 90% O IG IMPEDANCE ENABE 6 Figure 11a. Propagation Delays, Enable to Analog Out Figure 11b. Propagation Delay, Test Set Up Enable to Analog Out MOTOROA 16 ery igh Speed CMOS ogic C Data D203 Rev 2

175 MC4C4051 MC4C4052 MC4C4053 fin 0.1µF R IS ON 16 OS ANAOG I/O ON/OFF OFF/ON 16 A COMMON O/I NC OFF EE R 6 R C* R C* EE 6 11 CANNE SEECT *Includes all probe and jig capacitance Figure 12. Crosstalk Between Any Two Switches, Test Set Up Figure 13. Power Dissipation Capacitance, Test Set Up IS OS 0 10 FUNDAMENTA FREUENCY fin 0.1µF ON 16 R C* TO DISTORTION METER db DEICE SOURCE EE *Includes all probe and jig capacitance FREUENCY (kz) Figure 14a. Total armonic Distortion, Test Set Up Figure 14b. Plot, armonic Distortion APPICATIONS INFORMATION The Channel Select and Enable control pi should be at or logic levels. being recognized as a logic high and being recognized as a logic low. In this example: = +5 = logic high = 0 = logic low The maximum analog voltage swings are determined by the supply voltages and EE. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below EE. In this example, the difference between and EE is ten volts. Therefore, using the configuration of Figure 15, a maximum analog signal of ten volts peak to peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). owever, tying unused analog inputs and outputs to or through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only cotraints on the power supplies are that: = 2 to 6 volts EE = 0 to 6 volts EE = 2 to 12 volts and EE When voltage traients above and/or below EE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping. ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

176 MC4C4051 MC4C4052 MC4C ANAOG SIGNA ON 16 ANAOG SIGNA +5 5 Dx Dx 16 ON/OFF Dx Dx EE EE TO EXTERNA CMOS CIRCUITRY 0 to 5 DIGITA SIGNAS 5 EE Figure 15. Application Example Figure 16. External Germanium or Schottky Clipping Diodes +5 EE EE ANAOG SIGNA 6 ON/OFF ANAOG SIGNA +5 * R R R +5 EE STT/NMOS CIRCUITRY * 2K R 10K EE CT BUFFER a. Using Pull Up Resistors b. Using CT Interface +5 EE ANAOG SIGNA Figure 1. Interfacing STT/NMOS to CMOS Inputs 6 ON/OFF ANAOG SIGNA EE STT/NMOS CIRCUITRY A 11 EE SIFTER 13 X0 14 X1 B 10 EE SIFTER 15 X2 12 X3 C 9 EE SIFTER 1 X4 5 X5 ENABE 6 EE SIFTER 2 X6 4 X Figure 1. Function Diagram, C X MOTOROA 10 ery igh Speed CMOS ogic C Data D203 Rev 2

177 MC4C4051 MC4C4052 MC4C4053 A 10 EE SIFTER 12 X0 14 X1 B 9 EE SIFTER 15 X2 11 X3 13 X ENABE 6 EE SIFTER 1 Y0 5 Y1 2 Y2 4 Y3 3 Y Figure 19. Function Diagram, C4052 A 11 EE SIFTER 13 X1 12 X0 14 X B 10 EE SIFTER 1 Y1 2 Y0 15 Y C 9 EE SIFTER 3 Z1 5 Z0 4 Z ENABE 6 EE SIFTER Figure 20. Function Diagram, C4053 ery igh Speed CMOS ogic C Data D203 Rev 2 11 MOTOROA

178 SEMICONDUCTOR TECNICA DATA igh Performance Silicon Gate CMOS The MC4C4066 utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power supply range (from to ). The C4066 is identical in pinout to the metal gate CMOS MC14066 and the high speed CMOS C4066A. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with STT outputs. For analog switches with voltage level tralators, see the C4316. Fast Switching and Propagation Speeds igh ON/OFF Output oltage Ratio ow Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power Supply oltage Range ( ) = 2.0 to 12.0 olts Analog Input oltage Range ( ) = 2.0 to 12.0 olts Improved inearity and ower ON Resistance over Input oltage than the MC14016 or MC14066 ow Noise Chip Complexity: 44 FETs or 11 Equivalent Gates XA OGIC DIAGRAM 1 2 YA D SUFFIX 14 EAD SOIC PACKAGE CASE 51A 03 DT SUFFIX 14 EAD TSSOP PACKAGE CASE 94G 01 ORDERING INFORMATION MC4CXXXXD MC4CXXXXDT PIN ASSIGNMENT XA YA YB XB B ON/OFF CONTRO C ON/OFF CONTRO SOIC TSSOP A ON/OFF CONTRO D ON/OFF CONTRO XD YD YC XC A ON/OFF CONTRO 13 FUNCTION TABE XB 4 3 YB On/Off Control Input State of Analog Switch B ON/OFF CONTRO 5 ANAOG OUTPUTS/INPUTS Off On XC 9 YC C ON/OFF CONTRO 6 XD YD D ON/OFF CONTRO 12 ANAOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = PIN = This document contai information on a new product. Specificatio and information herein are subject to change without notice. 12/9 Motorola, Inc RE 0

179 MC4C4066 MAXIMUM RATINGS* SymbolÎ alue Unit Positive DC Supply oltage (Referenced to ) 0.5 to IS Analog Input oltage (Referenced to ) 0.5 to in Digital Input oltage (Referenced to ) 0.5 to I DC Current Into or Out of Any Pin ± 25 ma P D Power Dissipation in Still Air, SOIC Package 500 mw TSSOP Package 450 Tstg Storage Temperature 65 to C T ead Temperature, 1 mm from Case for 10 Seconds 260 C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. Derating SOIC Package: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. I/O pi must be connected to a properly terminated line or bus. RECOMMENDED OPERATING CONDITIONS Symbol Positive DC Supply oltage (Referenced to ) Min Max Unit IS Analog Input oltage (Referenced to ) in Digital Input oltage (Referenced to ) IO* Static or Dynamic oltage Across Switch 1.2 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time, ON/OFF Control Î Inputs (Figure 10) = Î = = Î = Î = * For voltage drops across the switch greater than 1.2 (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC EECTRICA CARACTERISTIC Digital Section (oltages Referenced to ) Guaranteed imit 55 to Symbol Test Conditio 25 C 5 C 125 C Unit I Minimum igh evel oltage Î Î Ron = Per Spec ON/OFF Control Inputs I Î Maximum ow evel oltage Î Ron = Per Spec ON/OFF Control Inputs Î Î Iin Maximum Input eakage Current in = or 12.0 ± 0.1 ± 1.0 ± 1.0 ON/OFF Control Inputs µa ICC Î Maximum uiescent Supply Î in = or 6.0 Î Current (per Package) IO = µa ery igh Speed CMOS ogic C Data D203 Rev 2 13 MOTOROA

180 MC4C4066 DC EECTRICA CARACTERISTICS Analog Section (oltages Referenced to ) Î Guaranteed imit Î 55 to Symbol Î Î Test Conditio 25 C 5 C 125 C Unit Ron Maximum ON Resistance Î Î in = I 2.0 Ω IS = to 3.0 IS 2.0 ma (Figures 1, 2) Î Î in = I 2.0 IS = or (Endpoints) 3.0 IS 2.0 ma (Figures 1, 2) Ron Î Maximum Difference in ON Î in = I 2.0 Ω Resistance Between Any Two IS = 1/2 ( ) Channels in the Same Package Î IS 2.0 ma Ioff Maximum Off Channel eakage Î Î in = I 12.0 Current, Any One Channel IO = or Switch Off (Figure 3) µa Ion Î Maximum On Channel eakageî in = I µa Current, Any One Channel IS = or (Figure 4) At supply voltage () approaching 3 the analog switch on resistance becomes extremely non linear. Therefore, for low voltage operation, it is recommended that these devices only be used to control digital signals. AC EECTRICA CARACTERISTICS (C = 50 pf, ON/OFF Control Inputs: tr = tf = 6 ) Guaranteed imit 55 to Symbol 25 C 5 C 125 C Unit Î tp, Maximum Propagation Delay, Analog Input to Analog Output tp Î (Figures and 9) tpz, Î Maximum Propagation Delay, ON/OFF Control to Analog Output tpz (Figures 10 and 11) Î tpz, Maximum Propagation Delay, ON/OFF Control to Analog Output tpz (Figures 10 and 1 1) C Î Maximum Capacitance ON/OFF Control Input pf Î Control Input = Analog I/O Feedthrough C, = 5.0 CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pf * Used to determine the no load dynamic power coumption: PD = CPD 2 f + ICC. MOTOROA 14 ery igh Speed CMOS ogic C Data D203 Rev 2

181 MC4C4066 ADDITIONA APPICATION CARACTERISTICS (oltages Referenced to Unless Noted) Î imit* 25 C Symbol Test Conditio Î 4C Î Unit Î BW Maximum On Channel Bandwidth or fin = 1 Mz Sine Wave Mz Minimum Frequency Respoe Adjust fin oltage to Obtain 0 dbm at OS Î (Figure 5) Increase fin Frequency Until db Meter Reads 3 db R = 50 Ω, C = 10 pf Î Off Channel Feedthrough Isolation fin Î (Figure 6) Sine Wave db Adjust fin oltage to Obtain 0 dbm at IS fin = 10 kz, R = 600 Ω, C = 50 pf fin = 1.0 Mz, R = 50 Ω, C = 10 pf Feedthrough Noise, Control to in 1 Mz Square Wave (tr = tf = 6 ) Î Switch Adjust R at Setup so that IS = 0 A m PP (Figure ) R = 600 Ω, C = 50 pf R = 10 kω, C = 10 pf Crosstalk Between Any Two Switches fin Sine Wave db (Figure 12) Adjust fin oltage to Obtain 0 dbm at IS fin = 10 kz, R = 600 Ω, C = 50 pf fin = 1.0 Mz, R = 50 Ω, C = 10 pf Î TD Total armonic Distortion fin = 1 kz, R = 10 kω, C = 50 pf % Î (Figure 14) TD = TDMeasured TDSource IS = 4.0 PP sine wave IS =.0 PP sine wave IS = 11.0 PP sine wave * Guaranteed limits not tested. Determined by design and verified by qualification. ery igh Speed CMOS ogic C Data D203 Rev 2 15 MOTOROA

182 MC4C4066 TBD TBD Figure 1a. Typical On Resistance, = 2.0 Figure 1b. Typical On Resistance, = 4.5 TBD TBD Figure 1c. Typical On Resistance, = 6.0 Figure 1d. Typical On Resistance, = 9.0 POTTER TBD PROGRAMMABE POWER SUPPY MINI COMPUTER DC ANAYZER + DEICE UNDER TEST ANAOG IN COMMON OUT Figure 1e. Typical On Resistance, = 12 Figure 2. On Resistance Test Set Up MOTOROA 16 ery igh Speed CMOS ogic C Data D203 Rev 2

183 MC4C A OFF A ON N/C SEECTED CONTRO INPUT I SEECTED CONTRO INPUT I Figure 3. Maximum Off Channel eakage Current, Any One Channel, Test Set Up Figure 4. Maximum On Channel eakage Current, Test Set Up OS IS OS fin 0.1µF ON C* db METER fin 0.1µF R OFF C* db METER SEECTED CONTRO INPUT SEECTED CONTRO INPUT *Includes all probe and jig capacitance. Figure 5. Maximum On Channel Bandwidth Test Set Up *Includes all probe and jig capacitance. Figure 6. Off Channel Feedthrough Isolation, Test Set Up /2 /2 14 R OFF/ON R IS OS C* in 1 Mz tr = tf = 6 CONTRO SEECTED CONTRO INPUT ANAOG IN tp ANAOG OUT 50% 50% tp *Includes all probe and jig capacitance. Figure. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set Up Figure. Propagation Delays, Analog In to Analog Out ery igh Speed CMOS ogic C Data D203 Rev 2 1 MOTOROA

184 MC4C4066 ANAOG IN ON Figure 9. Propagation Delay Test Set Up 14 *Includes all probe and jig capacitance. SEECTED CONTRO INPUT ANAOG OUT C* TEST POINT CONTRO ANAOG OUT 90% 50% 10% tr 50% 50% tpz tpz tf tpz tpz 10% 90% Figure 10. Propagation Delay, ON/OFF Control to Analog Out IG IMPEDANCE O O IG IMPEDANCE POSITION POSITION 1 2 WEN TESTING tpz AND tpz WEN TESTING tpz AND tpz ON/OFF SEECTED CONTRO INPUT 14 1 kω C* TEST POINT R fin 0.1 µf OR IS R ON OFF SEECTED CONTRO INPUT 14 R /2 OS C* R C* /2 *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set Up /2 *Includes all probe and jig capacitance. Figure 12. Crosstalk Between Any Two Switches, Test Set Up 14 A IS OS N/C OFF/ON N/C fin 0.1 µf ON R C* TO DISTORTION METER ON/OFF CONTRO SEECTED CONTRO INPUT SEECTED CONTRO INPUT /2 *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set Up Figure 14. Total armonic Distortion, Test Set Up MOTOROA 1 ery igh Speed CMOS ogic C Data D203 Rev 2

185 MC4C4066 dbm FUNDAMENTA FREUENCY DEICE SOURCE FREUENCY (kz) Figure 15. Plot, armonic Distortion 3.0 APPICATION INFORMATION The ON/OFF Control pi should be at or logic levels, being recognized as logic high and being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). owever, it is advisable to tie unused analog inputs and outputs to or through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pi. The maximum analog voltage swings are determined by the supply voltages and. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below. In the example below, the difference between and is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak to peak can be controlled. When voltage traients above and/or below are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 1. These diodes should be small signal, fast turn on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOsorbs (Motorola high current surge protectors). MOsorbs are fast turn on devices ideally suited for precise DC protection with no inherent wear out mechanism. = ANAOG I/O ON 14 ANAOG O/I Dx Dx ON 16 Dx Dx SEECTED CONTRO INPUT OTER CONTRO INPUTS ( OR ) SEECTED CONTRO INPUT OTER CONTRO INPUTS ( OR ) Figure Application Figure 1. Traient Suppressor Application ery igh Speed CMOS ogic C Data D203 Rev 2 19 MOTOROA

186 MC4C ANAOG SIGNAS 14 ANAOG SIGNAS ANAOG SIGNAS 14 ANAOG SIGNAS STT/ NMOS R* R* R* R* 5 C4066 STT/ NMOS CT BUFFER 5 C CONTRO INPUTS 6 14 CONTRO INPUTS R* = 2 TO 10 kω a. Using Pull-Up Resistors b. Using CT Buffer Figure 1. STT/NMOS to CMOS Interface DD = 5 = 5 TO ANAOG 14 SIGNAS MC C4066 CONTRO INPUTS ANAOG SIGNAS Figure 19. TT/NMOS to CMOS evel Converter Analog Signal Peak to Peak Greater than 5 (Also see C4316) CANNE 4 1 OF 4 SWITCES CANNE 3 CANNE 2 1 OF 4 SWITCES 1 OF 4 SWITCES COMMON I/O CANNE 1 1 OF 4 SWITCES INPUT 1 OF 4 SWITCES + F356 OR EUIAENT OUTPUT 0.01 µf CONTRO INPUTS Figure Input Multiplexer Figure 21. Sample/old Amplifier MOTOROA 10 ery igh Speed CMOS ogic C Data D203 Rev 2

187 SEMICONDUCTOR TECNICA DATA igh Performance Silicon Gate CMOS The MC4C4316 utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full analog power supply range (from to EE). The C4316 is similar in function to the C4066, the metal gate CMOS MC14016 and MC14066, and to the igh Speed CMOS C4066A. Each device has four independent switches. The device control and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with STT outputs. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal gate CMOS analog switches. ogic level tralators are provided so that the On/Off Control and Enable logic level voltages need only be and, while the switch is passing signals ranging between and EE. When the Enable pin (active low) is high, all four analog switches are turned off. ogic evel Tralator for On/Off Control and Enable Inputs Fast Switching and Propagation Speeds igh ON/OFF Output oltage Ratio Diode Protection on All Inputs/Outputs Analog Power Supply oltage Range ( EE) = 2.0 to 12.0 olts Digital (Control) Power Supply oltage Range ( ) = 2.0 to 6.0 olts, Independent of EE Improved inearity of ON Resistance Chip Complexity: 66 FETs or 16.5 Equivalent Gates XA 1 A ON/OFF CONTRO 15 XB B ON/OFF CONTRO XC 10 C ON/OFF CONTRO 6 XD 13 D ON/OFF CONTRO 14 ENABE 4 5 OGIC DIAGRAM EE TRANSATOR EE TRANSATOR EE TRANSATOR EE TRANSATOR ANAOG SWITC ANAOG SWITC ANAOG SWITC ANAOG SWITC 2 Y A 3 Y B 11 Y C 12 Y D ANAOG OUTPUTS/INPUTS PIN 16 = PIN = PIN 9 = EE EE D SUFFIX 16 EAD SOIC PACKAGE CASE 51B 05 DT SUFFIX 16 EAD TSSOP PACKAGE CASE 94F 01 ORDERING INFORMATION MC4CXXXXD MC4CXXXXDT PIN ASSIGNMENT XA YA YB XB B ON/OFF CONTRO C ON/OFF CONTRO ENABE FUNCTION TABE 9 SOIC TSSOP A ON/OFF CONTRO D ON/OFF CONTRO XD YD YC XC EE Inputs State of On/Off Analog Enable Control Switch On Off X Off X = don t care ANAOG INPUTS/OUTPUTS = XA, XB, XC, XD This document contai information on a new product. Specificatio and information herein are subject to change without notice. 12/9 Motorola, Inc RE 0

188 MC4C4316 MAXIMUM RATINGS* SymbolÎ alue Unit Positive DC Supply oltage (Ref. to ) 0.5 to +.0 (Ref. to EE) 0.5 to EE Negative DC Supply oltage (Ref. to ).0 to IS Analog Input oltage EE 0.5 to in DC Input oltage (Ref. to ) 0.5 to I Î DC Current Into or Out of Any Pin ± 25 ma P D Power Dissipation in Still Air SOIC Package 500 mw TSSOP Package 450 T stg Storage Temperature 65 to C T ead Temperature, 1 mm from Case for 10 Seconds 260 C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. Derating SOIC Package: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. I/O pi must be connected to a properly terminated line or bus. RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit Positive DC Supply oltage (Ref. to ) EE Negative DC Supply oltage (Ref. to ) 6.0 IS Analog Input oltage EE in Digital Input oltage (Ref. to ) IO* Static or Dynamic oltage Across Switch 1.2 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time = Î (Control or Enable Inputs) = (Figure 10) = = 6.0 * For voltage drops across the switch greater than 1.2 (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC EECTRICA CARACTERISTICS Digital Section (oltages Referenced to ) EE = Except Where Noted Î Guaranteed imit Î 55 to Symbol Î Î Test Conditio 25 C 5 C 125 C Unit I Î Minimum igh evel oltage, Î Ron = Per Spec Control or Enable Inputs I Î Maximum ow evel oltage, Î Ron = Per Spec Control or Enable Inputs Î Iin Maximum Input eakage in = or 6.0 Current, Control or Enable Î EE = 6.0 ± 0.1 ± 1.0 ± 1.0 µa Inputs Î ICC Maximum uiescent Supply Î Î in = or µa Current (per Package) IO = 0 EE = 6.0 EE = MOTOROA 12 ery igh Speed CMOS ogic C Data D203 Rev 2

189 MC4C4316 DC EECTRICA CARACTERISTICS Analog Section (oltages Referenced to EE) Î Guaranteed imit Î Symbol Î Î Test Conditio EE 55 to 25 C 5 C 125 C Unit RonÎ Maximum ON Resistance Î in = I 2.0* 0.0 Ω IS = to EE TBD TBD TBD IS Î 2.0 ma (Figures 1, 2) Î Î in = I Î IS = or EE (Endpoints) TBD TBD TBD IS 2.0 ma (Figures 1, 2) Î Î Ron Maximum Difference in ON in = I Ω Î Resistance Between Any TwoÎ IS = 1/2 ( EE) TBD TBD TBD Channels in the Same Package IS 2.0 ma Î Î Ioff Î Maximum Off Channel eakage Î in = I 6.0 Current, Any One Channel IO = or EE Î Î Switch Off (Figure 3) µa Î Î I on Maximum On Channel eakage Î in = I Î Current, Any One Channel Î IS = or EE µa (Figure 4) * At supply voltage ( EE) approaching 2 the analog switch on resistance becomes extremely non linear. Therefore, for low voltage operation, it is recommended that these devices only be used to control digital signals. AC EECTRICA CARACTERISTICS (C = 50 pf, Control or Enable tr = tf = 6, EE = ) Î Guaranteed imit Î 55 to Symbol 25 C 5 C 125 C Unit Î tp, Maximum Propagation Delay, Analog Input to Analog Output tp Î (Figures and 9) 3.0 TBD TBD tpz, Î Maximum Propagation Delay, Control or Enable to Analog Output tpz Î (Figures 10 and 11) 3.0 TBD TBD tpz, Î Maximum Propagation Delay, Control or Enable to Analog Output tpz Î (Figures 10 and 11) 3.0 TBD TBD C Î Maximum Capacitance ON/OFF Control Î and Enable Inputs pf Î Control Input = Analog I/O Î Feedthrough C, = 5.0 CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pf * Used to determine the no load dynamic power coumption: PD = CPD 2 f + ICC. ery igh Speed CMOS ogic C Data D203 Rev 2 13 MOTOROA

190 MC4C4316 ADDITIONA APPICATION CARACTERISTICS ( = 0 ) Î EE imit* Symbol Test Conditio 25 C Unit BW Maximum On Channel Bandwidth or fin = 1 Mz Sine Wave Mz Minimum Frequency Respoe Adjust fin oltage to Obtain 0 dbm at OS (Figure 5) Increase fin Frequency Until db Meter Reads 3 db R = 50 Ω, C = 10 pf Off Channel Feedthrough Isolation fin Sine Wave db (Figure 6) Adjust fin oltage to Obtain 0 dbm at IS Î fin = 10 kz, R = 600 Ω, C = 50 pf fin = 1.0 Mz, R = 50 Ω, C = 10 pf Î Feedthrough Noise, Control to in Î Switch 1 Mz Square Wave (tr = tf = 6 ) mpp Adjust R at Setup so that IS = 0 A Î (Figure ) R = 600 Ω, C = 50 pf R = 10 kω, C = 10 pf Crosstalk Between Any Two fin Sine Wave Î Î Switches Adjust fin oltage to Obtain 0 dbm at IS db (Figure 12) fin = 10 kz, R = 600 Ω, C = 50 pf fin = 1.0 Mz, R = 50 Ω, C = 10 pf TD Total armonic Distortion fin = 1 kz, R = 10 kω, C = 50 pf % (Figure 14) TD = TDMeasured TDSource IS = 4.0 PP sine wave Î IS =.0 PP sine wave * imits not tested. Determined by design and verified by qualification. IS = 11.0 PP sine wave TBD TBD Figure 1a. Typical On Resistance, EE = 2.0 Figure 1b. Typical On Resistance, EE = 3.0 MOTOROA 14 ery igh Speed CMOS ogic C Data D203 Rev 2

191 MC4C4316 TBD TBD Figure 1c. Typical On Resistance, EE = 4.5 Figure 1d. Typical On Resistance, EE = 6.0 TBD TBD Figure 1e. Typical On Resistance, EE = 9.0 Figure 1e. Typical On Resistance, EE = 12.0 POTTER PROGRAMMABE POWER SUPPY MINI COMPUTER DC ANAYZER + DEICE UNDER TEST ANAOG IN COMMON OUT EE Figure 2. On Resistance Test Set Up ery igh Speed CMOS ogic C Data D203 Rev 2 15 MOTOROA

192 MC4C4316 EE A OFF 16 O/I EE A ON 16 N/C 9 SEECTED CONTRO INPUT I 9 SEECTED CONTRO INPUT I EE EE Figure 3. Maximum Off Channel eakage Current, Any One Channel, Test Set Up Figure 4. Maximum On Channel eakage Current, Test Set Up IS fin 16 R ON 0.1 µf R C* TO db METER fin 16 OFF 0.1 µf R R C* TO db METER EE 9 SEECTED CONTRO INPUT EE 9 SEECTED CONTRO INPUT *Includes all probe and jig capacitance. Figure 5. Maximum On Channel Bandwidth Test Set Up *Includes all probe and jig capacitance. Figure 6. Off Channel Feedthrough Isolation, Test Set Up 16 EE R 9 ON/OFF SEECTED CONTRO INPUT R C* TEST POINT ANAOG IN tp 50% tp CONTRO *Includes all probe and jig capacitance. ANAOG OUT 50% Figure. Feedthrough Noise, Control to Analog Out, Test Set Up Figure. Propagation Delays, Analog In to Analog Out MOTOROA 16 ery igh Speed CMOS ogic C Data D203 Rev 2

193 MC4C4316 ANAOG I/O ON 16 ANAOG O/I 50 pf* TEST POINT ENABE CONTRO 50% tr tf 9 SEECTED CONTRO INPUT *Includes all probe and jig capacitance. ANAOG OUT tpz 50% tpz 50% tpz tpz 10% 90% IG IMPEDANCE O O IG IMPEDANCE Figure 9. Propagation Delay Test Set Up Figure 10. Propagation Delay, ON/OFF Control to Analog Out POSITION POSITION CONTRO OR ENABE WEN TESTING tpz AND tpz WEN TESTING tpz AND tpz ON/OFF 16 1 kω TEST POINT 50 pf* fin 0.1 µf EE R IS 9 ON OFF 16 SEECTED CONTRO INPUT R ANAOG I/O R C* C* TEST POINT *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set Up *Includes all probe and jig capacitance. Figure 12. Crosstalk Between Any Two Switches, Test Set Up (Adjacent Channels Used) N/C ON/OFF 16 A N/C fin 10 µf IS ON 16 R OS C* TO DISTORTION METER EE CONTRO 9 SEECTED CONTRO INPUT EE 9 SEECTED CONTRO INPUT *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set Up Figure 14. Total armonic Distortion, Test Set Up ery igh Speed CMOS ogic C Data D203 Rev 2 1 MOTOROA

194 MC4C4316 dbm FUNDAMENTA FREUENCY DEICE SOURCE FREUENCY (kz) Figure 15. Plot, armonic Distortion 3.0 APPICATION INFORMATION The Enable and Control pi should be at or logic levels, being recognized as logic high and being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). owever, it is advisable to tie unused analog inputs and outputs to or EE through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pi. The maximum analog voltage swings are determined by the supply voltages and EE. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below EE. In the example below, the difference between and EE is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak to peak can be controlled. When voltage traients above and/or below EE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 1. These diodes should be small signal, fast turn on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOsorbs (Motorola high current surge protectors). MOsorbs are fast turn on devices ideally suited for precise dc protection with no inherent wear out mechanism. = ANAOG I/O + 6 ON 16 SEECTED CONTRO INPUT EE ANAOG O/I ENABE CONTRO INPUTS ( OR ) Dx Dx EE ON 16 SEECTED CONTRO INPUT EE Dx Dx EE ENABE CONTRO INPUTS ( OR ) Figure 16. Figure 1. Traient Suppressor Application MOTOROA 1 ery igh Speed CMOS ogic C Data D203 Rev 2

195 MC4C4316 = 5 +5 ANAOG SIGNAS 16 ANAOG SIGNAS ANAOG SIGNAS 16 ANAOG SIGNAS TT R* R* R* R* R* C4316 ENABE AND CONTRO INPUTS 9 EE = 0 TO 6 STT/ NMOS CT BUFFER C4316 CONTRO INPUTS 9 EE = 0 TO 6 R* = 2 TO 10 kω a. Using Pull Up Resistors b. Using CT Buffer Figure 1. STT/NMOS to CMOS Interface = POWER SUPPY R1 R2 = 6 EE = 0 R1 = R2 12 PP ANAOG INPUT SIGNA C R3 R4 EE 1 OF 4 SWITCES R1 = R2 R3 = R4 ANAOG OUTPUT SIGNA 12 0 Figure 19. Switching a 0 to 12 Signal Using a Single Power Supply ( 0 ) CANNE 4 1 OF 4 SWITCES CANNE 3 CANNE 2 1 OF 4 SWITCES 1 OF 4 SWITCES COMMON I/O CANNE 1 1 OF 4 SWITCES INPUT 1 OF 4 SWITCES + F356 OR EUIAENT OUTPUT 0.01 µf CONTRO INPUTS Figure Input Multiplexer Figure 21. Sample/old Amplifier ery igh Speed CMOS ogic C Data D203 Rev 2 19 MOTOROA

196 SEMICONDUCTOR TECNICA DATA igh Performance Silicon Gate CMOS The MC4C4351 utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from to EE). The Channel Select inputs determine which one of the Analog Inputs/ Outputs is to be connected, by mea of an analog switch, to the Common Output/Input. The data at the Channel Select inputs may be latched by using the active low atch Enable pin. When atch Enable is high, the latch is traparent. When either Enable 1 (active low) or Enable 2 (active high) is inactive, all analog switches are turned off. The Channel Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with STT outputs. This device has been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal gate CMOS analog switches. For multiplexers/demultiplexers without latches, see the C4051, C4052, and C4053. Fast Switching and Propagation Speeds ow Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range ( EE) = 2.0 to 12.0 Digital (Control) Power Supply Range ( ) = 2.0 to 6.0 Improved inearity and ower ON Resistance than Metal Gate Types ow Noise In Compliance with the Requirements Defined by JEDEC Standard No. A Chip Complexity: 222 FETs or 55.5 Equivalent Gates DW SUFFIX 20 EAD SOIC WIDE PACKAGE CASE 51D 04 DT SUFFIX 20 EAD TSSOP PACKAGE CASE 94E 02 ORDERING INFORMATION MC4CXXXXDW MC4CXXXXDT PIN ASSIGNMENT MC4C4351 X4 X6 NC X X5 ENABE 1 ENABE 2 X 5 EE NC = NO CONNECTION SOIC Wide TSSOP X2 X1 X0 X3 A NC B C ATC ENABE This document contai information on a new product. Specificatio and information herein are subject to change without notice. 12/9 Motorola, Inc RE 0

197 MC4C4351 OGIC DIAGRAM MC4C4351 Single Pole, Position Plus Common Off and Address atch ANAOG INPUTS/OUTPUTS CANNE SEECT INPUTS A B C ATC ENABE SWITC ENABE 1 ENABES ENABE X0 1 X1 19 X2 16 X3 1 X4 6 X5 2 X6 5 X CANNE ADDRESS ATC MUTIPEXER/ DEMUTIPEXER 4 X COMMON OUTPUT/INPUT PIN 20 = PIN 9 = EE PIN 10 = PINS 3, 14 = NC FUNCTION TABE MC4C4351 Control Inputs ON Enable Select Channel 1 2 C B A (E = )* X0 X1 X2 X3 X4 X5 X6 X X X X X None X X X X None X = don t care * When atch Enable is low, the Channel Selection is latched and the Channel Address atch does not change states. MAXIMUM RATINGS* SymbolÎ alue Unit Positive DC Supply oltage (Ref. to ) 0.5 to +.0 (Ref. to EE) 0.5 to 14.0 EE Negative DC Supply oltage (Ref. to ).0 to IS Analog Input oltage EE 0.5 to in DC Input oltage (Ref. to ) 0.5 to I Î DC Current Into or Out of Any Pin ± 25 ma P D Power Dissipation in Still Air SOIC or TSSOP 50 mw 500 Tstg Storage Temperature 65 to C T ead Temperature, 1 mm from Case for 10 Seconds 260 C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. Derating SOIC Package: mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the ranges indicated in the Recommended Operating Conditio. Unused digital input pi must be tied to an appropriate logic voltage level (e.g., either or ). Unused Analog I/O pi may be left open or terminated. See Applicatio Information. ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

198 MC4C4351 RECOMMENDED OPERATING CONDITIONS Symbol Positive DC Supply oltage Min Max Unit (Ref. to ) Î (Ref. to EE) EE Negative DC Supply oltage (Ref. to ) 6.0 IS Analog Input oltage EE in Digital Input oltage (Ref. to ) IO* Static or Dynamic oltage Across Switch 1.2 TA Operating Temperature, All Package Types C tr, tf Input Rise and Fall Time, = Channel Select or Enable = Î Inputs (Figure 9a) = = 6.0 * For voltage drops across the switch greater than 1.2 (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC EECTRICA CARACTERISTICS Digital Section (oltages Referenced to ) EE =, Except Where Noted Guaranteed imit Symbol Test Conditio 55 to 25 C 5 C 125 C Unit Î I Minimum igh evel Input Ron = Per Spec oltage, Channel Select or Enable Inputs Î I Maximum ow evel Input Î Ron = Per Spec oltage, Channel Select or Enable Inputs Iin Î Maximum Input eakage Î in = or, 6.0 ± 0.1 ± 1.0 ± Current, Channel Select or EE = 6.0 µa Enable Inputs ICC Maximum uiescent Supply Î Channel Select = or µa Current (per Package) Î Enables = or IS = or EE = 6.0 IO = 0 EE = DC EECTRICA CARACTERISTICS Analog Section Guaranteed imit Î Symbol Î Î Test Conditio CC EE 55 to 25 C 5 C 125 C Unit RonÎ Maximum ON Resistance Î in = I or I TBD TBD TBD Ω IS = to EE IS 2.0 ma (Figures 1, 2) Î Î Î Î in = I or I TBD TBD TBD IS = or EE (Endpoints) Î IS 2.0 ma (Figures 1, 2) Î Ron Maximum Difference in ON in = I or I 3.0 TBD TBD TBD Ω Resistance Between Any TwoÎ IS = 1/2 ( EE) Channels in the Same Package Î IS 2.0 ma MOTOROA 192 ery igh Speed CMOS ogic C Data D203 Rev 2

199 MC4C4351 DC EECTRICA CARACTERISTICS Analog Section Guaranteed imit Î EE 55 to Symbol Test Conditio 25 C 5 C 125 C Unit Î Ioff Maximum Off Channel eakage in = I or I µa Current, Any One Channel Î IO = Î EE Switch Off (Figure 3) Î Î Maximum Off Channel eakage Î in = I or I Î Current, Common Channel IO = EE Î Î Switch Off (Figure 4) Ion Î Maximum On Channel eakage Î in = I or I µa Current, Channel to Channel Switch to Switch = EE Î (Figure 5) AC EECTRICA CARACTERISTICS (C = 50 pf, Input tr = tf = 6 ) Guaranteed imit Î 55 to Symbol 25 C 5 C 125 C Unit tp, Î Maximum Propagation Delay, Channel Select to Analog Output tp (Figure 9) 3.0 TBD TBD TBD tp, Î Maximum Propagation Delay, Analog Input to Analog Output tp (Figure 10) 3.0 TBD TBD TBD tp, Maximum Propagation Delay, atch Enable to Analog Output Î tp (Figure 12) 3.0 TBD TBD TBD Î tpz, Maximum Propagation Delay, Enable 1 or 2 to Analog Output tpz (Figure 11) 3.0 TBD TBD Î tpz, Maximum Propagation Delay, Enable 1 or 2 to Analog Output tpz (Figure 11) 3.0 TBD TBD Cin Î Maximum Input Capacitance pf Cl/O Î Maximum Capacitance Analog I/O Enable 1 = I, Enable 2 = I pf Common O/I Feedthrough CPD Power Dissipation Capacitance acitance (Per Package) (Figure 19. )* 25 C, = 5.0 pf 45 * Used to determine the no load dynamic power coumption: PD = CPD 2 f + ICC. ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

200 MC4C4351 TIMING REUIREMENTS (Input tr = tf = 6 ) Î Guaranteed imit Î 55 to Symbol Î 25 C 5 C 125 C Unit tsu Minimum Setup Time, Channel Select to atch Enable (Figure 12) 3.0 TBD TBD TBD Î th Minimum old Time, atch Enable to Channel Select (Figure 12) 3.0 TBD TBD Î tw Minimum Pulse Width, atch Enable (Figure 12) 3.0 TBD TBD Î tr, tf Maximum Input Rise and Fall Times, Channel Select, atch Enable, and Enables 1 and Î ADDITIONA APPICATION CARACTERISTICS ( = 0.0 ) imit* Symbol Test Condition EE 25 C Î 4C Unit Î BW Maximum On Channel Bandwidth or fin = 1 Mz Sine Wave Î Minimum Frequency Respoe Adjust fin oltage to Obtain 0 dbm at OS Mz (Figure 6) Increase fin Frequency Until db Meter Reads 3 db 4.50 Î 0 R = 50 Ω, C = 10 pf 6.00 Î 0 Off Channel Feedthrough Isolation fin Sine Wave Î db (Figure ) Adjust fin oltage to Obtain 0 dbm at IS fin = 10 kz, R = 600 Ω, C = 50 pf Î Î Î fin = 1.0 Mz, R = 50 Ω, C = 10 pf Î Î Feedthrough Noise, Channel Select in 1 Mz Square Wave Î mpp Input to Common O/I (tr = tf = 6 ) Î (Figure ) Adjust R at Setup so that IS = 0 A Î Enable = Î R = 600 Ω, C = 50 pf Î 6.00 Î 135 R = 10 kω, C = 10 pf 2.25 Î Î 6.00 Î 190 TD Total armonic Distortion fin = 1 kz, R = 10 kω, C = 50 pf Î % Î (Figure 14) TD = TDMeasured TDSource Î IS = 4.0 PP sine IS =.0 PP sine wave 4.50 Î 0.0 IS = 11.0 PP sine wave Î * imits not tested. Determined by design and verified by qualification. MOTOROA 194 ery igh Speed CMOS ogic C Data D203 Rev 2

201 MC4C4351 Ron, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C R on, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1a. Typical On Resistance, EE = IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1b. Typical On Resistance, EE = 3.0 Ron, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C R on, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1c. Typical On Resistance, EE = 4.5 IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1d. Typical On Resistance, EE = Ron, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C Ron, ON RESISTANCE (OMS) TBD 125 C 25 C 55 C IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1e. Typical On Resistance, EE = 9.0 IS, INPUT OTAGE (OTS), REFERENCED TO EE Figure 1f. Typical On Resistance, EE = 12.0 ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

202 MC4C4351 POTTER PROGRAMMABE POWER SUPPY MINI COMPUTER DC ANAYZER + DEICE UNDER TEST ANAOG IN COMMON OUT EE Figure 2. On Resistance Test Set Up MOTOROA 196 ery igh Speed CMOS ogic C Data D203 Rev 2

203 MC4C4351 EE A ANAOG I/O NC OFF OFF 20 COMMON O/I EE ANAOG I/O OFF OFF 20 A COMMON O/I I 9 10 I 9 10 EE EE Figure 3. Maximum Off Channel eakage Current, Any One Channel, Test Set Up Figure 4. Maximum Off Channel eakage Current, Common Channel, Test Set Up EE A ANAOG I/O I I 9 10 ON OFF 20 COMMON O/I N/C fin 0.1µF 9 10 ON 20 OS C* db METER R EE EE *Includes all probe and jig capacitance. Figure 5. Maximum On Channel eakage Current, Channel to Channel, Test Set Up Figure 6. Maximum On Channel Bandwidth, Test Set Up fin IS 0.1 µf R EE 9 10 OFF 20 OS C* db METER R in 1 Mz tr = tf = 6 R ANAOG I/O EE R 9 10 ON/OFF OFF/ON CANNE SEECT COMMON O/I R C* TEST POINT *Includes all probe and jig capacitance. Figure. Off Channel Feedthrough Isolation, Test Set Up *Includes all probe and jig capacitance. Figure. Feedthrough Noise, Channel Select to Common Out, Test Set Up ery igh Speed CMOS ogic C Data D203 Rev 2 19 MOTOROA

204 MC4C tr CANNE SEECT tp 90% 50% 10% tf tp ANAOG I/O 9 10 ON/OFF OFF/ON COMMON O/I C* TEST POINT ANAOG OUT 50% CANNE SEECT *Includes all probe and jig capacitance. Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set Up Channel Select to Analog Out 20 ANAOG IN tp ANAOG OUT 50% 50% tp ANAOG I/O 9 10 ON COMMON O/I C* TEST POINT *Includes all probe and jig capacitance. Figure 10a. Propagation Delays, Analog In to Analog Out Figure 10b. Propagation Delay, Test Set Up Analog In to Analog Out 1 POSITION POSITION 1 WEN TESTING tpz AND tpz 2 WEN TESTING tpz AND tpz ENABE ANAOG OUT ANAOG OUT 50% tpz 50% tpz 50% tpz tpz 10% 90% IG IMPEDANCE O O IG IMPEDANCE ANAOG I/O ENABE 9 10 ON/OFF 20 1 kω C* TEST POINT Figure 11a. Propagation Delay, Enable 1 or 2 to Analog Out Figure 11b. Propagation Delay, Test Set Up Enable to Analog Out MOTOROA 19 ery igh Speed CMOS ogic C Data D203 Rev 2

205 MC4C4351 CANNE SEECT ATC ENABE 2 tr 10% 50% tsu 90% 50% tw tf th ANAOG I/O 9 10 ON/OFF OFF/ON COMMON O/I C* TEST POINT ATC ENABE COMMON O/I 50% CANNE SEECT tp, tp *Includes all probe and jig capacitance. Figure 12a. Propagation Delay, atch Enable to Analog Out Figure 12b. Propagation Delay, Test Set Up atch Enable to Analog Out 20 A ANAOG I/O ON/OFF OFF/ON NC COMMON O/I EE CANNE SEECT Figure 19. Power Dissipation Capacitance, Test Set-Up 0 fin IS 0.1 µf EE 9 10 ON 20 R OS C* TO DISTORTION METER db FUNDAMENTA FREUENCY DEICE SOURCE *Includes all probe and jig capacitance. Figure 14a. Total armonic Distortion, Test Set-Up FREUENCY (kz) Figure 14b. Plot, armonic Distortion ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

206 MC4C4351 APPICATIONS INFORMATION The Channel Select and Enable control pi should be at or logic levels. being recognized as a logic high and being recognized as a logic low. In this example: = + 5 = logic high = 0 = logic low The maximum analog voltage swings are determined by the supply voltages and EE. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below EE. In this example, the difference between and EE is ten volts. Therefore, using the configuration in Figure 15, a maximum analog signal of ten volts peak to peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). owever, tying unused analog inputs and outputs to or through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only cotraints on the power supplies are that: = 2 to 6 volts EE = 0 to 6 volts EE = 2 to 12 volts and EE When voltage traients above and/or below EE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 16. These diodes should be able to absorb the maximum anticipated current surges during clipping ANAOG SIGNA ON 20 ANAOG SIGNA Dx Dx 20 ON/OFF Dx Dx EE TO EXTERNA CMOS CIRCUITRY 0 TO 5 DIGITA SIGNAS 9 10 EE EE Figure 15. Application Example Figure 16. External Germanium or Schottky Clipping Diodes EE ANAOG SIGNA 20 ON/OFF ANAOG SIGNA EE + 5 EE ANAOG SIGNA ON/OFF 20 ANAOG SIGNA + 5 EE * R R R R STT/NMOS CIRCUITRY STT/NMOS CIRCUITRY EE * 2 k R 10 k EE CT BUFFER a. Using Pull Up Resistors b. Using CT Interface Figure 1. Interfacing STT/NMOS to CMOS Inputs MOTOROA 200 ery igh Speed CMOS ogic C Data D203 Rev 2

207 MC4C4351 FUNCTION DIAGRAM C4351 A 15 ATC & EE SIFTER 1 X0 X1 B 13 ATC & EE SIFTER X2 X3 C 12 ATC & EE SIFTER X4 ATC ENABE 11 6 X5 ENABE 1 ENABE 2 EE SIFTER 2 5 X6 X 4 X ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

208 SEMICONDUCTOR TECNICA DATA Device Nomenclature MC 4 CX YYY A ZZ Motorola Circuit Identifier Temperature Range 4 = 40 to +5 C Family Identifier C = ery igh Speed CMOS CT = ery igh Speed CMOS, TT Compatible Inputs CU = ery igh Speed CMOS, Unbuffered Package Type D = Plastic Narrow JEDEC SOIC DW = Plastic Wide JEDEC SOIC M = Plastic EIAJ SOIC DT = Plastic TSSOP Output Type Indicates Full CMOS Output Swing (Shown on CT Only; all C parts have full CMOS output swings) Function Type MOTOROA 202 ery igh Speed CMOS ogic C Data D203 Rev 2

209 Case Outlines D SUFFIX PASTIC SOIC PACKAGE CASE 51A 03 ISSUE F SEATING PANE 14 G A 1 B C P P D 14 P K 0.25 (0.010) M T B S A S 0.25 (0.010) M B M R X 45 M J F NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.12 (0.005) TOTA IN EXCESS OF TE D DIMENSION AT MAXIMUM MATERIA CONDITION. DIM A B C D F G J K M P R MIIMETERS MIN MAX BSC BSC INCES MIN MAX DT SUFFIX PASTIC TSSOP PACKAGE CASE 94G 01 ISSUE O 0.15 (0.006) T 0.15 (0.006) T 0.10 (0.004) T SEATING PANE U U S 2X /2 PIN 1 IDENT. S D C X K REF 0.10 (0.004) M T U S S N 0.25 (0.010) M B U A G N J J1 F DETAI E K K1 ÇÇÇ ÉÉÉ SECTION N N DETAI E W NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS, PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE K DIMENSION AT MAXIMUM MATERIA CONDITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC J J K K BSC BSC M 0 0 ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

210 Case Outlines (continued) e 14 1 Z D E b A (0.005) M 0.10 (0.004) E A IEW P M SUFFIX PASTIC SOIC EIAJ PACKAGE CASE ISSUE O M E DETAI P 1 c NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS D AND E DO NOT INCUDE MOD FAS OR PROTRUSIONS AND ARE MEASURED AT TE PARTING INE. MOD FAS OR PROTRUSIONS SA NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 5. TE EAD WIDT DIMENSION (b) DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE EAD WIDT DIMENSION AT MAXIMUM MATERIA CONDITION. DAMBAR CANNOT BE OCATED ON TE OWER RADIUS OR TE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT EAD TO BE 0.46 ( 0.01). MIIMETERS INCES DIM MIN MAX MIN MAX A A b c D E e 1.2 BSC BSC E E M Z MOTOROA 204 ery igh Speed CMOS ogic C Data D203 Rev 2

211 Case Outlines D SUFFIX PASTIC SOIC PACKAGE CASE 51B 05 ISSUE J T SEATING PANE 16 A 1 G D 16 P 9 K B C P P 0.25 (0.010) M T B S A S 0.25 (0.010) M B M M R X 45 J F NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.12 (0.005) TOTA IN EXCESS OF TE D DIMENSION AT MAXIMUM MATERIA CONDITION. DIM A B C D F G J K M P R MIIMETERS MIN MAX INCES MIN MAX BSC BSC DT SUFFIX PASTIC TSSOP PACKAGE CASE 94F 01 ISSUE O 0.15 (0.006) T 0.15 (0.006) T 0.10 (0.004) T SEATING PANE U PIN 1 IDENT. U D S S 2X /2 C 16X K REF 0.10 (0.004) M T U S S A G B U N N J J1 F DETAI E DETAI E K K1 ÇÇ ÇÇ ÉÉ SECTION N N 0.25 (0.010) M W NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS. PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE K DIMENSION AT MAXIMUM MATERIA CONDITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC J J K K BSC BSC M 0 0 ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

212 Case Outlines (continued) e Z b D A E A (0.005) M 0.10 (0.004) E M SUFFIX PASTIC SOIC EIAJ PACKAGE CASE ISSUE O IEW P M E DETAI P 1 c NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS D AND E DO NOT INCUDE MOD FAS OR PROTRUSIONS AND ARE MEASURED AT TE PARTING INE. MOD FAS OR PROTRUSIONS SA NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 5. TE EAD WIDT DIMENSION (b) DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE EAD WIDT DIMENSION AT MAXIMUM MATERIA CONDITION. DAMBAR CANNOT BE OCATED ON TE OWER RADIUS OR TE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT EAD TO BE 0.46 ( 0.01). MIIMETERS INCES DIM MIN MAX MIN MAX A A b c D E e 1.2 BSC BSC E E M Z MOTOROA 206 ery igh Speed CMOS ogic C Data D203 Rev 2

213 Case Outlines 20 1 A 20X D B (0.25) M T A S B S 1X G K C DW SUFFIX PASTIC SOIC WIDE PACKAGE CASE 51D 04 ISSUE E 10X P (0.25) M T SEATING PANE J F B M M R X 45 NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.13 (0.005) TOTA IN EXCESS OF D DIMENSION AT MAXIMUM MATERIA CONDITION. MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 1.2 BSC BSC J K M 0 0 P R DT SUFFIX PASTIC TSSOP PACKAGE CASE 94E 02 ISSUE A 0.15 (0.006) T U 2X / (0.006) T U S PIN 1 IDENT S C (0.004) T SEATING PANE 20X K REF 0.10 (0.004) M T U S S A D G B U J J1 N N K K1 ÍÍÍÍ ÍÍÍÍ SECTION N N F DETAI E 0.25 (0.010) DETAI E M W NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS, PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE K DIMENSION AT MAXIMUM MATERIA CONDITION. 6. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC J J K K BSC BSC M 0 0 ery igh Speed CMOS ogic C Data D203 Rev 2 20 MOTOROA

214 Case Outlines (continued) M SUFFIX PASTIC SOIC EIAJ PACKAGE CASE ISSUE O e E E 1 10 Z D A b A (0.005) M 0.10 (0.004) IEW P M E DETAI P 1 c NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS D AND E DO NOT INCUDE MOD FAS OR PROTRUSIONS AND ARE MEASURED AT TE PARTING INE. MOD FAS OR PROTRUSIONS SA NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 5. TE EAD WIDT DIMENSION (b) DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE EAD WIDT DIMENSION AT MAXIMUM MATERIA CONDITION. DAMBAR CANNOT BE OCATED ON TE OWER RADIUS OR TE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT EAD TO BE 0.46 ( 0.01). MIIMETERS INCES DIM MIN MAX MIN MAX A A b c D E e 1.2 BSC BSC E E M Z MOTOROA 20 ery igh Speed CMOS ogic C Data D203 Rev 2

215 Case Outlines Three Ways To Receive Motorola Semiconductor Technical Information iterature Centers Printed literature can be obtained from the iterature Centers upon request. For those items that incur a cost, the U.S. iterature Center will accept Master Card and isa. ow to reach us: USA/EUROPE/ocatio Not isted: Motorola iterature Distribution P.O. Box 5405 Denver, Colorado 021 Phone: or JAPAN: Nippon Motorola td. SPD, Strategic Planning Office , Nishi Gotanda, Shinagawa ku Tokyo 141, Japan Phone: ASIA/PACIFIC: Motorola Semiconductors.K. td. B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., ong Kong Phone: Mfax - Touch Tone Fax Mfax offers access to over 30,000 Motorola documents for faxing to customers worldwide. With menus and voice itruction, customers can request the documents needed, using their own touch tone telephones from any location, days a week and 24 hours a day. A number of features are offered within the Mfax system, including product data sheets, application notes, engineering bulleti, article reprints, selector guides, iterature Order Forms, Technical Training Information, and OT DOCS (4 digit code identifiers for currently referenced promotional or advertising material). A fax of complete, easy to use itructio can be obtained with a first time phone call into the system, entering your FAX number and then, pressing 1. ow to reach us: Mfax : RMFAX0@ .sps.mot.com TOUC TONE Motorola Fax Back System US & Canada ONY Motorola SPS Internet Server Motorola SPS s Electronic Data Delivery organization has set up a World Wide Web Server to deliver Motorola SPS s technical data to the global Internet community. Technical data such as the complete Master Selection Guide along with the OEM North American price book are available on the Internet server with full search capabilities. Other data on the server include abstracts of data books, application notes, selector guides, and textbooks. All have easy text search capability. Ordering literature from the iterature Center is available on line. Other features of Motorola SPS s Internet server include the availability of a searchable press release database, technical training information, with on line registration capabilities, complete on line access to the Mfax system for ordering faxes, an on line technical support form to send technical questio and receive awers through , information on product groups, full search capabilities of device models, a listing of the Domestic and International sales offices, and links directly to other Motorola world wide web servers. ow to reach us: After accessing the Internet, use the following UR: ow to reach MFAX directly: After accessing the Internet, use the following UR: ery igh Speed CMOS ogic C Data D203 Rev MOTOROA

216 MOTOROA AUTORIZED DISTRIBUTOR & WORDWIDE SAES OFFICES NORT AMERICAN DISTRIBUTORS UNITED STATES AABAMA untsville Allied Electronics, Inc (205) Arrow Electronics (205) FAI (205) Future Electronics (205) amilton/allmark (205)3 00 Newark (205) Wyle Electronics (205) Mobile Allied Electronics, Inc (334)46 15 ARIZONA Phoenix Allied Electronics, Inc (602) FAI (602) Future Electronics (602) amilton/allmark (602) Wyle Electronics (602) Tempe Arrow Electronics (602) Newark (602) PENSTOCK (602) CAIFORNIA Agoura ills Future Electronics (1) Calabassas Arrow Electronics (1)0 966 Wyle Electronics (1) Culver City amilton/allmark (310) Irvine Arrow Electronics (14) Arrow Zeus (14) FAI (14)53 4 Future Electronics (14) amilton/allmark (14) Wyle aboratories Corporate. (14) Wyle Electronics (14) os Angeles FAI (1) Manhattan Beach PENSTOCK (310) Newberry Park PENSTOCK (05) Orange County Allied Electronics, Inc (14) Palo Alto Newark (415) Rancho Cordova Wyle Electronics (916) Riverside Allied Electronics, Inc (909) Newark (909) Rocklin amilton/allmark (916) Roseville Wyle Electronics (916) Sacramento Allied Electronics, Inc (916) FAI (916)2 2 Newark (916) San Diego Allied Electronics, Inc (619) Arrow Electronics (619) FAI (619)623 2 Future Electronics (619) amilton/allmark (619) Newark (619) PENSTOCK (619) Wyle Electronics (619) San Fernando alley Allied Electronics, Inc (1) CAIFORNIA continued San Jose Allied Electronics, Inc (40) Arrow Electronics (40) Arrow Electronics (40) Arrow Zeus (40) FAI (40) Future Electronics (40) Santa Clara Wyle Electronics (40) Santa Fe Springs Newark (310) Sierra Madre PENSTOCK (1) Sunnyvale amilton/allmark (40) PENSTOCK (40) Thousand Oaks Newark (05) Woodland ills amilton/allmark (1) COORADO akewood FAI (303) Future Electronics (303) Denver Allied Electronics, Inc (303) Newark (303) Englewood Arrow Electronics (303) amilton/allmark (303) PENSTOCK (303)99 45 Thornton Wyle Electronics (303) CONNECTICUT Bloomfield Newark (203) Cheshire Allied Electronics, Inc (203)22 30 FAI (203) Future Electronics (203) amilton/allmark (203) Wallingford Arrow Electronics (203) Wyle Electronics (203)269 0 FORIDA Altamonte Springs Future Electronics (40) Clearwater FAI (13) Future Electronics (13) Deerfield Beach Arrow Electronics (305) Wyle Electronics (954) Ft. auderdale FAI (954) Future Electronics (954) amilton/allmark (954) Newark (954) Jacksonville Allied Electronics, Inc (904) Newark (904) ake Mary Arrow Electronics (40) Arrow Zeus (40) argo/tampa/st. Petersburg amilton/allmark (13) Newark (13)2 15 Wyle Electronics (13) Miami Allied Electronics, Inc (305) Maitland Wyle Electronics (40) Orlando Allied Electronics, Inc (40) FAI (40) Newark (40) FORIDA continued Tallahassee FAI (904)66 2 Tampa Allied Electronics, Inc (13) Newark (13)2 15 PENSTOCK (13) Winter Park amilton/allmark (40) PENSTOCK (40) GEORGIA Atlanta Allied Electronics, Inc (0) FAI (404)44 46 Duluth Arrow Electronics (404) amilton/allmark (0) Norcross Future Electronics (0) Newark (0) PENSTOCK (0) Wyle Electronics (0) IDAO Boise Allied Electronics, Inc (20) FAI (20)36 00 Newark (20) IINOIS Addison Wyle aboratories (0) Arlington eights amilton/allmark (4)9 300 Chicago Allied Electronics, Inc. (North). (4) Allied Electronics, Inc. (South). (0) FAI (0) Newark Electronics Corp..... (3) offman Estates Future Electronics (0) Itasca Arrow Electronics (0) Arrow Zeus (630) ombard Newark (630) Palatine PENSTOCK (0) Rockford Allied Electronics, Inc (15) Springfield Newark (21) 992 Wood Dale Allied Electronics, Inc (630) INDIANA Indianapolis Allied Electronics, Inc (31)51 10 Arrow Electronics (31) amilton/allmark (31) FAI (31) Future Electronics (31) Newark (31) Wyle Electronics (31) Ft. Wayne Newark (219) PENSTOCK (219) IOWA Bettendorf Newark (319) Cedar Rapids Allied Electronics, Inc (319) Newark (319) KANSAS Kaas City Allied Electronics, Inc (913) FAI (913) enexa Arrow Electronics (913) MOTOROA 210 TIMING SOUTIONS BR1333 Rev 6

217 UNITED STATES continued KANSAS continued Olathe PENSTOCK (913) Overland Park Future Electronics (913) amilton/allmark (913) Newark (913)6 02 KENTUCKY ouisville Allied Electronics, Inc (502) Newark (502) OUISIANA New Orlea Allied Electronics, Inc (504) MARYAND Baltimore Allied Electronics, Inc (410) FAI (410) Columbia Arrow Electronics (301) Arrow Zeus (410) Future Electronics (410) amilton/allmark (410) PENSTOCK (410) Wyle Electronics (410) anover Newark (410) MASSACUSETTS Bedford Wyle Electronics (1) Boston Allied Electronics, Inc (61) Arrow Electronics (50) FAI (50) Newark NEWARK Bolton Future Corporate (50) Burlington PENSTOCK (61) Peabody Allied Electronics, Inc (50) amilton/allmark (50) Wilmington Arrow Zeus (9)65 46 Woburn Newark (61) MICIGAN Detroit Allied Electronics, Inc (313) FAI (313) Future Electronics (616) Grand Rapids Allied Electronics, Inc (616) Newark (616) ivonia Arrow Electronics (10) Future Electronics (313) amilton/allmark (313) Novi Wyle Electronics (24) Saginaw Newark (51) Troy Newark (24) MINNESOTA Bloomington Wyle Electronics (612) Burville PENSTOCK (612)2 630 Eden Prairie Arrow Electronics (612) FAI (612) Future Electronics (612) amilton/allmark (612) Minneapolis Allied Electronics, Inc (612) Newark (612) AUTORIZED DISTRIBUTORS continued MISSISSIPPI Jackson Newark (601) MISSOURI Earth City amilton/allmark (314) St. ouis Allied Electronics, Inc (314) Arrow Electronics (314)56 6 Future Electronics (314) FAI (314) Newark (314) NEBRASKA Omaha Allied Electronics, Inc (402) Newark (402) NEADA as egas Allied Electronics, Inc (02)25 10 Wyle Electronics (02)65 11 NEW JERSEY Bridgewater PENSTOCK (90) East Bruwick Allied Electronics, Inc (90) Newark (90) Fairfield FAI (201) Marlton Arrow Electronics (609) FAI (609) Future Electronics (609) Mt. aurel amilton/allmark (609) Wyle Electronics (609) Oradell Wyle Electronics (201) Pinebrook Arrow Electronics (201)22 0 Wyle Electronics (93)2 35 Parsippany Future Electronics (201) amilton/allmark (201) NEW MEXICO Albuquerque Allied Electronics, Inc (505) amilton/allmark (505) Newark (505)2 1 NEW YORK Albany Newark (51)3 093 Buffalo Newark (16) Great Neck Allied Electronics, Inc (516) auppauge Allied Electronics, Inc (516) Arrow Electronics (516) FAI (516) Future Electronics (516) amilton/allmark (516) Newark (516) PENSTOCK (516) Wyle Electronics (516) enrietta Wyle Electronics (16) Konkoma amilton/allmark (516) Pittsford Newark (16) Poughkeepsie Allied Electronics, Inc (914) Newark (914) Purchase Arrow Zeus (914) NEW YORK continued Rochester Allied Electronics, Inc (16) Arrow Electronics (16) Future Electronics (16) FAI (16) amilton/allmark (16) Syracuse Allied Electronics, Inc (315) FAI (315) Future Electronics (315) Newark (315)45 43 NORT CAROINA Charlotte Allied Electronics, Inc (04) FAI (04) Future Electronics (04) Newark (04) Greeboro Newark (910) Morrisville Wyle Electronics (919) Raleigh Allied Electronics, Inc (919)6 545 Arrow Electronics (919) FAI (919)6 00 Future Electronics (919) amilton/allmark (919)2 012 OIO Centerville Arrow Electronics (513) Cincinnati Allied Electronics, Inc (513) Newark (513)2 11 Cleveland Allied Electronics, Inc (216) FAI (216) Newark (216) Columbus Allied Electronics, Inc (614)5 120 Newark (614) Dayton FAI (513) Future Electronics (513) amilton/allmark (513) Newark (513) Mayfield eights Future Electronics (216) Miamisburg Wyle Electronics (93) Solon Arrow Electronics (216) amilton/allmark (216) Wyle Electronics (440) Toledo Newark (419) Worthington amilton/allmark (614) 3313 OKAOMA Oklahoma City Newark (405) Tulsa Allied Electronics, Inc (91) FAI (91) amilton/allmark (91) OREGON Beaverton Arrow/Almac Electronics Corp. (503) Future Electronics (503) amilton/allmark (503) Portland Allied Electronics, Inc (503) FAI (503) Newark (503) PENSTOCK (503) Wyle Electronics (503) TIMING SOUTIONS BR1333 Rev MOTOROA

218 UNITED STATES continued PENNSYANIA Allentown Newark (610) Chadds Ford Allied Electronics, Inc (610)3 455 Coatesville PENSTOCK (610) Ft. Washington Newark (215) arrisburg Allied Electronics, Inc (1) Philadelphia Allied Electronics, Inc (609) Pittsburgh Allied Electronics, Inc (412) Arrow Electronics (412) Newark (412) 490 SOUT CAROINA Greenville Allied Electronics, Inc (64)2 35 Newark (64) TENNESSEE Knoxville Newark (423) Memphis Newark (901) TEXAS Austin Allied Electronics, Inc (512) Arrow Electronics (512) Future Electronics (512) FAI (512) amilton/allmark (512) Newark (512)33 02 PENSTOCK (512) Wyle Electronics (512) Benbrook PENSTOCK (1) Browville Allied Electronics, Inc (210) Carrollton Arrow Electronics (214) Arrow Zeus (92) Dallas Allied Electronics, Inc (214) FAI (214) Future Electronics (214) amilton/allmark (214) Newark (92) El Paso Allied Electronics, Inc (915) FAI (915) Newark (915)2 636 Ft. Worth Allied Electronics, Inc (1) ouston Allied Electronics, Inc (21) Arrow Electronics (13)64 66 FAI (13)952 0 Future Electronics (13) amilton/allmark (13) Newark (21) Wyle Electronics (13) Richardson PENSTOCK (214) Wyle Electronics (92) San Antonio FAI (210) Newark (210) AUTORIZED DISTRIBUTORS continued UTA Draper Wyle Electronics (01) Salt ake City Allied Electronics, Inc (01) Arrow Electronics (01) FAI (01) Future Electronics (01) amilton/allmark (01) Newark (01) West alley City Wyle Electronics (01) IRGINIA erndon Newark (02) Richmond Newark (04) Springfield Allied Electronics, Inc (03) irginia Beach Allied Electronics, Inc (5) WASINGTON Bellevue Almac Electronics Corp (206) PENSTOCK (206) Bothell Future Electronics (206) Kirkland Newark (206) Redmond amilton/allmark (206)2 000 Wyle Electronics (425) Seattle Allied Electronics, Inc (206) FAI (206) Spokane Newark (509) WISCONSIN Brookfield Arrow Electronics (414) Future Electronics (414) Wyle Electronics (414) Madison Newark (60)2 01 Milwaukee Allied Electronics, Inc (414) FAI (414)92 9 New Berlin amilton/allmark (414)0 200 Wauwatosa Newark (414) CANADA ABERTA Calgary FAI (403) Future Electronics (403) amilton/allmark (00) Newark (00) Edmonton FAI (403)43 5 Future Electronics (403)43 25 amilton/allmark (00) Newark (00) Saskatchewan amilton/allmark (00) BRITIS COUMBIA ancouver Allied Electronics, Inc (604) Arrow Electronics (604) FAI (604) Future Electronics (604) amilton/allmark (604) Newark (00) MANITOBA Winnipeg FAI (204)6 305 Future Electronics (204) amilton/allmark (00) Newark (00) ONTARIO Kanata PENSTOCK (613) ondon Newark (519) Mississauga PENSTOCK (905) Newark (905)60 2 Ottawa Allied Electronics, Inc (613) Arrow Electronics (613) FAI (613) Future Electronics (613)2 100 amilton/allmark (613) Toronto Arrow Electronics (905)60 69 FAI (905)612 9 Future Electronics (905) amilton/allmark (905) Newark (905)60 2 UEBEC Montreal Arrow Electronics (514) FAI (514) Future Electronics (514) amilton/allmark (514) Mt. Royal Newark (514)3 44 uebec City Arrow Electronics (41) FAI (41)62 55 Future Electronics (41) 6666 MOTOROA 212 TIMING SOUTIONS BR1333 Rev 6

219 ARGENTINA Electrocomponentes (5 41) Elko (5 41) AUSTRAIA Avnet SI Electronics (Aust.)..... (61) Farnell (61) eltek Australia Pty. td..... (61) AUSTRIA EB Elektronik (43) Farnell (49) SEI/Elbatex Gmb (43) Spoerle Electronic (43) BEGIUM EB Elektronik (32) Farnell (32) SEI/Belgium (32) Spoerle Electronic (32) BRAZI Future (019) Intertek (011) Karimex (011) Masktrade (011) Panamericana (011) Siletek (011) Tec (011) Teleradio (011) 54 0 BUGARIA Macro Group (359) CINA Future Advanced Electronics td... (52) Avnet WKK Components td (52)2 35 China El. App. Corp. Beijing.... (6) China El. App. Corp. Xiamen.... (6) Nanco Electronics Supply td. (52) or (52) ing Cheng Enterprises td.. (52) CZEC REPUBIC EB Elektronik (420) Spoerle Electronic (420) SEI/Elbatex (420) Macro Group (420) DENMARK Arrow Exatec (45) A/S Avnet EMG (45) EB Elektronik Soeborg..... (45) EB Elektronik Aabyhoej.... (45) Farnell (45) Future Electronics (45) ESTONIA Arrow Field Eesti (32) Avnet Baltronic (32) FINAND Arrow Field OY (35) Avnet EMG OY (35) EB Elektronik (35) Farnell (35) Future Electronics (35) FRANCE Arrow Electronique (33) Avnet EMG (33) EB Elektronik (33) Farnell (33) Future Electronics (33) Newark (33) SEI/Scaib (33) GERMANY Avnet EMG (49) EB Elektronik Gmb (49) Farnell (49) Future Electronics Gmb... (49) SEI/Jermyn Gmb (49) Newark (49) Sasco Semiconductor (49) Spoerle Electronic (49) INTERNATIONA DISTRIBUTORS GREECE EB Elektronik (30) ONG KONG Avnet WKK Components td (52)2 35 Farnell (65) 0200 Future Advanced Electronics td... (52) Nanco Electronics Supply td..... (52) ing Cheng Enterprises td.. (52) UNGARY Future Electronics (36) Macro Group (36) SEI/Elbatex (36) Spoerle Electronic (36) INDIA Max India td INDONESIA P.T. Ometraco (62) IREAND Arrow Electronics (353) EB Elektronik (353) Farnell (353) Future Electronics (353) Macro Group (353) ISRAE Future Israel td (92) ITAY Avnet EMG SR (39) EB Elektronik SR (39) Future Electronics (39) Silverstar td. SpA (39) JAPAN AMSC Co., td Fuji Electronics Co., td Marubun Corporation Nippon Motorola Micro Elec OMRON Corporation Tokyo Electron td KOREA Jung Kwang Semiconductors td iteon Korea td Nasco Co. td ATIA Avnet Baltronic td (31) 2111 Macro Group (31) ITUANIA Macro Group (30) 6493 MAAYSIA Farnell (60) Strong Electronics (60) Ultro Technologies Pte. td.... (65) MEXICO Avnet (3) Dicopel (5) Future (3) Semiconductores Profesionales (5) Steren (5) NETERANDS OAND EB Elektronik (31) Farnell (31) Future Electronics (31) SEI/Benelux B (31) Spoerle Electronics Nieuwegen (31) Spoerle Electronics eldhoven (31) NEW ZEAAND Arrow Components NZ td... (64) Avnet Pacific td (64) Farnell (64) NORWAY Arrow Tahonic A/S (4) A/S Avnet EMG (4) EB Elektronik (4) Future Electronics (4) PIIPPINES Alexan Commercial (63) Ultro Technologies Pte. td.... (65) POAND EB Elektronik (4) Future Electronics (4) Macro Group (4) SEI/Elbatex (4) Spoerle Electronic (4) PORTUGA Amitron Arrow (35) Farnell (44) ROMANIA Macro Group (401) RUSSIA EB Elektronik () Macro Group Moscow.... () Macro Group St. Petersburg.... () SCOTAND EB Elektronik (44) Future (44) SINGAPORE Farnell (65) 0200 Future Electronics (65) Strong Pte. td (65) Uraco Technologies Pte td.... (65) SOAKIA Macro Group (42) SEI/Elbatex (42) 2213 SOENIA EB Elektronik (36) SEI/Elbatex (36) S. AFRICA Avnet ASD (2) Reutech Components (2) SPAIN Amitron Arrow (34) EB Elektronik (34) Farnell (44) SEI/Selco S.A (34) SWEDEN Arrow Th:s (46) Avnet EMG AB (46) EB Elektronik (46) Farnell (46) Future Electronics (46) SWITZERAND EB Elektronik (41) Farnell (41) SEI/Elbatex AG (41) Spoerle Electronic (41) TAIWAN Avnet Mercuries Co., td... (6) Solomon Technology Corp... (6)2 99 Strong Electronics Co. td... (6) TAIAND Sahapiphat td (662) Ultro Technologies Pte. td.... (65) TURKEY EB Elektronik (90) UNITED KINGDOM Arrow Electronics (UK) td.. (44) Avnet EMG (44) EB Elektronik (44) Farnell (44) Future Electronics td (44) Macro Group (44) Newark (44) TIMING SOUTIONS BR1333 Rev MOTOROA

220 UNITED STATES AABAMA untsville (205) AASKA (00) ARIZONA Phoenix (602) CAIFORNIA Calabasas (1) 600 Irvine (14) os Angeles (1) 600 San Diego (619) Sunnyvale (40) COORADO Denver (303) CONNECTICUT Wallingford (203) FORIDA Clearwater (13) Maitland (40) Pompano Beach/Ft. auderdale.... (954) GEORGIA Atlanta (0) IDAO Boise (20) IINOIS Chicago/Schaumburg (4) INDIANA Indianapolis (31) Kokomo (65) IOWA Cedar Rapids (319)3 033 KANSAS Kaas City/Mission (913) MARYAND Columbia (410) MASSACUSETTS Marlborough (50)35 20 Woburn (1) MICIGAN Detroit (24) MINNESOTA Minnetonka (612) MISSOURI St. ouis (314)25 30 NEW JERSEY Fairfield (93) NEW YORK Fairport (16) Fishkill (914) auppauge (516) NORT CAROINA Raleigh (919) OIO Cleveland (440) Columbus/Worthington (614) Dayton (93) OKAOMA Tulsa (91) or (91) OREGON Portland (503) PENNSYANIA Colmar (215) Philadelphia/orsham (215) TENNESSEE Knoxville (423) TEXAS Austin (512) ouston (13) Plano (92) MOTOROA WORDWIDE SAES OFFICES IRGINIA Richmond (04) WASINGTON Bellevue (425) Seattle (toll free) (206) WISCONSIN Milwaukee/Brookfield (414) Field Applicatio Engineering Available Through All Sales Offices CANADA BRITIS COUMBIA ancouver (604) ONTARIO Ottawa (613) Mississauga (905) UEBEC Montreal (514) INTERNATIONA AUSTRAIA Melbourne (61 3)9 011 Sydney (61 2) BRAZI Sao Paulo (011) CINA Beijing Guangzhou Shanghai Tianjin CZEC REPUBIC (420) FINAND elsinki (35) Direct Sales ines (35) (35) FRANCE Paris GERMANY angenhagen/anover (511)60 Munich Nuremberg Sindelfingen Wiesbaden ONG KONG Kwai Fong Tai Po UNGARY (36) INDIA Bangalore ISRAE erzlia ITAY Milan (2)2201 JAPAN Kyusyu Gotanda Nagoya Osaka Sendai Takamatsu Tokyo KOREA Pusan (51) Seoul MAAYSIA Penang (4) MEXICO Chihuahua (14) Mexico City (5) Guadalajara (36) 050 Zapopan Jalisco (36) 050 Marketing (36) Customer Service (36) NETERANDS Best (31) PIIPPINES Manila (63) POAND (4) PUERTO RICO Rio Piedras () RUSSIA () SCOTAND East Kilbride (44) SINGAPORE (65)411 SPAIN Madrid (1) or (1) SWEDEN Solna ()34 00 SWITZERAND Geneva (22) Zurich (1) TAIWAN Taipei (2)1 09 TAIAND Bangkok (2) TURKEY (90) UNITED KINGDOM Aylesbury (296) NORT AMERICA FU INE REPRESENTATIES ARIZONA, Tempe S&S Technologies, Inc (602) CAIFORNIA, oomis Galena Technology Group.... (916) INDIANA, Indianapolis Bailey s Electronics (31)4 995 NEADA, Clark County S&S Technologies, Inc (602) NEADA, Reno Galena Tech. Group (02) NEW MEXICO, Albuquerque S&S Technologies, Inc (505) TEXAS, El Paso S&S Technologies, Inc (915) UTA, Salt ake City Utah Comp. Sales, Inc (01) WASINGTON, Spokane Doug Kenley (509) NORT AMERICA YBRID/MCM COMPONENT SUPPIERS Chip Supply (40) Elmo Semiconductor (1)6 400 Minco Technology abs Inc... (512) Semi Dice Inc (310) MOTOROA 214 TIMING SOUTIONS BR1333 Rev 6

221