MARKING DIAGRAMS LOGIC DIAGRAM PIN ASSIGNMENT ORDERING INFORMATION FUNCTION TABLE DIP 14 N SUFFIX CASE 646 MC74HC4066AN AWLYYWW

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High Performance Silicon Gate CMOS The MC74HC466A utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF channel leakage current.

1 High Performance Silicon Gate CMOS The MC74HC466A utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF channel leakage current. This bilateral switch/ multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power supply range (from V CC to GND). The HC466A is identical in pinout to the metal gate CMOS MC1416 and MC1466. Each device has four independent switches. The device has been designed so the ON resistances (R ON ) are more linear over input voltage than R ON of metal gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. For analog switches with voltage level translators, see the HC4316A. Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power Supply Voltage Range (V CC GND) = 2. to 12. Volts Analog Input Voltage Range (V CC GND) = 2. to 12. Volts Improved Linearity and Lower ON Resistance over Input Voltage than the MC1416 or MC1466 Low Noise Chip Complexity: 44 FETs or 11 Equivalent Gates X A A ON/OFF CONTROL X B B ON/OFF CONTROL X C C ON/OFF CONTROL X D D ON/OFF CONTROL LOGIC DIAGRAM Y A Y B Y C Y D ANALOG OUTPUTS/INPUTS ANALOG INPUTS/OUTPUTS = X A, X B, X C, X D PIN 14 = V CC PIN 7 = GND FUNCTION TABLE On/Off Control State of Input Analog Switch L Off H On MARKING DIAGRAMS A WL, L YY, Y WW, W DIP 14 N SUFFIX CASE 646 SO 14 D SUFFIX CASE 751A TSSOP 14 DT SUFFIX CASE 948G = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION HC4 66A ALYW Device Package Shipping MC74HC466AN DIP 14 2 / Box MC74HC466ADR2 SO / Reel MC74HC466ADT TSSOP / Rail MC74HC466ADTR2 TSSOP / Reel PIN ASSIGNMENT X A Y A Y B X B B ON/OFF CONTROL C ON/OFF CONTROL GND SOEIAJ 14 F SUFFIX CASE 965 MC74HC466AN AWLYYWW 14 1 HC466A AWLYWW X D Y D HC466A ALYW V CC A ON/OFF CONTROL D ON/OFF CONTROL Y C X C Semiconductor Components Industries, LLC, 22 June, 22 Rev. 5 1 Publication Order Number: MC74HC466A/D

2 MAXIMUM RATINGS* SymbolÎÎ Parameter Î Value Unit V CC ÎÎ Positive DC Supply Voltage (Referenced to GND) Î.5 to V V IS ÎÎ Analog Input Voltage (Referenced to GND) Î.5 to V CC +.5 V V in ÎÎ Digital Input Voltage (Referenced to GND) Î.5 to V CC +.5 V I ÎÎ DC Current Into or Out of Any Pin Î ± 25 ma P D ÎÎ Power Dissipation in Still Air, Plastic DIP Î 75 EIAJ/SOIC Package 5 mw TSSOP Package 45 T stg ÎÎ Storage Temperature 65 to + 15 C T L Lead Temperature, 1 mm from Case for 1 Seconds Î (Plastic DIP, SOIC or TSSOP Package) Î 26 C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 1 mw/ C from 65 to 125 C EIAJ/SOIC Package: 7 mw/ C from 65 to 125 C TSSOP Package: 6.1 mw/ C from 65 to 125 C For high frequency or heavy load considerations, see the ON Semiconductor High Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î ÎÎ Symbol Parameter Min Max Unit V CC ÎÎ Positive DC Supply Voltage (Referenced to GND) V V IS Analog Input Voltage (Referenced to GND) GND V CC V V in Digital Input Voltage (Referenced to GND) GND V CC V Î V IO ÎÎ * Static or Dynamic Voltage Across Switch 1.2 V TA ÎÎ Operating Temperature, All Package Types C t r, t f ÎÎ Input Rise and Fall Time, ON/OFF Control ns Inputs (Figure 1) V CC = 2. V ÎÎ 1 V CC = 3. V 6 V CC ÎÎ = 4.5 V 5 V CC = 9. V ÎÎ 4 V CC = 12. V *For voltage drops across the switch greater than 1.2 V (switch on), excessive V CC current may be drawn; i.e., the current out of the switch may contain both V CC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND) Î Guaranteed Limit Î V Î CC 55 to Symbol Parameter Test Conditions V 25 C 85 C 125 C ÎÎ Unit V IH Minimum High Level Voltage R on = Per Spec V Î ON/OFF Control Inputs Î ÎÎ Î ÎÎ Î ÎÎ V IL ÎÎ Maximum Low Level Voltage ÎÎ R on = Per Spec ÎÎ V ON/OFF Control Inputs Î ÎÎ Î ÎÎ I in Maximum Input Leakage Current V in = V CC or GND Î ON/OFF Control Inputs ÎÎ 12. ±.1 ± 1. ÎÎ ± 1. Î A I CC ÎÎ Maximum Quiescent Supply Current (per Package) ÎÎ V in = V CC or GND ÎÎ A V IO = V 12. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range GND (V in or V out ) V CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. NOTE: Information on typical parametric values can be found in the ON Semiconductor High Speed CMOS Data Book (DL129/D)

3 DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND) Guaranteed Limit ÎÎ V CC 55 to Î Symbol Parameter Test Conditions V 25 C 85 C 125 C Unit Î R on Maximum ON Resistance V ÎÎ in = V IH 2. V IS = V CC to GND 3. ÎÎ Î I S 2. ma (Figures 1, 2) ÎÎ ÎÎ Î V in = V IH 2. ÎÎ Î V IS = V CC or GND (Endpoints) 3. ÎÎ I Î S 2. ma (Figures 1, 2) ÎÎ Î R on ÎÎ Maximum Difference in ON V Î in = V IH 2. Resistance Between Any Two V IS = 1/2 (V CC Î GND) Î Channels in the Same Package Î I S 2. ma ÎÎ Î I off Maximum Off Channel Leakage V ÎÎ Current, Any One Channel Î in = V IL A V IO = V CC or GND Î Î Switch Off (Figure 3) Î I on ÎÎ Maximum On Channel Leakage Î V in = V IH ÎÎ A Current, Any One Channel V Î IS = V CC or GND (Figure 4) Î At supply voltage (V CC ) approaching 3 V the analog switch on resistance becomes extremely non linear. Therefore, for low voltage operation, it is recommended that these devices only be used to control digital signals. NOTE: Information on typical parametric values can be found in the ON Semiconductor High Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (C L = 5 pf, ON/OFF Control Inputs: t r = t f = 6 ns) Guaranteed Limit ÎÎ ÎÎ V CC 55 to Î Symbol Parameter V 25 C 85 C 125 C Unit t PLH ÎÎ, Maximum Propagation Delay, Analog Input to Analog Output ns t PHL ÎÎ (Figures 8 and 9) ÎÎ Î ÎÎ t PLZ, ÎÎ Maximum Propagation Delay, ON/OFF Control to Analog Output ÎÎ ns t PHZ (Figures 1 and 11) ÎÎ ÎÎ Î t PZL, Maximum Propagation Delay, ON/OFF Control to Analog Output ns t PZH ÎÎ (Figures 1 and 1 1) ÎÎ ÎÎ ÎÎ C ÎÎ Maximum Capacitance ON/OFF Control Input ÎÎ pf ÎÎ Control Input = GNDÎ Analog I/O ÎÎ Feedthrough NOTES: 1. For propagation delays with loads other than 5 pf, see the ON Semiconductor High Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in the ON Semiconductor High Speed CMOS Data Book (DL129/D). 25 C, V CC = 5. V C PD Power Dissipation Capacitance (Per Switch) (Figure 13)* 15 pf * Used to determine the no load dynamic power consumption: P D = C PD V 2 CC f + I CC V CC. For load considerations, see the ON Semiconductor High Speed CMOS Data Book (DL129/D). 3

4 ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted) Limit* V CC 25 C ÎÎ Symbol Parameter Test Conditions V 54/74HC Unit ÎÎ ÎÎ BW Maximum On Channel Bandwidth f in = 1 MHz Sine Wave MHz ÎÎ or ÎÎ Adjust f in Voltage to Obtain dbm at V OS Minimum Frequency Response Increase f ÎÎ in Frequency Until db Meter Reads 3 db (Figure 5) R L = 5, C L = 1 pf ÎÎ ÎÎ Off Channel Feedthrough Isolation f in Sine Wave ÎÎ (Figure 6) ÎÎ Adjust f in Voltage to Obtain dbm at V IS 9. 5 db f in = 1 khz, R L = 6, C L = 5 pf Î f ÎÎ in = 1. MHz, R L = 5, C L = 1 pf ÎÎ Feedthrough Noise, Control to ÎÎ V in 1 MHz Square Wave (t r = t f = 6 ns) mv PP Switch Adjust R ÎÎ (Figure 7) ÎÎ L at Setup so that I S = A R L = 6, C L = 5 pf ÎÎ ÎÎ R L = 1 k, C L = 1 pf Î Î Crosstalk Between Any Two f Î Switches ÎÎ in Sine Wave db Adjust f in Voltage to Obtain dbm at V IS 9. 7 Î (Figure 12) ÎÎ f in = 1 khz, R L = 6, C L = 5 pf ÎÎ ÎÎ f in = 1. MHz, R L = 5, C L = 1 pf THD ÎÎ Total Harmonic Distortion ÎÎ f in = 1 khz, R L = 1 k, C L = 5 pf % Î (Figure 14) ÎÎ THD = THD Measured THD Source V ÎÎ IS = 4. V PP sine V IS = 8. V PP sine wave 9..6 ÎÎ V IS = 11. V PP sine wave *Guaranteed limits not tested. Determined by design and verified by qualification. 4

5 2 V C +125 C 55 C V is, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1a. Typical On Resistance, V CC = 2. V V C C 2 55 C V is, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1b. Typical On Resistance, V CC = 3. V 4.5 V C C 55 C V is, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1c. Typical On Resistance, V CC = 4.5 V 5

6 6 V C +125 C 55 C V is, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1d. Typical On Resistance, V CC = 6. V 9V C +125 C 55 C V is, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1e. Typical On Resistance, V CC = 9. V V C C 55 C V is, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 1f. Typical On Resistance, V CC = 12. V 6

7 Figure 2. On Resistance Test Set Up Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set Up Figure 4. Maximum On Channel Leakage Current, Test Set Up 7

8 *Includes all probe and jig capacitance. Figure 5. Maximum On Channel Bandwidth Test Set Up *Includes all probe and jig capacitance. Figure 6. Off Channel Feedthrough Isolation, Test Set Up *Includes all probe and jig capacitance. Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set Up Figure 8. Propagation Delays, Analog In to Analog Out 8

9 Figure 9. Propagation Delay Test Set Up *Includes all probe and jig capacitance. Figure 1. Propagation Delay, ON/OFF Control to Analog Out *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set Up *Includes all probe and jig capacitance. Figure 12. Crosstalk Between Any Two Switches, Test Set Up *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set Up Figure 14. Total Harmonic Distortion, Test Set Up 9

10 Figure 15. Plot, Harmonic Distortion APPLICATION INFORMATION The ON/OFF Control pins should be at V CC or GND logic levels, V CC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to V CC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages V CC and GND. The positive peak analog voltage should not exceed V CC. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between V CC and GND is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak to peak can be controlled. When voltage transients above V CC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (Mosorb is an acronym for high current surge protectors). Mosorbs are fast turn on devices ideally suited for precise DC protection with no inherent wear out mechanism. Figure V Application Figure 17. Transient Suppressor Application 1

11 a. Using Pull-Up Resistors b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface Figure 19. TTL/NMOS to CMOS Level Converter Analog Signal Peak to Peak Greater than 5 V (Also see HC4316A) Figure 2. 4 Input Multiplexer Figure 21. Sample/Hold Amplifier 11

12 PACKAGE DIMENSIONS B PDIP 14 N SUFFIX CASE ISSUE M T N A F L C K J H G D 14 PL M 12

13 PACKAGE DIMENSIONS SOIC 14 D SUFFIX CASE 751A 3 ISSUE F 14 A 1 7 G D 14 PL 8 B K C P 7 PL R X 45 M J F 13

14 PACKAGE DIMENSIONS TSSOP 14 DT SUFFIX CASE 948G 1 ISSUE O L T 2X L/2 PIN 1 IDENT. D C G 14X K REF A V B U H N J J1 N F DETAIL E DETAIL E K K1 ÇÇ ÉÉ M SECTION N N W 14

15 Z D e b E A H E A 1 VIEW P PACKAGE DIMENSIONS M SO EIAJ 14 F SUFFIX CASE ISSUE O L E Q 1 L DETAIL P c 15

16 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com N. American Technical Support: Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r14525@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 16 MC74HC466A/D

High Performance Silicon Gate CMOS

High Performance Silicon Gate CMOS The MC74HC4316A utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF channel leakage current. This bilateral switch/multiplexer/