MC74HC4066A. Quad Analog Switch/ Multiplexer/Demultiplexer. High Performance Silicon Gate CMOS

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MC4HC466A Quad Analog Switch/ Multiplexer/Demultiplexer High Performance Silicon Gate CMOS The MC4HC466A utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances,

1 MC4HC466A Quad Analog Switch/ Multiplexer/Demultiplexer High Performance Silicon Gate CMOS The MC4HC466A utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF channel leakage current. This bilateral switch/ multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power supply range (from to GND). The HC466A is identical in pinout to the metal gate CMOS MC6 and MC66. Each device has four independent switches. The device has been designed so the ON resistances (R ON ) are more linear over input voltage than R ON of metal gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. For analog switches with voltage level translators, see the HC436A. Features Fast Switching and Propagation Speeds High ON/OFF Output oltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power Supply oltage Range ( GND) = 2. to 2. Analog Input oltage Range ( GND) = 2. to 2. Improved Linearity and Lower ON Resistance over Input oltage than the MC6 or MC66 Low Noise Chip Complexity: 44 FETs or Equivalent Gates Pb Free Packages are Available PDIP N SUFFIX CASE 646 SOIC D SUFFIX CASE 5A TSSOP DT SUFFIX CASE 948G SOEIAJ F SUFFIX CASE 965 MARKING DIAGRAMS MC4HC466AN AWLYYWWG HC466AG AWLYWW HC4 66A ALYW 4HC466A ALYWG A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 26 October, 26 Rev. 8 Publication Order Number: MC4HC466A/D

2 MC4HC466A PIN ASSIGNMENT X A Y A 2 3 A ON/OFF Y B 3 2 D ON/OFF X B 4 X D B ON/OFF 5 Y D C ON/OFF 6 9 Y C GND 8 X C FUNCTION TABLE On/Off Control State of Input Analog Switch L Off H On X A A ON/OFF X B B ON/OFF X C C ON/OFF X D D ON/OFF LOGIC DIAGRAM Y A Y B Y C Y D ANALOG OUTPUTS/S ANALOG S/OUTPUTS = X A, X B, X C, X D PIN = PIN = GND ORDERING INFORMATION MC4HC466AN MC4HC466ANG Device Package Shipping PDIP PDIP (Pb Free) 25 Units / Rail MC4HC466AD MC4HC466ADG SOIC SOIC (Pb Free) 55 Units / Rail MC4HC466ADR2 MC4HC466ADR2G MC4HC466ADTR2 MC4HC466ADTR2G MC4HC466AFEL MC4HC466AFELG SOIC SOIC (Pb Free) TSSOP * TSSOP * SOEIAJ SOEIAJ (Pb Free) 25 / Tape & Reel 2 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *This package is inherently Pb Free. 2

3 MC4HC466A MAXIMUM RATINGS SymbolÎÎ Parameter ÎÎ alue Unit ÎÎ Positive DC Supply oltage (Referenced to GND) ÎÎ.5 to +. IS ÎÎ Analog Input oltage (Referenced to GND) ÎÎ.5 to +.5 in ÎÎ Digital Input oltage (Referenced to GND) ÎÎ.5 to +.5 I ÎÎ DC Current Into or Out of Any Pin ÎÎ ± 25 ma P D ÎÎ Power Dissipation in Still Air, Plastic DIP ÎÎ 5 mw EIAJ/SOIC Package 5 TSSOP Package 45 T stg Î Storage Temperature 65 to + 5 C T L Î Lead Temperature, mm from Case for Seconds C Î (Plastic DIP, SOIC or TSSOP Package) ÎÎ 26 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating Plastic DIP: mw/ C from 65 to 25 C EIAJ/SOIC Package: mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load considerations, see the ON Semiconductor High Speed CMOS Data Book (DL29/D). RECOMMENDED OPERATING CONDITIONS Î ÎÎ Symbol Parameter Min Max ÎÎ Unit Positive DC Supply oltage (Referenced to GND) ÎÎ IS Analog Input oltage (Referenced to GND) GND CC in Î Digital Input oltage (Referenced to GND) GND CC IO * Static or Dynamic oltage Across Switch.2 ÎÎ T A Operating Temperature, All Package Types ÎÎ C t r, t f Input Rise and Fall Time, ON/OFF Control ns Î Inputs (Figure ) = 2. ÎÎ = 3. ÎÎ 6 CC = = 9. ÎÎ 4 = 2. ÎÎ 25 *For voltage drops across the switch greater than.2 (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC ELECTRICAL CHARACTERISTIC Digital Section (oltages Referenced to GND) Î Guaranteed Limit 55 to Symbol Parameter Test Conditions 25 C 85 C 25 C Unit IH Î Minimum High Level oltage R on = Per Spec Î ON/OFF Control Inputs IL ÎÎ Maximum Low Level oltage R on = Per Spec ON/OFF Control Inputs Î I in Î Maximum Input Leakage Current in = or GND 2. Î ON/OFF Control Inputs ±. ±. ÎÎ ±. A I CC ÎÎ Maximum Quiescent Supply Current in = or GND A (per Package) IO = 2. 4 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. NOTE: Information on typical parametric values can be found in the ON Semiconductor High Speed CMOS Data Book (DL29/D)

4 MC4HC466A DC ELECTRICAL CHARACTERISTICS Analog Section (oltages Referenced to GND) Guaranteed Limit 55 to Symbol Parameter Test Conditions 25 C 85 C 25 C Unit Î R on Maximum ON Resistance Î in = IH 2. IS = to GND 3. I S 2. ma (Figures, 2) in = IH 2. IS = or GND 3. (Endpoints) I S 2. ma (Figures, 2) Î R on ÎÎ Maximum Difference in ON in = IH 2. Resistance Between Any Two IS = /2 ( GND) Î Channels in the Same Package I S 2. ma Î I off Maximum Off Channel Leakage ÎÎ Current, Any One Channel in = IL A IO = or GND Switch Off (Figure 3) I on ÎÎ Maximum On Channel Leakage in = IH 2. Current, Any One Channel IS = or GND (Figure 4)..5. A At supply voltage ( ) approaching 3 the analog switch on resistance becomes extremely non linear. Therefore, for low voltage operation, it is recommended that these devices only be used to control digital signals. NOTE: Information on typical parametric values can be found in the ON Semiconductor High Speed CMOS Data Book (DL29/D). AC ELECTRICAL CHARACTERISTICS (C L = 5 pf, ON/OFF Control Inputs: t r = t f = 6 ns) Î Guaranteed Limit Î SymbolÎ Parameter CC 55 to 25 C 85 C 25 C Unit t PLH, Î Maximum Propagation Delay, Analog Input to Analog Output ns t PHL Î (Figures 8 and 9) Î t PLZ, Maximum Propagation Delay, ON/OFF Control to Analog Output ns t PHZ ÎÎ (Figures and ) Î t PZL, Î Maximum Propagation Delay, ON/OFF Control to Analog Output ns t PZH Î (Figures and ) C Î Maximum Capacitance ON/OFF Control Input pf Control Input = GND Î Analog I/O 35 Feedthrough NOTES:. For propagation delays with loads other than 5 pf, see the ON Semiconductor High Speed CMOS Data Book (DL29/D). 2. Information on typical parametric values can be found in the ON Semiconductor High Speed CMOS Data Book (DL29/D). 25 C, = 5. C PD Power Dissipation Capacitance (Per Switch) (Figure 3)* 5 pf * Used to determine the no load dynamic power consumption: P D = C PD 2 CC f + I CC. For load considerations, see the ON Semiconductor High Speed CMOS Data Book (DL29/D). 4

5 MC4HC466A ADDITIONAL APPLICATION CHARACTERISTICS (oltages Referenced to GND Unless Noted) Limit* CC 25 C ÎÎ Symbol Parameter Test Conditions 54/4HC Unit ÎÎ ÎÎ BW Maximum On Channel Bandwidth or f in = MHz Sine Wave MHz ÎÎ Minimum Frequency Response ÎÎ Adjust f in oltage to Obtain dbm at OS 9. 6 (Figure 5) Increase f ÎÎ in Frequency Until db Meter Reads 3 db 2. 6 R L = 5, C L = pf ÎÎ Off Channel Feedthrough Isolation f in Sine Wave db Î (Figure 6) ÎÎ Adjust f in oltage to Obtain dbm at IS 9. 5 f Î in = khz, R L = 6, C L = 5 pf 2. 5 Î f ÎÎ in =. MHz, R L = 5, C L = pf ÎÎ Feedthrough Noise, Control to ÎÎ in MHz Square Wave (t r = t f = 6 ns) m PP Switch Adjust R ÎÎ L at Setup so that I S = A 9. 3 (Figure ) R L = 6, C L = 5 pf 2. 2 ÎÎ ÎÎ R L = k, C L = pf Î Crosstalk Between Any Two f Î Switches ÎÎ in Sine Wave 4.5 db Adjust f in oltage to Obtain dbm at IS 9. Î (Figure 2) ÎÎ f in = khz, R L = 6, C L = 5 pf 2. ÎÎ f ÎÎ in =. MHz, R L = 5, C L = pf THD ÎÎ Total Harmonic Distortion ÎÎ f in = khz, R L = k, C L = 5 pf % Î (Figure ) ÎÎ THD = THD Measured THD Source ÎÎ IS = 4. PP sine wave 4.5. IS = 8. PP sine wave 9..6 ÎÎ IS =. PP sine wave 2..4 *Guaranteed limits not tested. Determined by design and verified by qualification. 5

6 MC4HC466A C +25 C 55 C is, OLTAGE (OLTS), REFERENCED TO GROUND Figure a. Typical On Resistance, = C C 2 55 C is, OLTAGE (OLTS), REFERENCED TO GROUND Figure b. Typical On Resistance, = C C 55 C is, OLTAGE (OLTS), REFERENCED TO GROUND Figure c. Typical On Resistance, = 4.5 6

7 MC4HC466A C +25 C 55 C is, OLTAGE (OLTS), REFERENCED TO GROUND Figure d. Typical On Resistance, = C +25 C 55 C is, OLTAGE (OLTS), REFERENCED TO GROUND Figure e. Typical On Resistance, = C +25 C 55 C is, OLTAGE (OLTS), REFERENCED TO GROUND Figure f. Typical On Resistance, = 2.

8 MC4HC466A PLOTTER PROGRAMMABLE POWER SUPPLY MINI COMPUTER DC ANALYZER + DEICE UNDER TEST ANALOG IN COMMON OUT GND Figure 2. On Resistance Test Set Up GND A OFF GND A ON N/C IL IH Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set Up Figure 4. Maximum On Channel Leakage Current, Test Set Up 8

9 MC4HC466A OS IS OS f in ON. F C L * db METER f in OFF. F R L C L * db METER *Includes all probe and jig capacitance. Figure 5. Maximum On Channel Bandwidth Test Set Up *Includes all probe and jig capacitance. Figure 6. Off Channel Feedthrough Isolation, Test Set Up /2 /2 R L R L OS OFF/ON I S GND in MHz t r = t f = 6 ns *Includes all probe and jig capacitance. C L * ANALOG IN t PLH ANALOG OUT 5% 5% t PHL GND Figure. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set Up Figure 8. Propagation Delays, Analog In to Analog Out 9

10 MC4HC466A ANALOG IN ON Figure 9. Propagation Delay Test Set Up *Includes all probe and jig capacitance. ANALOG OUT C L * TEST POINT ANALOG OUT 9% 5% % t r t f CC 5% 5% t PZL t PZH t PLZ t PHZ % 9% Figure. Propagation Delay, ON/OFF Control to Analog Out GND HIGH IMPEDANCE OL OH HIGH IMPEDANCE 2 2 POSITIONММ WHEN TESTING t PHZ AND t PZH POSITIONММWHEN 2 TESTING t PLZ AND t PZL ON/OFF k C L * TEST POINT f in. F R L IS ON OFF OR GND R L C L * OS R L C L * R L /2 /2 *Includes all probe and jig capacitance. Figure. Propagation Delay Test Set Up /2 *Includes all probe and jig capacitance. Figure 2. Crosstalk Between Any Two Switches, Test Set Up A IS OS N/C OFF/ON N/C f in. F ON R L C L * TO DISTORTION METER ON/OFF /2 *Includes all probe and jig capacitance. Figure 3. Power Dissipation Capacitance Test Set Up Figure. Total Harmonic Distortion, Test Set Up

11 MC4HC466A dbm FUNDAMENTAL FREQUENCY DEICE SOURCE. 2. FREQUENCY (khz) Figure 5. Plot, Harmonic Distortion 3. APPLICATION INFORMATION The ON/OFF Control pins should be at or GND logic levels, being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages and GND. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between and GND is twelve volts. Therefore, using the configuration in Figure 6, a maximum analog signal of twelve volts peak to peak can be controlled. When voltage transients above and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure. These diodes should be small signal, fast turn on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (Mosorb is an acronym for high current surge protectors). Mosorbs are fast turn on devices ideally suited for precise DC protection with no inherent wear out mechanism. = ANALOG I/O ON ANALOG O/I + 2 D x D x ON 6 D x D x OTHER S ( OR GND) OTHER S ( OR GND) Figure 6. 2 Application Figure. Transient Suppressor Application

12 MC4HC466A ANALOG SIGNALS ANALOG SIGNALS ANALOG SIGNALS ANALOG SIGNALS LSTTL/ NMOS R* R* R* R* 5 HC466A LSTTL/ NMOS HCT BUFFER 5 HC466A 6 S 6 S 5 5 R* = 2 TO k a. Using Pull-Up Resistors b. Using HCT Buffer Figure 8. LSTTL/NMOS to HCMOS Interface DD = 5 = 5 TO ANALOG SIGNALS MC HC466A S ANALOG SIGNALS Figure 9. TTL/NMOS to CMOS Level Converter Analog Signal Peak to Peak Greater than 5 (Also see HC436A) CHANNEL 4 OF 4 SWITCHES CHANNEL 3 CHANNEL 2 OF 4 SWITCHES OF 4 SWITCHES COMMON I/O CHANNEL OF 4 SWITCHES OF 4 SWITCHES + LF356 OR EQUIALENT OUTPUT. F S Figure 2. 4 Input Multiplexer Figure 2. Sample/Hold Amplifier 2

13 MC4HC466A PACKAGE DIMENSIONS PDIP CASE ISSUE P 8 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, LING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T N SEATING PLANE A INCHES MILLIMETERS DIM MIN MAX MIN MAX A B F L C D C F G. BSC 2.54 BSC H J K K J L M H G D PL M N (.5) M 3

14 MC4HC466A PACKAGE DIMENSIONS SOIC CASE 5A 3 ISSUE H T SEATING PLANE G A 8 D PL B K P PL C.25 (.) M T B S A S.25 (.) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, LING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.2 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 45 F DIM MIN MAX MIN MAX A B C D M J F G.2 BSC.5 BSC J K M P R SOLDERING FOOTPRINT* X.58 X.4 X.52.2 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

15 MC4HC466A PACKAGE DIMENSIONS TSSOP CASE 948G ISSUE B.5 (.6) T.5 (.6) T L. (.4) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C X K REF. (.4) M T U S S N 8.25 (.) M B U A G H N J J F DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N DETAIL E NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, LING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED.5 (.6) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED.25 (.) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C.2.4 D F G.65 BSC.26 BSC H J J W K K L 6.4 BSC.252 BSC M 8 8 SOLDERING FOOTPRINT*.6.65 PITCH X.36 X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 5

16 MC4HC466A PACKAGE DIMENSIONS SOEIAJ CASE 965 ISSUE A L E 8 Q E H E M L Z DETAIL P D IEW P e A c b A.3 (.5) M. (.4) NOTES: М. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 982. М 2. LING DIMENSION: MILLIMETER. М 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED.5 (.6) PER SIDE. М 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. М 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE.46 (.8). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.2 BSC.5 BSC H E L E M Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 82 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC4HC466A/D

MARKING DIAGRAMS LOGIC DIAGRAM PIN ASSIGNMENT ORDERING INFORMATION FUNCTION TABLE DIP 14 N SUFFIX CASE 646 MC74HC4066AN AWLYYWW

MARKING DIAGRAMS LOGIC DIAGRAM PIN ASSIGNMENT ORDERING INFORMATION FUNCTION TABLE DIP 14 N SUFFIX CASE 646 MC74HC4066AN AWLYYWW High Performance Silicon Gate CMOS The MC74HC466A utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF channel leakage current. This bilateral switch/