MC74HC4046A. Phase Locked Loop. High Performance Silicon Gate CMOS

Transcription

1 Phase Locked Loop High Performance Silicon Gate CMOS The MC74HC446A is similar in function to the MC446 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC446A phase locked loop contains three phase comparators, a voltage controlled oscillator (CO) and unity gain op amp DEM OUT. The comparators have two common signal inputs, COMP IN, and SIG IN. Input SIG IN and COMP IN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator (an exclusive OR gate) provides a digital error signal PC OUT and maintains 9 degrees phase shift at the center frequency between SIG IN and COMP IN signals (both at 5% duty cycle). Phase comparator 2 (with leading edge sensing logic) provides digital error signals PC2 OUT and PCP OUT and maintains a degree phase shift between SIG IN and COMP IN signals (duty cycle is immaterial). The linear CO produces an output signal CO OUT whose frequency is determined by the voltage of input CO IN signal and the capacitor and resistors connected to pins CA, CB, R and R2. The unity gain op amp output DEM OUT with an external resistor is used where the CO IN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the CO and all op amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage to frequency conversion and motor speed control. Features Output Drive Capability: LSTTL Loads Low Power Consumption Characteristic of CMOS Devices Operating Speeds Similar to LSTTL Wide Operating oltage Range: to Low Input Current:. A Maximum (except SIG IN and COMP IN ) In Compliance with the Requirements Defined by JEDEC Standard No. 7A Low Quiescent Current: 8 A Maximum (CO disabled) High Noise Immunity Characteristic of CMOS Devices Diode Protection on all Inputs Chip Complexity: 279 FETs or 7 Equivalent Gates Pb Free Packages are Available* PDIP N SUFFIX CASE 648 SOIC D SUFFIX CASE 75B TSSOP DT SUFFIX CASE 948F SOEIAJ F SUFFIX CASE 966 MARKING DIAGRAMS MC74HC446AN AWLYYWWG HC446AG AWLYWW HC4 46A ALYW A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb Free Package = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. 74HC446A ALYWG *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 25 June, 25 Rev. 8 Publication Order Number: MC74HC446A/D

2 Pin No. Symbol Name and Function PCP OUT PC OUT COMP IN CO OUT INH CA CB GND CO IN DEM OUT R R2 PC2 OUT SIG IN PC3 OUT CC Phase Comparator Pulse Output Phase Comparator Output Comparator Input CO Output Inhibit Input Capacitor C Connection A Capacitor C Connection B Ground ( ) SS CO Input Demodulator Output Resistor R Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply oltage PCP out PC out 2 5 CC PC3 out COMP in 3 4 SIG in CO out 4 3 PC2 out INH 5 2 R2 CA 6 R CB 7 DEM out GND 8 9 CO in Figure. Pin Assignment ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Symbol Parameter alue Unit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ CC DC Supply oltage (Referenced to GND).5 to + 7. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ in DC Input oltage (Referenced to GND).5 to CC +.5 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ out DC Output oltage (Referenced to GND).5 to CC +.5 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ I in DC Input Current, per Pin ± 2 ma ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ I out DC Output Current, per Pin ± 25 ma ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ I CC DC Supply Current, CC and GND Pins ± 5 ma ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ P ÎÎÎÎ D Power Dissipation in Still Air Plastic DIP 75 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SOIC Package ÎÎÎÎÎ 5 ÎÎÎ mw ÎÎÎÎ T stg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature ÎÎÎÎÎ 65 to + 5ÎÎÎ C ÎÎÎÎ T L ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature, mm from Case for Seconds ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Plastic DIP and SOIC Package ÎÎÎÎÎ 26 ÎÎÎ C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating Plastic DIP: mw/ C from 65 to 25 C SOIC Package: 7 mw/ C from 65 to 25 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ CC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply oltage (Referenced to GND) ÎÎÎ Min ÎÎÎ Max ÎÎÎ Unit ÎÎÎ ÎÎÎ CC DC Supply oltage (Referenced to GND) NON CO ÎÎÎÎ in, outîîîîîîîîîîîîîî DC Input oltage, Output oltage (Referenced to GND) ÎÎÎ ÎÎÎ CC ÎÎÎ T ÎÎÎÎ A Operating Temperature, All Package Types 55 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ + 25 ÎÎÎ C t ÎÎÎÎ r, t f Input Rise and Fall Time ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ CC = ns (Pin 5) CC ÎÎÎ ÎÎÎ = 5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ CC = ÎÎÎ ÎÎÎ 4ÎÎÎ This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. 2

3 [Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions CC 55 to 25 C 85 C 25 C Unit IH Minimum High Level Input oltage DC Coupled SIG IN, COMP IN out = or CC I out 2 A IL Maximum Low Level Input oltage DC Coupled SIG IN, COMP IN out = or CC I out 2 A OH Minimum High Level Output oltage PCP OUT, PCn OUT in = IH or IL I out 2 A in = IH or IL I out 4. ma I out 5.2 ma OL Maximum Low Level Output oltage Qa Qh PCP OUT, PCn OUT out = or CC I out 2 A I in I OZ I CC in = IH or IL I out 4. ma I out 5.2 ma Maximum Input Leakage Current SIG IN, COMP IN in = CC or GND Maximum Three State Leakage Current PC2 OUT Maximum Quiescent Supply Current (per Package) (CO disabled) Pins 3, 5 and 4 at CC Pin 9 at GND; Input Leakage at Pins 3 and 4 to be excluded Output in High Impedance State in = IH or IL out = CC or GND in = CC or GND I out = A ± ± 7. ± 8. ± ± 4. ± 9. ± 2 ± ± 5. ±. ± 27. ± 45. A ±.5 ± 5. ± A 4. 4 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). [Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS (C L = 5 pf, Input t r = t f = ns) Guaranteed Limit Symbol Parameter CC 55 to 25 C 85 C 25 C Unit t PLH, t PHL Maximum Propagation Delay, SIG IN /COMP IN to PC OUT (Figure 2) ns t PLH, t PHL Maximum Propagation Delay, SIG IN /COMP IN to PCP OUT (Figure 2) ns t PLH, t PHL Maximum Propagation Delay, SIG IN /COMP IN to PC3 OUT (Figure 2) ns t PLZ, t PHZ Maximum Propagation Delay, SIG IN /COMP IN Output Disable Time to PC2 OUT (Figures 3 and 4) ns t PZH, t PZL Maximum Propagation Delay, SIG IN /COMP IN Output Enable Time to PC2 OUT (Figures 3 and 4) ns t TLH, t THL Maximum Output Transition Time (Figure 2) ns 3

4 [CO Section] DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions IH Minimum High Level Input oltage INH out = or CC I out 2 A CC 55 to 25 C 85 C 25 C Unit IL Maximum Low Level Input oltage INH out = or CC I out 2 A OH Minimum High Level Output oltage CO OUT in = IH or IL I out 2 A in = IH or IL I out 4. ma I out 5.2 ma OL Maximum Low Level Output oltage CO OUT out = or CC I out 2 A I in CO IN in = IH or IL I out 4. ma I out 5.2 ma Maximum Input Leakage in = CC or GND.. A Current INH, CO IN Operating oltage Range at CO IN over the range specified for R; For linearity see Fig. 5A, Parallel value of R and R2 should be > 2.7 k INH = IL R Resistor Range R2 C Capacitor Range Min Max Min Max Min Max No Limit k pf [CO Section] AC ELECTRICAL CHARACTERISTICS (C L = 5 pf, Input t r = t f = ns) Symbol f/t fo Frequency Stability with Temperature Changes (Figure 4A, B, C) CO Center Frequency (Duty Factor = 5%) (Figure 5A, B, C, D) Parameter CC fco CO Frequency Linearity CO Duty Factor at CO OUT Guaranteed Limit 55 to 25 C 85 C 25 C Min Max Min Max Min Max 3 3 Unit %/K MHz See Figures A, B, C % Typical 5% % 4

5 [Demodulator Section] DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditions RS Resistor Range At RS > k the Leakage Current can Influence DEM OUT OFF RD Offset oltage i = CO IN = /2 CC ; CO IN to DEM OUT alues taken over RS Range. CC Dynamic Output DEM OUT = /2 CC Resistance at DEM OUT Guaranteed Limit 55 to 25 C 85 C 25 C Min Max Min Max Min Max See Figure 3 Typical 25 Unit k m ORDERING INFORMATION Device Package Shipping MC74HC446AN PDIP 2 Units / Box MC74HC446ANG PDIP (Pb Free) 2 Units / Box MC74HC446AD SOIC 48 Units / Rail MC74HC446ADG SOIC (Pb Free) 48 Units / Rail MC74HC446ADR2 SOIC 25 Units / Reel MC74HC446ADR2G SOIC (Pb Free) 25 Units / Reel MC74HC446ADT TSSOP * 96 Units / Rail MC74HC446ADTG TSSOP * 96 Units / Rail MC74HC446ADTR2 TSSOP * 25 Units / Reel MC74HC446ADTR2G TSSOP * 25 Units / Reel MC74HC446AF SOEIAJ 5 Units / Rail MC74HC446AFG SOEIAJ (Pb Free) 5 Units / Rail MC74HC446AFEL SOEIAJ 2 Units / Reel MC74HC446AFELG SOEIAJ (Pb Free) 2 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *This package is inherently Pb Free. 5

6 SWITCHING WAEFORMS SIG IN, COMP IN INPUTS 5% CC SIG IN INPUT 5% CC GND PCP OUT, PC OUT PC3 OUT OUTPUTS t THL t PHL 9% 5% % t PLH t TLH GND COMP IN INPUT PC2 OUT OUTPUT t PZH 5% 5% t PHZ 9% CC GND OH HIGH IMPEDANCE Figure 2. Figure 3. CC SIG IN INPUT COMP IN INPUT PC2 OUT OUTPUT 5% t PZL 5% 5% t PLZ % GND CC GND HIGH IMPEDANCE OL DEICE UNDER TEST OUTPUT TEST POINT C L * *INCLUDES ALL PROBE AND JIG CAPACITANCE Figure 4. Figure 5. Test Circuit 6

7 DETAILED CIRCUIT DESCRIPTION oltage Controlled Oscillator/Demodulator Output The CO requires two or three external components to operate. These are R, R2, C. Resistor R and Capacitor C are selected to determine the center frequency of the CO (see typical performance curves Figure 5). R2 can be used to set the offset frequency with volts at CO input. For example, if R2 is decreased, the offset frequency is increased. If R2 is omitted the CO range is from Hz. The effect of R2 is shown in Figure 25, typical performance curves. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/hz) is decreased. Thus, for a narrow lock range, large swings on the CO input will cause less frequency variation. Internally, the resistors set a current in a current mirror, as shown in Figure 6. The mirrored current drives one side of the capacitor. Once the voltage across the capacitor charges up to ref of the comparators, the oscillator logic flips the capacitor which causes the mirror to charge the opposite side of the capacitor. The output from the internal logic is then taken to CO output (Pin 4). The input to the CO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filters design. In order to make signals at the CO input accessible without degrading the loop performance, the CO input voltage is buffered through a unity gain Op amp to Demod Output. This Op amp can drive loads of 5K ohms or more and provides no loading effects to the CO input voltage (see Figure 3). An inhibit input is provided to allow disabling of the CO and all Op amps (see Figure 6). This is useful if the internal CO is not being used. A logic high on inhibit disables the CO and all Op amps, minimizing standby power consumption. 2 REF + _ I R 2 CURRENT MIRROR I + I 2 = I 3 CO IN 9 + _ I 2 4 CO OUT R I 3 DEMOD OUT + _ C (EXTERNAL) 6 7 ref + + INH 5 Figure 6. Logic Diagram for CO The output of the CO is a standard high speed CMOS output with an equivalent LS TTL fan out of. The CO output is approximately a square wave. This output can either directly feed the COMP IN of the phase comparators or feed external prescalers (counters) to enable frequency synthesis. 7

8 Phase Comparators All three phase comparators have two inputs, SIG IN and COMP IN. The SIG IN and COMP IN have a special DC bias network that enables AC coupling of input signals. If the signals are not AC coupled, standard 74HC input levels are required. Both input structures are shown in Figure 7. The outputs of these comparators are essentially standard 74HC outputs (comparator 2 is TRI STATEABLE). In normal operation CC and ground voltage levels are fed to the loop filter. This differs from some phase detectors which supply a current to the loop filter and should be considered in the design. (The MC446 also provides a voltage). CC CC SIG IN 4 PC2 OUT 3 CC COMP IN 3 PCP OUT PC3 OUT 5 PC OUT 2 Figure 7. Logic Diagram for Phase Comparators Phase Comparator This comparator is a simple XOR gate similar to the 74HC86. Its operation is similar to an overdriven balanced modulator. To maximize lock range the input frequencies must have a 5% duty cycle. Typical input and output waveforms are shown in Figure 8. The output of the phase detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will lock onto if initially out of lock is defined as the capture range. The capture range for phase detector is dependent on the loop filter design. The capture range can be as large as the lock range, which is equal to the CO frequency range. To see how the detector operates, refer to Figure 8. When two square wave signals are applied to this comparator, an output waveform (whose duty cycle is dependent on the phase difference between the two signals) results. As the phase difference increases, the output duty cycle increases and the voltage after the loop filter increases. In order to achieve lock when the PLL input frequency increases, the CO input voltage must increase and the phase difference between COMP IN and SIG IN will increase. At an input frequency equal to f min, the CO input is at. This requires the phase detector output to be grounded; hence, the two input signals must be in phase. When the input frequency is f max, the CO input must be CC and the phase detector inputs must be 8 degrees out of phase. SIG IN COMP IN PC OUT CO IN CC GND Figure 8. Typical Waveforms for PLL Using Phase Comparator The XOR is more susceptible to locking onto harmonics of the SIG IN than the digital phase detector 2. For instance, a signal 2 times the CO frequency results in the same output duty cycle as a signal equal to the CO frequency. The difference is that the output frequency of the 2f example is twice that of the other example. The loop filter and CO range should be designed to prevent locking on to harmonics. 8

9 Phase Comparator 2 This detector is a digital memory network. It consists of four flip flops and some gating logic, a three state output and a phase pulse output as shown in Figure 6. This comparator acts only on the positive edges of the input signals and is independent of duty cycle. Phase comparator 2 operates in such a way as to force the PLL into lock with phase difference between the CO output and the signal input positive waveform edges. Figure 8 shows some typical loop waveforms. First assume that SIG IN is leading the COMP IN. This means that the CO s frequency must be increased to bring its leading edge into proper phase alignment. Thus the phase detector 2 output is set high. This will cause the loop filter to charge up the CO input, increasing the CO frequency. Once the leading edge of the COMP IN is detected, the output goes TRI STATE holding the CO input at the loop filter voltage. If the CO still lags the SIG IN then the phase detector will again charge up the CO input for the time between the leading edges of both waveforms. If the CO leads the SIG IN then when the leading edge of the CO is seen; the output of the phase comparator goes low. This discharges the loop filter until the leading edge of the SIG IN is detected at which time the output disables itself again. This has the effect of slowing down the CO to again make the rising edges of both waveforms coincidental. When the PLL is out of lock, the CO will be running either slower or faster than the SIG IN. If it is running slower the phase detector will see more SIG IN rising edges and so the output of the phase comparator will be high a majority of the time, raising the CO s frequency. Conversely, if the CO is running faster than the SIG IN, the output of the detector will be low most of the time and the CO s output frequency will be decreased. As one can see, when the PLL is locked, the output of phase comparator 2 will be disabled except for minor corrections at the leading edge of the waveforms. When PC 2 is TRI STATED, the PCP output is high. This output can be used to determine when the PLL is in the locked condition. This detector has several interesting characteristics. Over the entire CO frequency range there is no phase difference between the COMP IN and the SIG IN. The lock range of the PLL is the same as the capture range. Minimal power was consumed in the loop filter since in lock the detector output is a high impedance. When no SIG IN is present, the detector will see only CO leading edges, so the comparator output will stay low, forcing the CO to f min. Phase comparator 2 is more susceptible to noise, causing the PLL to unlock. If a noise pulse is seen on the SIG IN, the comparator treats it as another positive edge of the SIG IN and will cause the output to go high until the CO leading edge is seen, potentially for an entire SIG IN period. This would cause the CO to speed up during that time. When using PC, the output of that phase detector would be disturbed for only the short duration of the noise spike and would cause less upset. Phase Comparator 3 This is a positive edge triggered sequential phase detector using an RS flip flop as shown in Figure 7. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIG IN and COMP IN are not important. It has some similar characteristics to the edge sensitive comparator. To see how this detector works, assume input pulses are applied to the SIG IN and COMP IN s as shown in Figure. When the SIG IN leads the COMP IN, the flop is set. This will charge the loop filter and cause the CO to speed up, bringing the comparator into phase with the SIG IN. The phase angle between SIG IN and COMP IN varies from to 36 and is 8 at f o. The voltage swing for PC 3 is greater than for PC 2 but consequently has more ripple in the signal to the CO. When no SIG IN is present the CO will be forced to f max as opposed to f min when PC 2 is used. The operating characteristics of all three phase comparators should be compared to the requirements of the system design and the appropriate one should be used. SIG IN COMP IN PC2 OUT CO IN PCP OUT SIG IN COMP IN PC3 OUT CO IN HIGH IMPEDANCE OFF STATE Figure 9. Typical Waveforms for PLL Using Phase Comparator 2 Figure. Typical Waveform for PLL Using Phase Comparator 3 CC GND CC GND 9

10 8 CC = 4. CC = CC = CC = R I = (k Ω ) 4 CC = I I ( μ A) CC = /2 CC. /2 CC I () /2 CC /2CC 5 m /2 CC /2 CC + 5 m I () Figure. Input Resistance at SIG IN, COMP IN with I =. at Self Bias Point Figure 2. Input Current at SIG IN, COMP IN with I = 5 m at Self Bias Point DEM OUT DEMOD OUT CC = R S = k CC = R S =5 k CC = R S = k CC = R S =5 k CC = R S = k CC = R S =5 k CO IN () Figure 3. Offset oltage at Demodulator Output as a Function of CO IN and R S FREQUENCY STABILITY (%) R= k R= k R= k R= k R= k CC = R= k C = pf; R2 = ; COIN =/3 CC AMBIENT TEMPERATURE ( C) Figure 3A. Frequency Stability versus Ambient Temperature: CC = FREQUENCY STABILITY (%) R= k R= k CC = C = pf; R2 = ; COIN = /2 CC AMBIENT TEMPERATURE ( C) R= k FREQUENCY STABILITY (%) R= k R= k R= k CC = 8. C = pf; R2 = ; COIN =/2 CC AMBIENT TEMPERATURE ( C) Figure 3B. Frequency Stability versus Ambient Temperature: CC = Figure 3C. Frequency Stability versus Ambient Temperature: CC =

11 23 2 CC = 7 6 CC = CC = f CO (MHz) CC = f CO (KHz) CC = CC = 2 9 R = k C = 39 pf COIN () R = k C = F COIN () Figure 4A. CO Frequency (f CO ) as a Function of the CO Input oltage ( COIN ) Figure 4B. CO Frequency (f CO ) as a Function of the CO Input oltage ( COIN ) f CO (MHz). CC = CC = CC = f CO (KHz) CC = CC = CC =.3 R = k C = 39 pf COIN ().2 R = k C = F COIN () Figure 4C. CO Frequency (f CO ) as a Function of the CO Input oltage ( COIN ) Figure 4D. CO Frequency (f CO ) as a Function of the CO Input oltage ( COIN ) CC =. C =. F f 2 Δ f CO (%) f f f. C = 39 pf R2 = ; = R (k ) MIN /2 CC MAX =.5 OER THE CC RANGE: FOR CO LINEARITY f = (f + f 2 ) / 2 LINEARITY = (f f ) / f ) x % Figure 5A. Frequency Linearity versus R, C and CC Figure 5B. Definition of CO Frequency Linearity

12 6 C L = 5 pf; R2 = ; COIN = /2 CC FOR CC = AND ; COIN = /3 CC FOR CC = ; T amb = 25 C 6 C L = 5 pf; R = ; COIN = ; T amb = 25 C PR (μ W) 5 4 CC =, C = 4 pf CC =, C =. F CC =, C = 4 pf CC =, C =. F CC =, C = 4 pf CC =, C =. F PR2 (μ W) 5 4 CC =, C =. F CC =, C = 4 pf CC =, C =. F CC =, C = 4 pf CC =, C =. F CC =, C = 4 pf R (k ) Figure. Power Dissipation versus R R2 (k ) Figure 7. Power Dissipation versus R2 P DEM ( μ W) 3 2 R = R2 = ; T amb = 25 C CC = CC = f CO (Hz) CC = INH = GND; T amb = 25 C; R2 = ; COIN = /3 CC R= k 2 3 R S (k ) CC = Figure 8. DC Power Dissipation of Demodulator versus R S R= k 3 R= k C (pf) Figure 9. CO Center Frequency versus C f off (Hz) CC = R = ; COIN = /2 CC FOR CC = AND ; COIN = /3 CC FOR CC = ; INH = GND; T amb = 25 C R2= k 2fL (Hz) CC = ; R2 = 3 2 R2= k R2= k C (pf) RC Figure 2. Frequency Offset versus C Figure 2. Typical Frequency Lock Range (2f L ) versus R C 2

13 FREQ. (MHz) C=39 pf R2 ( k ) R= k R= k R=2 k R=3 k R=4 k R=5 k R= k R= k FREQ. (MHz) C=39 pf R2 ( k ) R=3 k R= k R=2 k R=3 k R=4 k R=5 k R= k R= k Figure 22. R2 versus f max Figure 23. R2 versus f min 2 C=39 pf L(MHz) 2f R= k R= k R=2 k R=3 k R=4 k R=5 k R= k R2 ( k ) R= k Figure 24. R2 versus Frequency Lock Range (2f L ) 3

14 APPLICATION INFORMATION The following information is a guide for approximate values of R, R2, and C. Figures 2, 2, and 22 should be used as references as indicated below, also the values of R, R2, and C should not violate the Maximum values indicated in the DC ELECTRICAL CHARACTERISTICS tables. Phase Comparator Phase Comparator 2 Phase Comparator 3 R 2 = R 2 R 2 = R 2 R 2 = R 2 Given f Given f and fl Given f max and f Given f and fl Given f max and f Given f and fl Use f with Figure 9 to determine R and C. (see Figure 24 for characteristics of the CO operation) Calculate f min f min = f fl Determine values of C and R2 from Figure 2. Determine R C from Figure 22. Calculate value of R from the value of C and the product of RC from Figure 22. (see Figure 25 for characteristics of the CO operation) Determine the value of R and C using Figure 2 and use Figure 22 to obtain 2fL and then use this to calculate f min. Calculate f min f min = f fl Determine values of C and R2 from Figure 2. Determine R C from Figure 22. Calculate value of R from the value of C and the product of RC from Figure 22. (see Figure 25 for characteristics of the CO operation) Determine the value of R and C using Figure 2 and Figure 22 to obtain 2fL and then use this to calculate f min. Calculate f min: f min = f fl Determine values of C and R2 from Figure 2. Determine R C from Figure 22. Calculate value of R from the value of C and the product of RC from Figure 22. (see Figure 25 for characteristics of the CO operation) 4

15 PACKAGE DIMENSIONS PDIP N SUFFIX CASE ISSUE T A 8 9 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. H G F D PL S C K.25 (.) M T T SEATING PLANE A M J L M INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G BSC 2.54 BSC H.5 BSC.27 BSC J K L M S SOIC D SUFFIX CASE 75B 5 ISSUE J A 9 8 B P 8 PL.25 (.) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G K C D PL.25 (.) M T B S A S M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC.5 BSC J K M 7 7 P R

16 PACKAGE DIMENSIONS TSSOP DT SUFFIX CASE 948F ISSUE A 5 (.6) T 5 (.6) T (.4) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 C X K REF (.4) M T U S S 9 8 A G B U N H J N J F DETAIL E DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N.25 (.) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 5 (.6) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED.25 (.) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C.2.47 D F G.65 BSC.26 BSC H J J K K L 6.4 BSC.252 BSC M 8 8

17 PACKAGE DIMENSIONS SOEIAJ F SUFFIX CASE 966 ISSUE O e 9 Z b D A H E A 3 (.5) M (.4) 8 E IEW P M L E Q L DETAIL P c NOTES: М. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. М 2. CONTROLLING DIMENSION: MILLIMETER. М 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 5 (.6) PER SIDE. М 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. М 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE.46 (.8). MILLIMETERS INCHES DIM MIN MAX MIN MAX A 5.8 A b c D E e.27 BSC.5 BSC H E L L E M Q Z

18 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, Meguro ku, Tokyo, Japan 53 5 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. MC74HC446A/D