MC74HC4046B. Phase-Locked Loop. High Performance Silicon Gate CMOS

Transcription

1 MC74HC446B Phase-Locked Loop High Performance Silicon Gate CMOS The MC74HC446B is similar in function to the MC446 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC446B phase locked loop contai three phase comparators, a voltage controlled oscillator (CO) and unity gain op amp DEM OUT. The comparators have two common signal inputs,, and. Input and can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator (an exclusive OR gate) provides a digital error signal PC OUT and maintai 9 degrees phase shift at the center frequency between and signals (both at % duty cycle). Phase comparator 2 (with leading edge seing logic) provides digital error signals PC2 OUT and PCP OUT and maintai a degree phase shift between and signals (duty cycle is immaterial). The linear CO produces an output signal CO OUT whose frequency is determined by the voltage of input CO IN signal and the capacitor and resistors connected to pi CA, CB, R and R2. The unity gain op amp output DEM OUT with an external resistor is used where the CO IN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the CO and all op amps to minimize standby power coumption. Applicatio include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage to frequency conversion and motor speed control. Features Output Drive Capability: LSTTL Loads Low Power Coumption Characteristic of CMOS Devices Operating Speeds Similar to LSTTL Wide Operating oltage Range for CO: to Low Input Current:. A Maximum (except and ) In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Low Quiescent Current: 8 A Maximum (CO disabled) High Noise Immunity Characteristic of CMOS Devices Diode Protection on All Inputs Chip Complexity: 279 FETs or 7 Equivalent Gates NL Prefix for Automotive and Other Applicatio Requiring Unique Site and Control Change Requirements; AEC Q Qualified and PPAP Capable These Devices are Pb Free, Halogen Free and are RoHS Compliant SOIC 6 D SUFFIX CASE 7B PCP out PC out COMP in CO out PIN ASSIGNMENT INH CA CB TSSOP 6 DT SUFFIX CASE 948F MARKING DIAGRAMS HC446BG AWLYWW SOIC 6 6 HC4 46B ALYW TSSOP 6 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page of this data sheet PC3 out SIG in PC2 out R2 R DEM out CO in Semiconductor Components Industries, LLC, 28 May, 28 Rev. Publication Order Number: MC74HC446B/D

2 MC74HC446B Pin No. Symbol Name and Function PCP OUT PC OUT CO OUT INH CA CB CO IN DEM OUT R R2 PC2 OUT PC3 OUT Phase Comparator Pulse Output Phase Comparator Output Comparator Input CO Output Inhibit Input Capacitor C Connection A Capacitor C Connection B Ground ( ) SS CO Input Demodulator Output Resistor R Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply oltage MAXIMUM RATINGS Symbol Parameter alue Unit DC Supply oltage (Referenced to ). to +7. in DC Input oltage (Referenced to ). to +. out DC Output oltage (Referenced to ). to +. I in DC Input Current, per Pin ±2 ma I out DC Output Current, per Pin ±2 ma I CC DC Supply Current, and Pi ± ma P D Power Dissipation in Still Air SOIC Package mw T stg Storage Temperature 6 to + C T L Lead Temperature, mm from Case for Seconds SOIC Package 26 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating: SOIC Package: 7 mw/ C from 6 to 2 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit DC Supply oltage (Referenced to ) DC Supply oltage (Referenced to ) NON CO 2. in, out DC Input oltage, Output oltage (Referenced to ) T A Operating Temperature, All Package Types +2 C t r, t f Input Rise and Fall Time = 2. (Pin ) = = Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4 2

3 MC74HC446B [Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS (oltages Referenced to ) Symbol Parameter Test Conditio Guaranteed Limit to 2 C 8 C 2 C Unit IH Minimum High Level Input oltage DC Coupled, out = or I out 2 A IL Maximum Low Level Input oltage DC Coupled, out = or I out 2 A OH Minimum High Level Output oltage PCP OUT, PCn OUT in = IH or IL I out 2 A in = IH or IL I out 4. ma I out.2 ma OL Maximum Low Level Output oltage Qa Qh PCP OUT, PCn OUT out = or I out 2 A 2. I in I OZ I CC in = IH or IL I out 4. ma I out.2 ma Maximum Input Leakage Current, in = or 2. Maximum Three State Leakage Current PC2 OUT Maximum Quiescent Supply Current (per Package) (CO disabled) Pi 3, and 4 at Pin 9 at ; Input Leakage at Pi 3 and 4 to be excluded Output in High Impedance State in = IH or IL out = or in = or I out = A.26.3 ± ±8. ±24 ± ±4. ±9. ±24 ±8.4.4 ±. ±. ±27. ±8 A ±. ±. ± A A [Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS (C L = pf, Input t r = t f = ) Symbol Parameter Guaranteed Limit to 2 C 8 C 2 C Unit t PLH, t PHL Maximum Propagation Delay, / to PC OUT (Figure ) t PLH, t PHL Maximum Propagation Delay, / to PCP OUT (Figure ) t PLH, t PHL Maximum Propagation Delay, / to PC3 OUT (Figure ) t PLZ, t PHZ Maximum Propagation Delay, / Output Disable Time to PC2 OUT (Figures 2 and 3) t PZH, t PZL Maximum Propagation Delay, / Output Enable Time to PC2 OUT (Figures 2 and 3) t TLH, t THL Maximum Output Traition Time (Figure )

4 MC74HC446B [CO Section] DC ELECTRICAL CHARACTERISTICS (oltages Referenced to ) Symbol Parameter Test Conditio IH Minimum High Level Input oltage INH out = or I out 2 A Guaranteed Limit to 2 C 8 C 2 C Unit IL Maximum Low Level Input oltage INH out = or I out 2 A OH Minimum High Level Output oltage CO OUT in = IH or IL I out 2 A in = IH or IL I out 4. ma I out.2 ma OL Maximum Low Level Output oltage CO OUT out = or I out 2 A I in CO IN in = IH or IL I out 4. ma I out.2 ma Maximum Input Leakage in = or.. A Current INH, CO IN Operating oltage Range at CO IN over the range specified for R; For linearity see Fig. 3A, Parallel value of R and R2 should be > 2.7 k INH = IL R Resistor Range R2 C Capacitor Range Min Max Min Max Min Max No Limit k pf [CO Section] AC ELECTRICAL CHARACTERISTICS (C L = pf, Input t r = t f = ) Symbol f/t fo Parameter Frequency Stability with Temperature Changes (Figures A, B, C) CO Center Frequency (Duty Factor = %, R = 3 k, C = 39 pf, R2 = infinity) (See Figures 2A, B, C, D for other conditio) fco CO Frequency Linearity CO Duty Factor at CO OUT Guaranteed Limit to 2 C 8 C 2 C Min Max Min Max Min Max 3 3 Unit %/K MHz See Figures 3A, B % Typical % % 4

5 MC74HC446B [Demodulator Section] DC ELECTRICAL CHARACTERISTICS Symbol Parameter Test Conditio RS Resistor Range At RS > k the Leakage Current can Influence DEM OUT OFF RD Offset oltage i = CO IN = /2 ; CO IN to DEM OUT alues taken over RS Range. Dynamic Output DEM OUT = /2 Resistance at DEM OUT Guaranteed Limit to 2 C 8 C 2 C Min Max Min Max Min Max See Figure Typical 2 Unit k m SWITCHING WAEFORMS, INPUTS % INPUT % PCP OUT, PC OUT PC3 OUT OUTPUTS t THL t PHL 9% % % t PLH t TLH INPUT PC2 OUT OUTPUT t PZH % % t PHZ 9% OH HIGH IMPEDANCE Figure. Figure 2. INPUT INPUT PC2 OUT OUTPUT % t PZL % % t PLZ % HIGH IMPEDANCE OL DEICE UNDER TEST OUTPUT TEST POINT C L * *INCLUDES ALL PROBE AND JIG CAPACITANCE Figure 3. Figure 4. Test Circuit

6 MC74HC446B DETAILED CIRCUIT DESCRIPTION oltage Controlled Oscillator/Demodulator Output The CO requires two or three external components to operate. These are R, R2, C. Resistor R and Capacitor C are selected to determine the center frequency of the CO (see typical performance curves Figure 2). R2 can be used to set the offset frequency with volts at CO input. For example, if R2 is decreased, the offset frequency is increased. If R2 is omitted the CO range is from Hz. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/hz) is decreased. Thus, for a narrow lock range, large swings on the CO input will cause less frequency variation. Internally, the resistors set a current in a current mirror, as shown in Figure. The mirrored current drives one side of the capacitor. Once the voltage across the capacitor charges up to ref of the comparators, the oscillator logic flips the capacitor which causes the mirror to charge the opposite side of the capacitor. The output from the internal logic is then taken to CO output (Pin 4). The input to the CO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filter design. In order to make signals at the CO input accessible without degrading the loop performance, the CO input voltage is buffered through a unity gain Op amp to Demod Output. This Op amp can drive loads of K ohms or more and provides no loading effects to the CO input voltage (see Figure ). An inhibit input is provided to allow disabling of the CO and all Op amps (see Figure ). This is useful if the internal CO is not being used. A logic high on inhibit disables the CO and all Op amps, minimizing standby power coumption. 2 REF + _ I R 2 CURRENT MIRROR I + I 2 = I 3 CO IN 9 + _ I 2 4 CO OUT R I 3 DEMOD OUT + _ C (EXTERNAL) 6 7 ref + + INH Figure. Logic Diagram for CO 6

7 MC74HC446B The output of the CO is a standard high speed CMOS output with an equivalent LS TTL fan out of. The CO output is approximately a square wave. This output can either directly feed the of the phase comparators or feed external prescalers (counters) to enable frequency synthesis. Phase Comparators All three phase comparators have two inputs, and. The and have a special DC bias network that enables AC coupling of input signals. If the signals are not AC coupled, standard 74HC input levels are required. Both input structures are shown in Figure 6. The outputs of these comparators are essentially standard 74HC outputs (comparator 2 is TRI STATEABLE). In normal operation and ground voltage levels are fed to the loop filter. This differs from some phase detectors which supply a current to the loop filter and should be coidered in the design. (The MC446 also provides a voltage). 4 PC2 OUT 3 3 PCP OUT PC3 OUT PC OUT 2 Figure 6. Logic Diagram for Phase Comparators Phase Comparator This comparator is a simple XOR gate similar to the 74HC86. Its operation is similar to an overdriven balanced modulator. To maximize lock range the input frequencies must have a % duty cycle. Typical input and output waveforms are shown in Figure 7. The output of the phase detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will lock onto if initially out of lock is defined as the capture range. The capture range for phase detector is dependent on the loop filter design. The capture range can be as large as the lock range, which is equal to the CO frequency range. To see how the detector operates, refer to Figure 7. When two square wave signals are applied to this comparator, an output waveform (whose duty cycle is dependent on the phase difference between the two signals) results. As the phase difference increases, the output duty cycle increases and the voltage after the loop filter increases. In order to achieve lock when the PLL input frequency increases, the CO input voltage must increase and the phase difference between and will increase. At an input frequency equal to f min, the CO input is at. This requires the phase detector output to be grounded; hence, the two input signals must be in phase. When the input frequency is f max, the CO input must be and the phase detector inputs must be 8 degrees out of phase. PC OUT CO IN Figure 7. Typical Waveforms for PLL Using Phase Comparator The XOR is more susceptible to locking onto harmonics of the than the digital phase detector 2. For itance, 7

8 MC74HC446B a signal 2 times the CO frequency results in the same output duty cycle as a signal equal to the CO frequency. The difference is that the output frequency of the 2f example is twice that of the other example. The loop filter and CO range should be designed to prevent locking on to harmonics. Phase Comparator 2 This detector is a digital memory network. It coists of four flip flops and some gating logic, a three state output and a phase pulse output as shown in Figure 6. This comparator acts only on the positive edges of the input signals and is independent of duty cycle. Phase comparator 2 operates in such a way as to force the PLL into lock with phase difference between the CO output and the signal input positive waveform edges. Figure 8 shows some typical loop waveforms. First assume that is leading the. This mea that the CO s frequency must be increased to bring its leading edge into proper phase alignment. Thus the phase detector 2 output is set high. This will cause the loop filter to charge up the CO input, increasing the CO frequency. Once the leading edge of the is detected, the output goes TRI STATE holding the CO input at the loop filter voltage. If the CO still lags the then the phase detector will again charge up the CO input for the time between the leading edges of both waveforms. If the CO leads the then when the leading edge of the CO is seen; the output of the phase comparator goes low. This discharges the loop filter until the leading edge of the is detected at which time the output disables itself again. This has the effect of slowing down the CO to again make the rising edges of both waveforms coincidental. When the PLL is out of lock, the CO will be running either slower or faster than the. If it is running slower the phase detector will see more rising edges and so the output of the phase comparator will be high a majority of the time, raising the CO s frequency. Conversely, if the CO is running faster than the, the output of the detector will be low most of the time and the CO s output frequency will be decreased. As one can see, when the PLL is locked, the output of phase comparator 2 will be disabled except for minor correctio at the leading edge of the waveforms. When PC 2 is TRI STATED, the PCP output is high. This output can be used to determine when the PLL is in the locked condition. This detector has several interesting characteristics. Over the entire CO frequency range there is no phase difference between the and the. The lock range of the PLL is the same as the capture range. Minimal power was coumed in the loop filter since in lock the detector output is a high impedance. When no is present, the detector will see only CO leading edges, so the comparator output will stay low, forcing the CO to f min. Phase comparator 2 is more susceptible to noise, causing the PLL to unlock. If a noise pulse is seen on the, the comparator treats it as another positive edge of the and will cause the output to go high until the CO leading edge is seen, potentially for an entire period. This would cause the CO to speed up during that time. When using PC, the output of that phase detector would be disturbed for only the short duration of the noise spike and would cause less upset. Phase Comparator 3 This is a positive edge triggered sequential phase detector using an RS flip flop as shown in Figure 6. When the PLL is using this comparator, the loop is controlled by positive signal traitio and the duty factors of and are not important. It has some similar characteristics to the edge seitive comparator. To see how this detector works, assume input pulses are applied to the and s as shown in Figure 9. When the leads the, the flop is set. This will charge the loop filter and cause the CO to speed up, bringing the comparator into phase with the. The phase angle between and varies from to 36 and is 8 at f o. The voltage swing for PC 3 is greater than for PC 2 but coequently has more ripple in the signal to the CO. When no is present the CO will be forced to f max as opposed to f min when PC 2 is used. The operating characteristics of all three phase comparators should be compared to the requirements of the system design and the appropriate one should be used. PC2 OUT CO IN PCP OUT PC3 OUT CO IN HIGH IMPEDANCE OFF-STATE Figure 8. Typical Waveforms for PLL Using Phase Comparator 2 Figure 9. Typical Waveform for PLL Using Phase Comparator 3 CC 8

9 MC74HC446B TYPICAL CHARACTERISTICS Y AXIS LABEL (UNIT) =, R S = k =, R S = k =, R S = k =, R S = k X AXIS LABEL (UNIT) Figure. Offset oltage at Demodulator Output as a Function of CO IN and R S =, R S = k =, R S = k FREQUENCY STABILITY (%) 2 2 =, C = pf; R2 = ; COin = /3 T A, AMBIENT TEMPERATURE ( C) Figure A. Frequency Stability vs. Ambient Temperature: = R = 3 k R = k R = k FREQUENCY STABILITY (%) 2 2 =, C = pf; R2 = ; COin = /2 R = 3 k T A, AMBIENT TEMPERATURE ( C) R = k R = k Figure B. Frequency Stability vs. Ambient Temperature: = FREQUENCY STABILITY (%) 2 2 =, C = pf; R2 = ; COin = /2 T A, AMBIENT TEMPERATURE ( C) Figure C. Frequency Stability vs. Ambient Temperature: = R = 3 k R = k R = k 9

10 MC74HC446B TYPICAL CHARACTERISTICS = 6 = f CO (MHz) = = f CO (khz) = = R = k C = 39 pf R = k C = F COIN () COIN () Figure 2A. CO Frequency (f CO ) as a Function of the CO Input oltage ( COIN ) Figure 2B. CO Frequency (f CO ) as a Function of the CO Input oltage ( COIN ) f CO (MHz) =. = = R = k C = 39 pf f CO (khz) =.. = = R = k C = F COIN () COIN () Figure 2C. CO Frequency (f CO ) as a Function of the CO Input oltage ( COIN ) Figure 2D. CO Frequency (f CO ) as a Function of the CO Input oltage ( COIN ) 8 = C = F R2 = =. =. over the Range: for CO Linearity f = (f + f 2 ) / 2 Linearity = (f f ) / (f ) x % f CO (%) = C = F = C = 39 pf = C = F = C = 39 pf f 2 f f f 2 = C = 39 pf R (k ) MIN /2 cc Figure 3A. Frequency Linearity vs. Figure 3B. Definition of CO Frequency R, C and Linearity MAX

11 MC74HC446B ORDERING INFORMATION MC74HC446BDG Device Package Shipping SOIC 6 (Pb Free) 48 Units / Rail MC74HC446BDR2G NL74HC446ADR2G* MC74HC446BDTG SOIC 6 (Pb Free) SOIC 6 (Pb Free) TSSOP 6 (Pb Free) 2 Units / Reel 2 Units / Reel 96 Units / Rail MC74HC446BDTR2G TSSOP 6 (Pb Free) 2 Units / Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD8/D. *NL Prefix for Automotive and Other Applicatio Requiring Unique Site and Control Change Requirements; AEC Q Qualified and PPAP Capable.

12 MC74HC446B (.6) T (.6) T (.4) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 C 6X K REF A G PACKAGE DIMENSIONS (.4) M T U S S B U TSSOP 6 CASE 948F ISSUE B H J N N J F DETAIL E DETAIL E K K ÇÇÇ ÉÉÉ ÇÇÇ SECTION N N.2 (.) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED (.6) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED.2 (.) PER SIDE.. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C.2.47 D..2.6 F G.6 BSC.26 BSC H J J K K L 6.4 BSC.22 BSC M 8 8 SOLDERING FOOTPRINT* PITCH 6X.36 6X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 2

13 MC74HC446B PACKAGE DIMENSIONS A B SOIC 6 CASE 7B ISSUE K P 8 PL.2 (.) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION (.6) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 27 (.) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC. BSC J K M 7 7 P R T SEATING PLANE G D 6 PL.2 (.) M T B S A S K C M R X 4 J F SOLDERING FOOTPRINT* 8X 6.4 6X.2 6 6X.8.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor ow the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Buyer is respoible for its products and applicatio using ON Semiconductor products, including compliance with all laws, regulatio and safety requirements or standards, regardless of any support or applicatio information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any licee under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 92 E. 32nd Pkwy, Aurora, Colorado 8 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74HC446B/D