NTMFD4C20N. Dual N-Channel Power MOSFET. 30 V, High Side 18 A / Low Side 27 A, Dual N Channel SO8FL

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1 NTMFDCN Dual N-Channel Power MOSFET 3 V, High Side A / Low Side 7 A, Dual N Channel SOFL Features Co Packaged Power Stage Solution to Minimize Board Space Minimized Parasitic Inductances Optimized Devices to Reduce Power Losses These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant Applications DC DC Converters System Voltage Rails Point of Load V (BR)DSS R DS(ON) MAX I D MAX Top FET 3 V Bottom FET 3 V 7.3 V. V 3. V. V D (, 3,, 9) A 7 A () G S/D () () G S (,, 7) PIN CONNECTIONS D S D D 3 9 D S/D 7 S S G G (Bottom View) DFN CASE BX MARKING DIAGRAM CN AYWZZ CN A Y W ZZ = Specific Device Code = Assembly Location = Year = Work Week = Lot Traceability ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, 3 September, Rev. Publication Order Number: NTMFDCN/D

2 NTMFDCN MAXIMUM RATINGS ( unless otherwise stated) Parameter Symbol Value Unit Drain to Source Voltage V DSS 3 V Drain to Source Voltage Gate to Source Voltage V GS ± V Gate to Source Voltage Continuous Drain Current R JA (Note ) Power Dissipation R JA (Note ) Steady State T A = C I D T A = C. T A = C T A = C 3 T A = C P D. W.97 Continuous Drain Current R JA s (Note ) T A = C I D. Power Dissipation R JA s (Note ) Continuous Drain Current R JA (Note ) Power Dissipation R JA (Note ) Pulsed Drain Current TA = C tp = s T A = C 3. T A = C 7. T A = C 9. T A = C P D.37 W. T A = C I D 9. T A = C. T A = C 3.7 T A = C 9.9 T A = C P D.9 W. I DM A Operating Junction and Storage Temperature T J, T STG to + C Source Current (Body Diode) I S. A. Drain to Source DV/DT dv/dt V/ns Single Pulse Drain to Source Avalanche Energy (T J = C, V DD = V, V GS = V, L =. mh, R G = ) Lead Temperature for Soldering Purposes (/ from case for s) I L = A pk EAS mj I L = 9 A pk EAS T L C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.. Surface mounted on FR board using sq in pad, oz Cu.. Surface mounted on FR board using the minimum recommended pad size of mm. A A A

3 NTMFDCN THERMAL RESISTANCE MAXIMUM RATINGS Parameter FET Symbol Value Unit Junction to Ambient Steady State (Note 3) R JA. 3.3 Junction to Ambient Steady State (Note ) R JA.3.7 Junction to Ambient (t s) (Note 3) R JA. 7. Junction to Case (Drain) R JC. 3. Surface mounted on FR board using sq in pad, oz Cu.. Surface mounted on FR board using the minimum recommended pad size of mm. 3.7 C/W ELECTRICAL CHARACTERISTICS ( unless otherwise specified) Parameter FET Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage Drain to Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V (BR)DSS V GS = V, I D = A 3 V V GS = V, I D = ma 3 V (BR)DSS /. mv/ C T J I DSS V GS = V, V DS = V V GS = V, V DS = V A Gate to Source Leakage Current I GSS V DS = V, V GS = ± V ± na ± ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = A.3. V Negative Threshold Temperature Coefficient Drain to Source On Resistance.3. V GS(TH) /.7 mv/ C T J. R DS(on) V GS = V I D = A. 7.3 V GS =. V I D = A.7. V GS = V I D = A.7 3. V GS =. V I D = A.. Forward Transconductance g FS V DS =. V, I D = A 3 S. Pulse Test: pulse width 3 s, duty cycle %.. Switching characteristics are independent of operating junction temperatures. m 3

4 NTMFDCN ELECTRICAL CHARACTERISTICS ( unless otherwise specified) Parameter FET Symbol Test Condition Min Typ CHARGES, CAPACITANCES & GATE RESISTANCE 97 Input Capacitance C ISS 9 3 Output Capacitance C OSS V GS = V, f = MHz, V DS = V 99 Reverse Capacitance C RSS 9.3 Total Gate Charge Q G(TOT) 3. Threshold Gate Charge Q G(TH) 3.3 V GS =. V, V DS = V; I D = A 3.3 Gate to Source Charge Q GS.. Gate to Drain Charge Q GD 3. 9 Total Gate Charge Q G(TOT) V GS = V, V DS = V; I D = A 9 SWITCHING CHARACTERISTICS (Note ) 9. Turn On Delay Time t d(on) 33 Rise Time t r V GS =. V, V DS = V, 3 I D = A, R G = 3. Turn Off Delay Time t d(off). Fall Time t f. SWITCHING CHARACTERISTICS (Note ). Turn On Delay Time t d(on). Rise Time t r V GS = V, V DS = V, I D = A, R G = 3. Turn Off Delay Time t d(off) Fall Time DRAIN SOURCE DIODE CHARACTERISTICS Forward Voltage. t f. V SD V GS = V, I S = 3 A V GS = V, I S = 3 A. Pulse Test: pulse width 3 s, duty cycle %.. Switching characteristics are independent of operating junction temperatures. Max Unit pf nc nc ns ns V

5 NTMFDCN ELECTRICAL CHARACTERISTICS ( unless otherwise specified) Parameter FET Symbol Test Condition Min Typ DRAIN SOURCE DIODE CHARACTERISTICS 3 Reverse Recovery Time t RR 3. Charge Time ta V GS = V, d IS /d t = A/ s, I S =. 3 A. Discharge Time tb 9. Reverse Recovery Charge PACKAGE PARASITIC VALUES Source Inductance Drain Inductance Gate Inductance Gate Resistance Q RR..3 L S.. L D.7 T A = C L G..3.. R G.3... Pulse Test: pulse width 3 s, duty cycle %.. Switching characteristics are independent of operating junction temperatures. Max Unit ns nc nh nh nh ORDERING INFORMATION NTMFDCNTG Device Package Shipping DFN (Pb Free) / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D.

6 NTMFDCN TYPICAL CHARACTERISTICS 3 3. V. V to V 3 3. V 3. V 3. V 3. V 3. V. V. V 7 3 V DS = V.. T J = C V GS, GATE TO SOURCE VOLTAGE (V) Figure. On Region Characteristics Figure. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) V GS, GATE TO SOURCE VOLTAGE (V) I D = 3 A V GS = V Figure 3. On Resistance vs. V GS 7 T J, JUNCTION TEMPERATURE ( C) I D = 3 A Figure. On Resistance Variation with Temperature R DS(on), DRAIN TO SOURCE RESISTANCE ( ) I DSS, LEAKAGE (na) Figure. On Resistance vs. Drain Current and Gate Voltage V GS = V V GS =. V V GS = V T J = C T J = C Figure. Drain to Source Leakage Current vs. Voltage 7 3

7 NTMFDCN TYPICAL CHARACTERISTICS C, CAPACITANCE (pf) C iss C oss C rss V GS = V 3 V GS, GATE TO SOURCE VOLTAGE (V) Q gs Q gd Q T V DD = V V GS = V I D = 3 A Q g, TOTAL GATE CHARGE (nc) Figure 7. Capacitance Variation Figure. Gate to Source and Drain to Source Voltage vs. Total Charge t, TIME (ns) V DD = V I D = A V GS = V R G, GATE RESISTANCE ( ) t d(on) t r t d(off) Figure 9. Resistive Switching Time Variation vs. Gate Resistance t f I S, SOURCE CURRENT (A). V GS = V V SD, SOURCE TO DRAIN VOLTAGE (V) Figure. Diode Forward Voltage vs. Current.... V < V GS < V Single Pulse T C = C R DS(on) Limit Thermal Limit Package Limit. s s ms ms dc E AS, SINGLE PULSE DRAIN TO SOURCE AVALANCHE ENERGY (mj) 7 I D = 7 A T J, STARTING JUNCTION TEMPERATURE ( C) Figure. Maximum Rated Forward Biased Safe Operating Area Figure. Maximum Avalanche Energy vs. Starting Junction Temperature 7

8 NTMFDCN TYPICAL CHARACTERISTICS R(t) ( C/W) Duty Cycle = % % % % % %. Single Pulse PULSE TIME (sec) Figure 3. Thermal Response G FS (S) 3 T A = C T A = C 3 7.E.E 7.E.E.E.E 3 I D (A) PULSE WIDTH (SECONDS) Figure. G FS vs. I D Figure. Avalanche Characteristics

9 NTMFDCN TYPICAL CHARACTERISTICS 3 V V to. V 3 3. V 3. V 3. V 3. V 3. V. V. V 3 V DS = V T J = C V GS, GATE TO SOURCE VOLTAGE (V) Figure. On Region Characteristics Figure 7. Transfer Characteristics R DS(on), DRAIN TO SOURCE RESISTANCE ( ) R DS(on), DRAIN TO SOURCE RES- ISTANCE (NORMALIZED) V GS, GATE TO SOURCE VOLTAGE (V) Figure. On Resistance vs. V GS I D = 3 A V GS = V 7 T J, JUNCTION TEMPERATURE ( C) I D = 3 A Figure. On Resistance Variation with Temperature R DS(on), DRAIN TO SOURCE RESISTANCE ( ) I DSS, LEAKAGE (na) Figure 9. On Resistance vs. Drain Current and Gate Voltage V GS = V V GS =. V V GS = V T J = C T J = C Figure. Drain to Source Leakage Current vs. Voltage 7 3 9

10 NTMFDCN TYPICAL CHARACTERISTICS C, CAPACITANCE (pf) C iss C oss C rss V GS = V 3 V GS, GATE TO SOURCE VOLTAGE (V) Q gs Q gd Q T V DD = V V GS = V I D = 3 A 3 Q g, TOTAL GATE CHARGE (nc) Figure. Capacitance Variation Figure 3. Gate to Source and Drain to Source Voltage vs. Total Charge t, TIME (ns) V DD = V I D = A V GS = V R G, GATE RESISTANCE ( ) t d(off) t d(on) Figure. Resistive Switching Time Variation vs. Gate Resistance t r t f I S, SOURCE CURRENT (A). V GS = V V SD, SOURCE TO DRAIN VOLTAGE (V) Figure. Diode Forward Voltage vs. Current. V < V GS < V Single Pulse T C = C. R DS(on) Limit Thermal Limit Package Limit... Figure. Maximum Rated Forward Biased Safe Operating Area s s ms ms dc E AS, SINGLE PULSE DRAIN TO SOURCE AVALANCHE ENERGY (mj) I D = 9 A T J, STARTING JUNCTION TEMPERATURE ( C) Figure 7. Maximum Avalanche Energy vs. Starting Junction Temperature

11 NTMFDCN TYPICAL CHARACTERISTICS R(t) ( C/W) Duty Cycle = % % % % % %. Single Pulse PULSE TIME (sec) Figure. Thermal Response G FS (S) T A = C T A = C 3 7.E 7.E.E.E.E 3 I D (A) PULSE WIDTH (SECONDS) Figure 9. G FS vs. I D Figure 3. Avalanche Characteristics

12 NTMFDCN PACKAGE DIMENSIONS PIN ONE IDENTIFIER NOTE. C. C k k k D D NOTE 7 ÉÉ 3 TOP VIEW SIDE VIEW e D BOTTOM VIEW X e/ DFN x,.7p Dual Flag (SOFL Dual Asymmetrical) CASE BX ISSUE D NOTE E A E. C A B E E3 X L X c C SEATING PLANE DETAIL A DETAIL B. REF. C DETAIL B NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y.M, 99.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN. AND. MM FROM THE TERMINAL TIP.. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS.. DIMENSIONS b AND L ARE MEASURED AT THE PACKAGE SUR- FACE. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 7. SEATING PLANE IS DEFINED BY THE TERMINALS. A IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. X MILLIMETERS h DIM MIN MAX A.9. A.. b.. A NOTE 7 b.. c.3.33 D..3 D.. D 3.. DETAIL A E..3 E.. E.7.7 E3.. e.7 BSC h k.39.9 k..7 k L.3. X b. C A B. C NOTE 3 X b NOTE 3 PACKAGE OUTLINE. RECOMMENDED SOLDERING FOOTPRINT*.97.3 X..3. X.9 X.9..7 PITCH DIMENSION: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 9 E. 3nd Pkwy, Aurora, Colorado USA Phone: or 3 3 Toll Free USA/Canada Fax: or 3 37 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: 3 7 ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NTMFDCN/D

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