MC74HCT4066A. Quad Analog Switch/ Multiplexer/Demultiplexer with LSTTL Compatible Inputs. High Performance Silicon Gate CMOS

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MC4HCT4066A Quad Analog Switch/ Multiplexer/Demultiplexer with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC4HCT4066A utilizes silicon gate CMOS technology to achieve fast

1 MC4HCT4066A Quad Analog Switch/ Multiplexer/Demultiplexer with LSTTL Compatible Inputs High Performance Silicon Gate CMOS The MC4HCT4066A utilizes silicon gate CMOS technology to achieve fast propagation delays, low resistances, and low OFF channel leakage current. This bilateral switch/ multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power supply range (from to GND). The HCT4066A is identical in pinout to the metal gate CMOS MC06 and MC066. Each device has four independent switches. The device has been designed so the resistances (R ) are more linear over input voltage than R of metal gate CMOS analog switches. The /OFF control inputs are compatible with standard CMOS and LSTTL outputs. For analog switches with voltage level translators, see the HC436A. SOIC D SUFFIX CASE 5A TSSOP DT SUFFIX CASE 948G MARKING DIAGRAMS HCT4066AG AWLYWW HCT40 66A ALYW Features Fast Switching and Propagation Speeds High /OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power Supply Voltage Range ( GND) = 4.5 to 5.5 V Analog Input Voltage Range ( GND) = 0 to 5.5 V Improved Linearity and Lower Resistance over Input Voltage than the MC06 or MC066 Low Noise Chip Complexity: 44 FETs or Equivalent Gates These are Pb Free Devices A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATI See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 200 November, 200 Rev. Publication Order Number: MC4HCT4066A/D

2 MC4HCT4066A X A Y A 2 3 A /OFF Y B 3 2 D /OFF X B 4 X D B /OFF 5 0 Y D C /OFF 6 9 Y C GND 8 X C Figure. Pin Assignment FUNCTI TABLE On/Off Control State of Input Analog Switch L Off H On X A A /OFF X B B /OFF X C C /OFF X D D /OFF Y A Y B Y C Y D ANALOG OUTPUTS/S ANALOG S/OUTPUTS = X A, X B, X C, X D PIN = PIN = GND Figure 2. Logic Diagram ORDERING INFORMATI MC4HCT4066ADG Device Package Shipping SOIC (Pb Free) 55 Units / Rail MC4HCT4066ADR2G SOIC (Pb Free) 2500 / Tape & Reel MC4HCT4066ADTR2G TSSOP * 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *This package is inherently Pb Free. 2

3 MC4HCT4066A MAXIMUM RATINGS Symbol Parameter Value Unit Positive DC Supply Voltage (Referenced to GND) 0.5 to +.0 V V IS Analog Input Voltage (Referenced to GND) 0.5 to V V in Digital Input Voltage (Referenced to GND) 0.5 to V I DC Current Into or Out of Any Pin ±25 ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package T stg Storage Temperature 65 to +50 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating SOIC Package: mw/ C from 65 C to 25 C TSSOP Package: 6. mw/ C from 65 C to 25 C mw This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range GND (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. RECOMMENDED OPERATING CDITIS Symbol Parameter Min Max Unit Positive DC Supply Voltage (Referenced to GND) V V IS Analog Input Voltage (Referenced to GND) GND V V in Digital Input Voltage (Referenced to GND) GND V V IO * Static or Dynamic Voltage Across Switch.2 V T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time, /OFF Control Inputs (Figure 0) = 4.5 V *For voltage drops across the switch greater than.2 V (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. ns DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND) Symbol Parameter Test Conditions V IH V IL I in I CC I CC Minimum High Level Voltage /OFF Control Inputs Maximum Low Level Voltage /OFF Control Inputs Maximum Input Leakage Current /OFF Control Inputs Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current (per Input) V Guaranteed Limit 55 to 25 C 85 C 25 C R on = Per Spec 4.5 to V R on = Per Spec 4.5 to V V in = or GND 5.5 ±0. ±.0 ±.0 A V in = or GND V IO = 0 V V in = 2. V Other control inputs at or GND Unit A 4.5 to A 3

4 MC4HCT4066A DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions R on Maximum Resistance V in = V IH V IS = to GND I S 2.0 ma (Figures 3, 4) R on I off I on Maximum Difference in Resistance Between Any Two Channels in the Same Package Maximum Off Channel Leakage Current, Any One Channel Maximum On Channel Leakage Current, Any One Channel V in = V IH V IS = or GND (Endpoints) I S 2.0 ma (Figures 3, 4) V in = V IH V IS = /2 ( GND) I S 2.0 ma V in = V IL V IO = or GND Switch Off (Figure 5) V in = V IH V IS = or GND (Figure 6) V 55 to 25 C 85 C 25 C Unit A A AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, /OFF Control Inputs: t r = t f = 6 ns) Symbol t PLH, t PHL t PLZ, t PHZ Parameter Maximum Propagation Delay, Analog Input to Analog Output (Figures 0 and ) Maximum Propagation Delay, /OFF Control to Analog Output (Figures 2 and 3) V Guaranteed Limit 55 to 25 C 85 C 25 C Unit ns ns t PZL, t PZH Maximum Propagation Delay, /OFF Control to Analog Output (Figures 2 and 3) ns C Maximum Capacitance /OFF Control Input pf Control Input = GND Analog I/O Feedthrough C, = 5.0 V C PD Power Dissipation Capacitance (Per Switch) (Figure 5)* *Used to determine the no load dynamic power consumption: P D = C PD 2 f + I CC. 5 pf 4

5 MC4HCT4066A ADDITIAL APPLICATI CHARACTERISTICS (Voltages Referenced to GND Unless Noted) ÎÎÎÎÎ Limit* ÎÎÎ ÎÎ ÎÎÎÎ 25 C ÎÎÎ Symbol Parameter Test Conditions V 54/4HCT Unit ÎÎÎÎÎÎÎ BW Maximum On Channel Bandwidth or f Minimum Frequency Response Î in = MHz Sine Wave MHz Adjust f in Voltage to Obtain 0 dbm at V OS ÎÎÎÎÎÎÎÎ (Figure ) Î Increase f in Frequency Until db Meter Reads 3 db ÎÎÎÎÎÎÎÎ R L = 50, C L = 0 pf ÎÎÎÎÎÎÎ Off Channel Feedthrough Isolation f (Figure 8) Î in Sine Wave db Adjust f in Voltage to Obtain 0 dbm at V IS ÎÎÎÎÎÎÎÎ f in = 0 khz, R L = 600, C L = 50 pf ÎÎÎ 4.5 ÎÎÎÎ 50 ÎÎÎ f in =.0 MHz, R L = 50, C L = 0 pf ÎÎÎ 4.5 ÎÎÎÎ 40 ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Feedthrough Noise, Control to Î V in MHz Square Wave (t r = t f = 6 ns) ÎÎÎÎÎÎÎÎ mv PP Switch Adjust R (Figure 9) Î L at Setup so that I S = 0 A R L = 600, C L = 50 pf ÎÎÎ 4.5 ÎÎÎÎ 60 ÎÎÎ R L = 0 k, C L = 0 pf ÎÎÎ 4.5 ÎÎÎÎ 30 ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Crosstalk Between Any Two Î f in Sine Wave ÎÎÎÎÎÎÎÎ db Switches Î Adjust f in Voltage to Obtain 0 dbm at V IS ÎÎÎÎÎÎÎÎ (Figure ) f in = 0 khz, R L = 600, C L = 50 pf Î ÎÎÎÎÎÎ ÎÎÎ f in =.0 MHz, R L = 50, C L = 0 pf ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ THD Total Harmonic Distortion f (Figure 6) Î in = khz, R L = 0 k, C L = 50 pf % THD = THD Measured THD Source ÎÎÎÎÎÎÎÎ V IS = 4.0 V PP sine wave ÎÎÎ 4.5 ÎÎÎÎ 0.0 ÎÎÎ *Guaranteed limits not tested. Determined by design and verified by qualification. 5

6 MC4HCT4066A 4.5 V C C 55 C V is, VOLTAGE (VOLTS), REFERENCED TO GROUND Figure 3. Typical On Resistance, = 4.5 V PLOTTER PROGRAMMABLE POWER SUPPLY MINI COMPUTER DC ANALYZER - + DEVICE UNDER TEST ANALOG IN COMM OUT GND Figure 4. On Resistance Test Set Up GND A OFF GND A N/C V IL V IH Figure 5. Maximum Off Channel Leakage Current, Any One Channel, Test Set Up Figure 6. Maximum On Channel Leakage Current, Test Set Up 6

7 MC4HCT4066A V OS V IS V OS f in 0. F C L * db METER f in OFF 0. F R L C L * db METER Figure. Maximum On Channel Bandwidth Test Set Up Figure 8. Off Channel Feedthrough Isolation, Test Set Up /2 /2 R L R L V OS OFF/ I S 3.0 V GND V in MHz t r = t f = 6 ns C L * ANALOG IN (V I ) t PLH ANALOG OUT 50% 50% t PHL GND Figure 9. Feedthrough Noise, /OFF Control to Analog Out, Test Set Up Figure 0. Propagation Delays, Analog In to Analog Out

8 MC4HCT4066A ANALOG IN Figure. Propagation Delay Test Set Up ANALOG OUT C L * TEST POINT (V I ) ANALOG OUT 90% V m 0% t r t f VCC 50% 50% V I = GND to 3.0 V V m =.3 V t PZL t PZH t PLZ t PHZ 0% 90% Figure 2. Propagation Delay, /OFF Control to Analog Out GND HIGH IMPEDANCE V OL V OH HIGH IMPEDANCE 2 2 POSITI WHEN TESTING t PHZ AND t PZH POSITI WHEN 2 TESTING t PLZ AND t PZL /OFF k C L * TEST POINT f in 0. F R L V IS OFF OR GND R L C L * V OS R L C L * R L /2 /2 Figure 3. Propagation Delay Test Set Up /2 Figure. Crosstalk Between Any Two Switches, Test Set Up A V IS V OS N/C OFF/ N/C f in 0. F R L C L * TO DISTORTI METER /OFF /2 Figure 5. Power Dissipation Capacitance Test Set Up Figure 6. Total Harmonic Distortion, Test Set Up 8

9 MC4HCT4066A dbm FUNDAMENTAL FREQUENCY DEVICE SOURCE FREQUENCY (khz) Figure. Plot, Harmonic Distortion 3.0 APPLICATI INFORMATI Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages and GND. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between and GND is twelve volts. Therefore, using the configuration in Figure 6, a maximum analog signal of twelve volts peak to peak can be controlled. When voltage transients above and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure. These diodes should be small signal, fast turn on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOSORB (MOSORB is an acronym for high current surge protectors). MOSORBs are fast turn on devices ideally suited for precise DC protection with no inherent wear out mechanism. = 5 V + 5 V 0 V ANALOG I/O ANALOG O/I + 5 V 0 V D x D x 6 D x D x OTHER S OTHER S Figure 8. 5 V Application Figure 9. Transient Suppressor Application 9

10 MC4HCT4066A + 5 V + 5 V ANALOG SIGNALS ANALOG SIGNALS ANALOG SIGNALS ANALOG SIGNALS LSTTL/ NMOS R* R* R* R* 5 HC4066A LSTTL/ NMOS 5 HCT4066A 6 S 6 S 5 5 R* = 2 TO 0 k a. Using Pull-Up Resistors with HC Device b. Using HCT Buffer Figure 20. LSTTL/NMOS to HCTMOS Interface CHANNEL 4 OF 4 SWITCHES CHANNEL 3 CHANNEL 2 OF 4 SWITCHES OF 4 SWITCHES COMM I/O CHANNEL OF 4 SWITCHES OF 4 SWITCHES - + LF356 OR EQUIVALENT OUTPUT 0.0 F S Figure 2. 4 Input Multiplexer Figure 22. Sample/Hold Amplifier 0

11 MC4HCT4066A PACKAGE DIMENSIS T SEATING PLANE G A 8 B P PL SOIC CASE 5A 03 ISSUE J 0.25 (0.00) M B M NOTES:. DIMENSIING AND TOLERANCING PER ANSI Y.5M, LING DIMENSI: MILLIMETER. 3. DIMENSIS A AND B DO NOT INCLUDE MOLD PROTRUSI. 4. MAXIMUM MOLD PROTRUSI 0.5 (0.006) PER SIDE. 5. DIMENSI D DOES NOT INCLUDE DAMBAR PROTRUSI. ALLOWABLE DAMBAR PROTRUSI SHALL BE 0.2 (0.005) TOTAL IN EXCESS OF THE D DIMENSI AT MAXIMUM MATERIAL CDITI. MILLIMETERS INCHES C R X 45 F DIM MIN MAX MIN MAX A B C D D PL K M J F G.2 BSC BSC 0.25 (0.00) M T B S A S J K M 0 0 P SOLDERING FOOTPRINT* R X 0.58 X.04 X.52.2 PITCH DIMENSIS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

12 MC4HCT4066A PACKAGE DIMENSIS TSSOP CASE 948G 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C X K REF 0.0 (0.004) M T U S V S N (0.00) M B U A V G H N J J F DETAIL E K K ÇÇÇ ÉÉÉ SECTI N N DETAIL E W NOTES:. DIMENSIING AND TOLERANCING PER ANSI Y.5M, LING DIMENSI: MILLIMETER. 3. DIMENSI A DOES NOT INCLUDE MOLD FLASH, PROTRUSIS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSI B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSI. INTERLEAD FLASH OR PROTRUSI SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSI K DOES NOT INCLUDE DAMBAR PROTRUSI. ALLOWABLE DAMBAR PROTRUSI SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSI AT MAXIMUM MATERIAL CDITI. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE LY.. DIMENSI A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH X 0.36 X.26 DIMENSIS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 2

13 MC4HCT4066A Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATI ORDERING INFORMATI LITERATURE FULFILLMENT: Literature Distribution Center for Semiconductor P.O. Box 563, Denver, Colorado 802 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC4HCT4066A/D

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