MC74LVXT4066. Quad Analog Switch/ Multiplexer/Demultiplexer. High Performance Silicon Gate CMOS
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1 MC4LVXT466 Quad Analog Switch/ Multiplexer/Demultiplexer High Performance Silicon Gate CMOS The MC4LVXT466 utilizes silicon gate CMOS technology to achieve fast propagation delays, low resistances, and low OFF channel leakage current. This bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full power supply range (from to ). The LVXT466 is identical in pinout to the metal gate CMOS MC66 and the high speed CMOS HC466A. Each device has four independent switches. The device has been designed so that the resistances (R ) are much more linear over input voltage than R of metal gate CMOS analog switches. The /OFF control inputs are compatible with standard LSTTL outputs. The input protection circuitry on this device allows overvoltage tolerance on the /OFF control inputs, allowing the device to be used as a logic level translator from 3. V CMOS logic to. V CMOS Logic or from.8 V CMOS logic to 3. V CMOS Logic while operating at the higher voltage power supply. The MC4LVXT466 input structure provides protection when voltages up to. V are applied, regardless of the supply voltage. This allows the MC4LVXT466 to be used to interface. V circuits to 3. V circuits. Features Fast Switching and Propagation Speeds High /OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power Supply Voltage Range ( ) = 2. to 6. V Analog Input Voltage Range ( ) = 2. to 6. V Improved Linearity and Lower Resistance over Input Voltage than the MC6 or MC66 Low Noise These Devices are Pb Free and are RoHS Compliant SOIC D SUFFIX CASE A TSSOP DT SUFFIX CASE 948G SOEIAJ M SUFFIX CASE 96 MARKING DIAGRAMS ORDERING INFORMATI See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. LVXT466G AWLYWW LVXT 466 ALYW LVXT466 ALYWG LVXT466 = Specific Device Code A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) Semiconductor Components Industries, LLC, 2 May, 2 Rev. 3 Publication Order Number: MC4LVXT466/D
2 MC4LVXT466 LOGIC DIAGRAM PIN CNECTI (Top View) X A A /OFF X B B /OFF X C C /OFF X D Y A Y B Y C Y D ANALOG OUTPUTS/S X A Y A Y B X B B /OFF C /OFF A /OFF D /OFF X D Y D Y C X C D /OFF 2 ANALOG S/OUTPUTS = X A, X B, X C, X D PIN = PIN = On/Off Control Input FUNCTI TABLE State of Analog Switch L H Off On ORDERING INFORMATI MC4LVXT466DR2G Device Package Shipping SOIC (Pb Free) 2 Tape & Reel MC4LVXT466DTR2G TSSOP * 2 Tape & Reel MC4LVXT466MG SOEIAJ (Pb Free) Units / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *This package is inherently Pb Free. 2
3 MC4LVXT466 MAXIMUM RATINGS SymbolÎÎ Parameter Î Value Unit ÎÎ Positive DC Supply Voltage (Referenced to ) Î. to +. V V IS ÎÎ Analog Input Voltage (Referenced to ) Î. to +. V V in ÎÎ Digital Input Voltage (Referenced to ) Î. to +. V I ÎÎ DC Current Into or Out of Any Pin Î 2 ma P D ÎÎ Power Dissipation in Still Air, SOIC Package Î mw TSSOP Package 4 T stg ÎÎ Storage Temperature 6 to + C T L Lead Temperature, mm from Case for Seconds 26 C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating SOIC Package: mw/ C from 6 to 2 C TSSOP Package: 6. mw/ C from 6 to 2 C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. RECOMMENDED OPERATING CDITIS SymbolÎÎ Parameter Min Max Unit ÎÎ Positive DC Supply Voltage (Referenced to ) 2.. V V IS ÎÎ Analog Input Voltage (Referenced to ) VCC V V in ÎÎ Digital Input Voltage (Referenced to ) VCC V V IO * ÎÎ Static or Dynamic Voltage Across Switch.2 V T A ÎÎ Operating Temperature, All Package Types + 8 C t r, t f ÎÎ Input Rise and Fall Time, /OFF Control Î Inputs (Figure ) = 3.3 V ±.3 V ns/v =. V ±. V 2 *For voltage drops across the switch greater than.2 V (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to ) ÎÎ ÎÎ Guaranteed Limit Symbol Parameter Test Conditions V to 2 C 8 C 2 C Unit Î V IH Minimum High Level Voltage R Î /OFF Control Inputs on = Per Spec V 4. Î (Note ). Î V IL Maximum Low Level Voltage R on = Per Spec V /OFF Control Inputs (Note ). Î I in Î Maximum Input Leakage Current V in = or. Î ±. ±. ± A /OFF Control Inputs ÎÎ I CC Maximum Quiescent Supply V Î Current (per Package) in = or V IO = V. 4. ÎÎ 4 6 ÎÎ A. Specifications are for design target only. Not final specification limits. 3
4 MC4LVXT466 DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to ) Guaranteed Limit to Symbol Parameter Test Conditions V 2 C 8 C 2 C Unit R on Î Î Maximum Resistance V in = 2. V IS = to I S 2. ma (Figures, 2) V in = 2. V IS = or (Endpoints) I S 2. ma (Figures, 2) R on Î Maximum Difference in Î V in = 3. ÎÎ Resistance Between Any Two Î V IS = /2 ( ) Channels in the Same Package I S 2. ma. 2 I off Î Î Maximum Off Channel Leakage V in = V IL ÎÎ.. Current, Any One Channel Î V IO = or ÎÎ.. A Switch Off (Figure 3) Î I on Maximum On Channel Leakage V Î Î in = Current, Any One Channel V IS =. or (Figure 4)... A At supply voltage ( ) approaching 2 V the analog switch on resistance becomes extremely non linear. Therefore, for low voltage operation, it is recommended that these devices only be used to control digital signals. AC ELECTRICAL CHARACTERISTICS (C L = pf, /OFF Control Inputs: t r = t f = 6 ns) ÎÎ ÎÎ Guaranteed Limit Symbol Parameter V to 2 C 8 C 2 C Unit Î t PLH, Maximum Propagation Delay, Analog Input to Analog Output ns t PHL Î (Figures 8 and 9) 3. Î ÎÎ 4. Î Î t PLZ, Maximum Propagation Delay, /OFF Control to Analog Output ns t PHZ Î (Figures and ) 3. Î Î. 8 2 t PZL ÎÎ, Maximum Propagation Delay, /OFF Control to Analog Output ns t PZH Î (Figures and ) 3. Î ÎÎ. Î 8. 2 C Î Maximum Capacitance /OFF Control Input Î pf Control Input = ÎÎ Analog I/O ÎÎ C PD Power Dissipation Capacitance (Per Switch) (Figure 3)* Feedthrough * Used to determine the no load dynamic power consumption: P D = C PD 2 f + I CC... 2 C, =. V. pf 4
5 MC4LVXT466 ADDITIAL APPLICATI CHARACTERISTICS (Voltages Referenced to Unless Noted) Limit* Symbol Parameter Test Conditions V 2 C Î Unit BW Maximum On Channel Bandwidth or f ÎÎ in = MHz Sine Wave 4. Minimum Frequency Response Adjust f in Voltage to Obtain dbm at V OS ÎÎ (Figure ) Î Increase f in Frequency Until db Meter Reads 3 db. MHz 6 R ÎÎ L =, C L = pf Off Channel Feedthrough Isolation f ÎÎ in Sine Wave 4. (Figure 6) Adjust f in Voltage to Obtain dbm at V IS ÎÎ f in = khz, R L = 6, C L = pf. db ÎÎ f in =. MHz, R L =, C L = pf Î Feedthrough Noise, Control to Switch V ÎÎ in MHz Square Wave (t r = t f = 3 ns) 4. (Figure ) Adjust R L at Setup so that I S mv PP = A. 2 ÎÎ R L = 6, C L = pf ÎÎ R L = k, C L = pf 4.. Î Crosstalk Between Any Two Switches f ÎÎ in Sine Wave 4. (Figure 2) Adjust f in Voltage to Obtain dbm at V IS ÎÎ f in = khz, R L = 6, C L = pf. db ÎÎ f in =. MHz, R L =, C L = pf Î THD Total Harmonic Distortion f ÎÎ in = khz, R L = k, C L = pf % (Figure ) THD = THD Measured THD Source ÎÎ V IS = 4. V PP sine wave 4.. V ÎÎ IS =. V PP sine wave..6 *Guaranteed limits not tested. Determined by design and verified by qualification.
6 MC4LVXT Ron (Ohms) 2 I s = 9mA I s = ma I s = ma Ron (Ohms) C 2 C 8 C 2 C. I s = ma Vin (Volts) Vin (Volts) Figure a. Typical On Resistance, = 2. V, T = 2 C Figure b. Typical On Resistance, = 2. V Ron (Ohms) 2 2 C 8 C 2 C - C Ron (Ohms) 2 C 8 C 2 C - C Vin (Volts) Vin (Volts) Figure c. Typical On Resistance, = 3. V Figure d. Typical On Resistance, = 4. V 8 6 PLOTTER Ron (Ohms) C 8 C 2 C - C PROGRAMMABLE POWER SUPPLY - + MINI COMPUTER DEVICE UNDER TEST DC ANALYZER Vin (Volts) Figure e. Typical On Resistance, =. V ANALOG IN COMM OUT Figure 2. On Resistance Test Set Up 6
7 MC4LVXT466 A OFF A N/C V IL Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set Up Figure 4. Maximum On Channel Leakage Current, Test Set Up V OS V IS V OS f in. F C L * db METER f in OFF. F R L C L * db METER Figure. Maximum On Channel Bandwidth Test Set Up Figure 6. Off Channel Feedthrough Isolation, Test Set Up /2 /2 R L R L V OS OFF/ I S V IL V in MHz t r = t f = 3 ns C L * ANALOG IN t PLH ANALOG OUT % % t PHL Figure. Feedthrough Noise, /OFF Control to Analog Out, Test Set Up Figure 8. Propagation Delays, Analog In to Analog Out
8 MC4LVXT466 ANALOG IN Figure 9. Propagation Delay Test Set Up ANALOG OUT C L * TEST POINT ANALOG OUT 9% % % t r t f VCC % % t PZL t PZH t PLZ t PHZ % 9% Figure. Propagation Delay, /OFF Control to Analog Out HIGH IMPEDANCE V OL V OH HIGH IMPEDANCE V IL 2 2 POSITI WHEN TESTING t PHZ AND t PZH POSITI WHEN 2 TESTING t PLZ AND t PZL /OFF k C L * TEST POINT f in. F R L V IS OFF OR V IL R L CL * R L /2 /2 V OS R L C L * Figure. Propagation Delay Test Set Up /2 Figure 2. Crosstalk Between Any Two Switches, Test Set Up A V IS V OS N/C OFF/ N/C f in. F R L C L * TO DISTORTI METER V IL /OFF Figure 3. Power Dissipation Capacitance Test Set Up /2 Figure. Total Harmonic Distortion, Test Set Up 8
9 MC4LVXT466 dbm FUNDAMENTAL FREQUENCY DEVICE SOURCE. 2. FREQUENCY (khz) Figure. Plot, Harmonic Distortion 3. APPLICATI INFORMATI The /OFF Control pins should be at or V IL logic levels, being recognized as logic high and V IL being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to or through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages and. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below. In the example below, the difference between and is six volts. Therefore, using the configuration in Figure 6, a maximum analog signal of six volts peak to peak can be controlled. When voltage transients above and/or below are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure. These diodes should be small signal, fast turn on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (Mosorb is an acronym for high current surge protectors). Mosorbs are fast turn on devices ideally suited for precise DC protection with no inherent wear out mechanism. = 6. V + 6. V V ANALOG I/O ANALOG O/I + 6. V V D x D x 6 D x D x OTHER S ( OR V IL ) OTHER S ( OR V IL ) Figure V Application Figure. Transient Suppressor Application 9
10 MC4LVXT V + V +3V ANALOG SIGNALS ANALOG SIGNALS +3V ANALOG SIGNALS ANALOG SIGNALS.8-2.V CIRCUITRY 6 LVXT466 S LSTTL/ NMOS/ ABT/ ALS 6 LVXT466 S R* = 2 TO k a. Low Voltage Logic Level Shifting Control b. Using LVXT466 Figure 8. Low Voltage CMOS Interface CHANNEL 4 OF 4 SWITCHES CHANNEL 3 CHANNEL 2 OF 4 SWITCHES OF 4 SWITCHES COMM I/O CHANNEL OF 4 SWITCHES OF 4 SWITCHES - + LF36 OR EQUIVALENT OUTPUT. F S Figure 9. 4 Input Multiplexer Figure 2. Sample/Hold Amplifier
11 T SEATING PLANE G A 8 D PL B K P PL C.2 (.) M T B S A S MC4LVXT466 PACKAGE DIMENSIS.2 (.) M B M SOIC D SUFFIX CASE A 3 ISSUE J NOTES:. DIMENSIING AND TOLERANCING PER ANSI Y.M, LING DIMENSI: MILLIMETER. 3. DIMENSIS A AND B DO NOT INCLUDE MOLD PROTRUSI. 4. MAXIMUM MOLD PROTRUSI. (.6) PER SIDE.. DIMENSI D DOES NOT INCLUDE DAMBAR PROTRUSI. ALLOWABLE DAMBAR PROTRUSI SHALL BE.2 (.) TOTAL IN EXCESS OF THE D DIMENSI AT MAXIMUM MATERIAL CDITI. MILLIMETERS INCHES R X 4 F DIM MIN MAX MIN MAX A B C D M J F G.2 BSC. BSC J K M P R SOLDERING FOOTPRINT X.8 X.4 X.2.2 PITCH DIMENSIS: MILLIMETERS
12 MC4LVXT466 PACKAGE DIMENSIS. (.6) T. (.6) T L. (.4) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C G X K REF A V. (.4) M T U S V S 8 B U H TSSOP DT SUFFIX CASE 948G ISSUE B N N J J F DETAIL E DETAIL E.2 (.) K K M ÇÇÇ ÉÉÉ ÇÇÇ SECTI N N W NOTES:. DIMENSIING AND TOLERANCING PER ANSI Y.M, LING DIMENSI: MILLIMETER. 3. DIMENSI A DOES NOT INCLUDE MOLD FLASH, PROTRUSIS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED. (.6) PER SIDE. 4. DIMENSI B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSI. INTERLEAD FLASH OR PROTRUSI SHALL NOT EXCEED.2 (.) PER SIDE.. DIMENSI K DOES NOT INCLUDE DAMBAR PROTRUSI. ALLOWABLE DAMBAR PROTRUSI SHALL BE.8 (.3) TOTAL IN EXCESS OF THE K DIMENSI AT MAXIMUM MATERIAL CDITI. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE LY.. DIMENSI A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C.2.4 D F G.6 BSC.26 BSC H J J K K L 6.4 BSC.22 BSC M 8 8 SOLDERING FOOTPRINT.6.6 PITCH X.36 X.26 DIMENSIS: MILLIMETERS 2
13 MC4LVXT466 PACKAGE DIMENSIS SOEIAJ M SUFFIX CASE 96 ISSUE B L E 8 Q E H E M L Z DETAIL P D VIEW P e A c b A.3 (.) M. (.4) NOTES:. DIMENSIING AND TOLERANCING PER ANSI Y.M, LING DIMENSI: MILLIMETER. 3. DIMENSIS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIS SHALL NOT EXCEED. (.6) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE LY.. THE LEAD WIDTH DIMENSI (b) DOES NOT INCLUDE DAMBAR PROTRUSI. ALLOWABLE DAMBAR PROTRUSI SHALL BE.8 (.3) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSI AT MAXIMUM MATERIAL CDITI. DAMBAR CANNOT BE LOCATED THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIS AND ADJACENT LEAD TO BE.46 (.8). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A b c D E e.2 BSC. BSC H E L L E M Q Z Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATI ORDERING INFORMATI LITERATURE FULFILLMENT: Literature Distribution Center for Semiconductor P.O. Box 63, Denver, Colorado 82 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC4LVXT466/D
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Is Now Part of To learn more about ON Semiconductor, please visit our website at www.onsemi.com ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC
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