MARKING DIAGRAMS MAXIMUM RATINGS (Note 1.) ORDERING INFORMATION PDIP 16 P SUFFIX CASE 648 MC140xxBCP AWLYYWW
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1 The MC14051B, MC14052B, and MC14053B analog multiplexers are digitally controlled analog switches. The MC14051B effectively implements an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a Triple SPDT. All three devices feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved. Triple Diode Protection on Control Inputs Switch Function is Break Before Make Supply Voltage Range = 3.0 Vdc to 18 Vdc Analog Voltage Range (V DD V EE ) = 3.0 to 18 V Note: V EE must be V SS Linearized Transfer Characteristics Low noise 12 nv/ Cycle, f 1.0 khz Typical Pin for Pin Replacement for CD4051, CD4052, and CD4053 For 4PDT Switch, See MC14551B For Lower R ON, Use the HC4051, HC4052, or HC4053 High Speed CMOS Devices MAXIMUM RATINGS (Note 1.) Symbol Parameter Value Unit V DD DC Supply Voltage (Referenced to V EE, V SS V EE ) 0.5 to V V in, V out I in Input or Output Voltage Range (DC or Transient) (Referen ced to V SS for Control Inputs and V EE for Switch I/O) Input Current (DC or Transient) per Control Pin 0.5 to V DD V ± ma I SW Switch Through Current ±25 ma P D Power Dissipation, per Package (Note 2.) 500 mw T A Ambient Temperature Range 55 to +125 C T stg Storage Temperature Range 65 to +0 C T L Lead Temperature (8 Second Soldering) 260 C 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/c From 65C To 125C xx A WL, L YY, Y WW, W PDIP 16 P SUFFIX CASE 648 SOIC 16 D SUFFIX CASE 751B TSSOP 16 DT SUFFIX CASE 948F SOEIAJ 16 F SUFFIX CASE 966 MARKING DIAGRAMS MC140xxBCP AWLYYWW 140xxB AWLYWW 16 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION 14 0xxB ALYW MC140xxB ALYW See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. 1 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS, V EE or V DD ). Unused outputs must be left open. Semiconductor Components Industries, LLC, 2000 August, 2000 Rev. 4 1 Publication Order Number: MC14051B/D
2 MC14051B 8 Channel Analog Multiplexer/Demultiplexer MC14052B Dual 4 Channel Analog Multiplexer/Demultiplexer MC14053B Triple 2 Channel Analog Multiplexer/Demultiplexer Note: Control Inputs referenced to V SS, Analog Inputs and Outputs reference to V EE. V EE must be V SS. PIN ASSIGMENT MC14051B MC14052B MC14053B 2
3 ELECTRICAL CHARACTERISTICS Î 55C Î 25C 125C Characteristic Î Symbol V DD Î Test Conditions Min Max MinÎ Typ (3.) Max Min Max Unit SUPPLY REQUIREMENTS (Voltages Referenced to V EE ) Power Supply Voltage Î V DD Î V DD 3.0 V SS V EE Î V Range Quiescent Current Per I Package Î DD 5.0 Control Inputs: µa Î V in = V SS or V DD, Î Î Switch I/O: V EE V I/O 20 Î V DD, and V switch 500 mv Î (4.) Total Supply Current Î I D(AV) 5.0Î T A = 25C only (The Î µa (0.07 µa/khz) f + I (Dynamic Plus Î channel component, DD Typical (0.20 µa/khz) f + I Quiescent, Per Package (V in V out )/R on, is DD not included.) (0.36 µa/khz) f + I DD CONTROL INPUTS INHIBIT, A, B, C (Voltages Referenced to V SS ) Low Level Input Voltage Î V IL 5.0 R on = per spec, I Î off = per spec Î Î V Î High Level Input Voltage V IH 5.0 R on Î = per spec, V Î I off = per spec Î Input Leakage Current I in V Î in = 0 or V DD ± 0.1 Î ± ± Î µa Input Capacitance C in pf SWITCHES IN/OUT AND Î COMMONS OUT/IN X, Y, Z (Voltages Referenced to V EE ) Recommended V I/O Channel On or Off 0 V DD 0 V Î DD 0 V DD V PP Peak to Peak Voltage Into or Out of the Switch Recommended Static or Î V Dynamic Voltage Across the Switch (4.) (Figure 5) Î Î switch Channel On 0 Î 600 0Î mv Î Output Offset Voltage Î V OO Î V in = 0 V, No Load Î µv ON Resistance Î R on 5.0Î V switch 500 mv Î (4.) 800 Î Ω V in = V IL or V IH 400 Î (Control), and V in = to V DD (Switch) Î ON Resistance BetweenÎ R on Any Two Channels in the 5.0 Î Î Î Î Ω Same Package Off Channel Leakage Current (Figure ) Î Î I off V in = V IL or V IH (Control) Channel to ± 0 ± 0.05 ± 0 ±00 na Channel or Any OneÎ Channel Î Capacitance, Switch I/O C I/O Inhibit = V DD Î pf Î Capacitance, Common O/I Î Î Î C O/I Inhibit = V DD pf (MC14051B) Î Î (MC14052B) Î Î (MC14053B) 17 Capacitance, Feedthrough C I/O Î (Channel Off) Î Î Pins Not Adjacent 0. pf Pins Adjacent Î Data labeled Typ is not to be used for design purposes, but is intended as an indication of the IC s potential performance. Î 4. For voltage drops across the switch ( V switch ) > 600 mv ( > 300 mv at high temperature), excessive V DD current may be drawn, i.e. the current out of the switch may contain both V DD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) 3
4 ELECTRICAL CHARACTERISTICS (5.) (C L = 50 pf, T A = 25C) (V EE V SS unless otherwise indicated) V DD V EE Typ (6.) Characteristic Symbol Vdc All Types Max Unit Î Propagation Delay Times (Figure 6) t PLH, t PHL Î ns Switch Input to Switch Output (R L = kω) Î MC14051 t PLH, t PHL = (0.17 ns/pf) C L Î ns t PLH, t PHL = (0.08 ns/pf) C L + 11 ns 40 t PLH, t PHL = (0.06 ns/pf) C L ns MC14052 ns t PLH, t PHL = (0.17 ns/pf) C L ns t PLH, t PHL = (0.08 ns/pf) C L ns t PLH, t PHL = (0.06 ns/pf) C L Î ns 25 MC14053 ns t PLH, t PHL = (0.17 ns/pf) C L ns t PLH, t PHL = (0.08 ns/pf) C L ns t PLH, t PHL = (0.06 ns/pf) C L ns 6.0 Inhibit to Output (R L = kω, V EE = V SS ) t PHZ, t PLZ, Î ns Output 1 or 0 to High Impedance, or t Î PZH, t PZL Î High Impedance to 1 or 0 Level MC14051B MC14052B Î ns Î MC14053B Î Î ns Control Input to Output (R L = kω, V EE = V SS ) t MC14051B PLH, t PHL ns MC14052B ns MC14053B ns Second Harmonic Distortion (R L = KΩ, f = 1 khz) V in = 5 V 0.07 % PP Bandwidth (Figure 7) (R L = 1 kω, V in = 1/2 (V DD V EE ) p p, C L = 50pF Î BW 17 Î MHz 20 Log (V out /V in ) = 3 db) Î Off Channel Feedthrough Attenuation (Figure 7) R L = 1KΩ, V in = 1/2 (V DD V EE ) p p Î 50 db Î f in = 4.5 MHz MC14051B f in Î = 30 MHz MC14052B f in = 55 MHz MC14053B Î Channel Separation (Figure 8) (R L = 1 kω, V in = 1/2 (V DD V EE ) p p, f in = 3.0 MHz 50 db Î Crosstalk, Control Input to Common O/I (Figure 9) 75 (R 1 = 1 kω, R L = kω Î mv Control t TLH = t THL = 20 ns, Inhibit = V SS ) 5. The formulas given are for the typical characteristics only at 25C. 6. Data labelled Typ is not lo be used for design purposes but In intended as an indication of the IC s potential performance. 4
5 Figure 1. Switch Circuit Schematic Control Inputs Select TRUTH TABLE ON Switches Inhibit C* B A MC14051B MC14052B MC14053B X0 Y0 X0 Z0 Y0 X X1 Y1 X1 Z0 Y0 X X2 Y2 X2 Z0 Y1 X X3 Y3 X3 Z0 Y1 X X4 Z1 Y0 X X5 Z1 Y0 X X6 Z1 Y1 X X7 Z1 Y1 X1 1 x x x None None None *Not applicable for MC14052 x = Don t Care Figure 2. MC14051B Functional Diagram Figure 3. MC14052B Functional Diagram Figure 4. MC14053B Functional Diagram 5
6 TEST CIRCUITS Figure 5. V Across Switch Figure 6. Propagation Delay Times, Control and Inhibit to Output A, B, and C inputs used to turn ON or OFF the switch under test. Figure 7. Bandwidth and Off Channel Feedthrough Attenuation Figure 8. Channel Separation (Adjacent Channels Used For Setup) Figure 9. Crosstalk, Control Input to Common O/I Figure. Off Channel Leakage NOTE: See also Figures 7 and 8 in the MC14016B data sheet. 6
7 Ω Figure 11. Channel Resistance (R ON ) Test Circuit TYPICAL RESISTANCE CHARACTERISTICS Figure 12. V DD = 7.5 V, V EE = 7.5 V Figure 13. V DD = 5.0 V, V EE = 5.0 V Figure 14. V DD = 2.5 V, V EE = 2.5 V Figure. Comparison at 25 C, V DD = V EE 7
8 APPLICATIONS INFORMATION Figure A illustrates use of the on chip level converter detailed in Figures 2, 3, and 4. The 0 to 5 V Digital Control signal is used to directly control a 9 V p p analog signal. The digital control logic levels are determined by V DD and V SS. The V DD voltage is the logic high voltage; the V SS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; V SS = GND = 0 V = logic low. The maximum analog signal level is determined by V DD and V EE. The V DD voltage determines the maximum recommended peak above V SS. The V EE voltage determines the maximum swing below V SS. For the example, V DD V SS = 5 V maximum swing above V SS ; V SS V EE = 5 V maximum swing below V SS. The example shows a ± 4.5 V signal which allows a 1/2 volt margin at each peak. If voltage transients above V DD and/or below V EE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and V EE is 18.0 V. Most parameters are specified up to V which is the recommended maximum difference between V DD and V EE. Balanced supplies are not required. However, V SS must be greater than or equal to V EE. For example, V DD = + V, V SS = + 5 V, and V EE 3 V is acceptable. See the Table below. + Figure A. Application Example Figure B. External Germanium or Schottky Clipping Diodes Î POSSIBLE SUPPLY CONNECTIONS Î Î Control Inputs Î V DD V SS Î V EE Î Logic High/Logic Low Maximum Analog Signal Range In Volts In Volts In Volts In Volts In Volts Î Î + 8 Î 0 Î 8 Î + 8/0 + 8 to 8 = 16 V p p Î + 5 Î 0 Î 12 Î + 5/0 + 5 to 12 = 17 V p p Î + 5 Î 0 Î 0 Î + 5/0 + 5 to 0 = 5 V p p Î + 5 Î 0 Î 5 Î + 5/0 + 5 to 5 = V p p Î + Î + 5 Î 5 Î + / to 5 = V p p 8
9 PACKAGE DIMENSIONS H A G B F C S K D 16 PL PDIP 16 P SUFFIX PLASTIC DIP PACKAGE CASE ISSUE R T J L M T G A D 16 PL K B C SOIC 16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B 05 ISSUE J P 8 PL M R X 45 J F 9
10 PACKAGE DIMENSIONS T L PIN 1 IDENT. D 2X L/2 C 16X K REF A V G TSSOP 16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F 01 ISSUE O B U H N N J J1 F DETAIL E DETAIL E K K1 ÇÇÇ ÉÉÉ SECTION N N M W
11 PACKAGE DIMENSIONS e Z D b E A H E A 1 SOEIAJ 16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE ISSUE O VIEW P M L E Q 1 L DETAIL P c 11
12 ORDERING & SHIPPING INFORMATION: Device Package Shipping MC14051BCP PDIP Units per Box MC14051BD SOIC Units per Rail MC14051BDR2 SOIC Units / Tape & Reel MC14051BDT TSSOP Units per Rail MC14051BDTEL TSSOP Units / Tape & Reel MC14051BDTR2 TSSOP Units / Tape & Reel MC14051BF SOEIAJ 16 See Note 7. MC14051BFEL SOEIAJ 16 See Note 7. MC14052BCP PDIP Units per Box MC14052BD SOIC Units per Rail MC14052BDR2 SOIC Units / Tape & Reel MC14052BDT TSSOP Units per Rail MC14052BDTR2 TSSOP Units / Tape & Reel MC14052BF SOEIAJ 16 See Note 7. MC14052BFEL SOEIAJ 16 See Note 7. ORDERING & SHIPPING INFORMATION: MC14053BCP PDIP Units per Box MC14053BD SOIC Units per Rail MC14053BDR2 SOIC Units / Tape & Reel MC14053BDT TSSOP Units per Rail MC14053BDTEL TSSOP Units / Tape & Reel MC14053BDTR2 TSSOP Units / Tape & Reel MC14053BF SOEIAJ 16 See Note 7. MC14053BFEL SOEIAJ 16 See Note For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com Fax Response Line: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada EUROPE: LDC for ON Semiconductor European Support German Phone: (+1) (Mon Fri 2:30pm to 7:00pm CET) ONlit german@hibbertco.com French Phone: (+1) (Mon Fri 2:00pm to 7:00pm CET) ONlit french@hibbertco.com English Phone: (+1) (Mon Fri 12:00pm to 5:00pm GMT) ONlit@hibbertco.com EUROPEAN TOLL FREE ACCESS*: *Available from Germany, France, Italy, UK CENTRAL/SOUTH AMERICA: Spanish Phone: (Mon Fri 8:00am to 5:00pm MST) ONlit spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor Asia Support Phone: (Tue Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: ONlit asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r14525@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 12 MC14051B/D
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