MC74LVX4066. Quad Analog Switch/ Multiplexer/Demultiplexer. High Performance Silicon Gate CMOS

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MC4LVX4 Quad Analog Switch/ Multiplexer/Demultiplexer High Performance Silicon Gate CMOS The MC4LVX4 utilizes silicon gate CMOS technology to achieve fast propagation delays, low resistances, and low

1 MC4LVX4 Quad Analog Switch/ Multiplexer/Demultiplexer High Performance Silicon Gate CMOS The MC4LVX4 utilizes silicon gate CMOS technology to achieve fast propagation delays, low resistances, and low OFF channel leakage current. This bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full power supply range (from to GND). The LVX4 is identical in pinout to the metal gate CMOS MC and the high speed CMOS HC4A. Each device has four independent switches. The device has been designed so that the resistances (R ) are much more linear over input voltage than R of metal gate CMOS analog switches. The /OFF control inputs are compatible with standard CMOS outputs; with pull up resistors, they are compatible with LSTTL outputs. Features Fast Switching and Propagation Speeds High /OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power Supply Voltage Range ( GND) =. to. Volts Analog Input Voltage Range ( GND) =. to. Volts Improved Linearity and Lower Resistance over Input Voltage than the MC or MC Low Noise Chip Complexity: 44 FETs or Equivalent Gates These Devices are Pb Free and are RoHS Compliant SOIC D SUFFIX CASE A TSSOP DT SUFFIX CASE 948G SOEIAJ M SUFFIX CASE 9 MARKING DIAGRAMS LVX4G AWLYWW LVX 4 ALYW LVX4 ALYWG LVX4 = Specific Device Code A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATI See detailed ordering and shipping information in the package dimensions section on page of this data sheet. Semiconductor Components Industries, LLC, May, Rev. Publication Order Number: MC4LVX4/D

2 MC4LVX4 LOGIC DIAGRAM X A A /OFF X B B /OFF X C C /OFF Y A Y B Y C OUTPUTS/S PIN CNECTI (Top View) X A Y A 3 A /OFF Y B 3 D /OFF X B 4 X D B /OFF Y D C /OFF 9 Y C GND 8 X C X D Y D D /OFF S/OUTPUTS = X A, X B, X C, X D PIN = PIN = GND On/Off Control Input FUNCTI TABLE State of Analog Switch L H Off On ORDERING INFORMATI MC4LVX4DRG Device Package Shipping SOIC (Pb Free) Tape & Reel MC4LVX4DTRG MC4LVX4MG TSSOP * (Pb Free) SOEIAJ (Pb Free) Tape & Reel Units / Rail MC4LVX4MELG SOEIAJ (Pb Free) Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. *This package is inherently Pb Free.

3 MC4LVX4 Î MAXIMUM RATINGS Symbol Parameter Î Value Î Unit Positive DC Supply Voltage (Referenced to GND) Î. to +. Î V V IS Analog Input Voltage (Referenced to GND) Î. to +. Î V V in Digital Input Voltage (Referenced to GND) Î. to +. Î V I in DC Current Into or Out of /OFF Control Pins Î ± Î ma I s DC Current Into or Out of Switch Pins Î ± Î ma P D Power Dissipation in Still Air, SOIC Package Î Î mw TSSOP Package 4 Î T stg Storage Temperature to + C Î T L Lead Temperature, mm from Case for Seconds C Î Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress Î ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Î Î Derating SOIC Package: mw/ C from to C TSSOP Package:. mw/ C from to C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range GND (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. RECOMMENDED OPERATING CDITIS Symbol Parameter Î Min MaxÎ Unit Positive DC Supply Voltage (Referenced to GND) Î. Î. Î V V IS Analog Input Voltage (Referenced to GND) Î GND Î Î V V in Digital Input Voltage (Referenced to GND) Î GND Î Î V V IO* Static or Dynamic Voltage Across Switch Î. Î V T A Operating Temperature, All Package Types + 8 Î C t r, t f Input Rise and Fall Time, /OFF Control ns/v Inputs (Figure ) Î Î = 3.3 V ±.3 V Î =. V ±. V Î Î Î *For voltage drops across the switch greater than. V (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND) Î SymbolÎ Parameter Test Conditions Î V Guaranteed Limit CC VÎ to C 8 CÎ C Unit V IH Î Minimum High Level Voltage R on = Per Spec Î.Î.. Î. V /OFF Control Inputs (Note ) Î Î.Î Î 3.8 V IL Î Maximum Low Level Voltage R on = Per Spec Î.Î.. Î. V /OFF Control Inputs (Note ) Î 4.Î.3.3 Î.3 Î.Î.. Î. I in Maximum Input Leakage Current V in = or GND Î.V ±. ±. ±. Î A /OFF Control Inputs I CC Î Maximum Quiescent Supply V in = or GND V IO = V Current (per Package).Î Î 4. 4 Î A. Specifications are for design target only. Not final specification limits. 3

4 MC4LVX4 DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND) SymbolÎ Parameter Test Conditions Î V Guaranteed Limit CC VÎ to C 8 C Î C Unit R on Î Maximum Resistance V in = V IH. V IS = Î to GND Î I S ma (Figures, ) Î 4.Î 3 Î 3. 3 Î V Î in = V IH. V IS = or GND Î 3.Î 3 3 Î 4 Î (Endpoints) Î 4.Î 3 Î 3 I S ma (Figures, ). 3 Î R on Maximum Difference in V Î Resistance Between Any Two in = V IH 3. V IS = / ( GND) Î 4.Î Î Channels in the Same Package I Î S. ma. Î I off Maximum Off Channel Leakage V in = V IL Current, Any One Channel V IO = Î. or GND Î Switch Off (Figure 3) Î Î... A Î I on Î Maximum On Channel Leakage V in = V IH Î.Î.. Î. A Current, Any One Channel V IS = or GND (Figure 4) At supply voltage ( ) approaching V the analog switch on resistance becomes extremely non linear. Therefore, for low voltage operation, it is recommended that these devices only be used to control digital signals (See Figure a). AC ELECTRICAL CHARACTERISTICS (C L = pf, /OFF Control Inputs: t r = t f = ns) Î Î V Guaranteed Limit CC Î Symbol Parameter V to C 8 C C Unit t PLH, Maximum Propagation Delay, Analog Input to Analog Output Î.Î 4.. Î 8. ns t PHL (Figures 8 and 9) Î 3.Î. Î Î.Î.. Î. t PLZ, Maximum Propagation Delay, /OFF Control to Analog Output Î.Î 3 3 Î 4 ns t PHZ (Figures and ) Î 3.Î Î Î.Î 8 Î t PZL, Maximum Propagation Delay, /OFF Control to Analog Output Î.Î Î 3 ns t PZH (Figures and ) Î.Î 8. Î C Maximum Capacitance /OFF Control InputÎ Î Î pf Î Control Input = GND Î Analog I/O Î Feedthrough Î 3 Î Î. C PD Power Dissipation Capacitance (Per Switch) (Figure 3)* * Used to determine the no load dynamic power consumption: P D = C PD f + I CC. C, =. V pf 4

5 MC4LVX4 ADDITIAL APPLICATI CHARACTERISTICS (Voltages Referenced to GND Unless Noted) Limit* Symbol Parameter Test Conditions V C Unit BW Maximum On Channel Bandwidth or f Minimum Frequency Response (Figure ) in = MHz Sine Wave 4. Adjust f in Voltage to Obtain dbm at V OS Î Increase f in Frequency Until db Meter Reads 3 db Î MHz. R L =, C L = pfî Off Channel Feedthrough Isolation f (Figure ) in Sine Wave 4. Adjust f in Voltage to Obtain dbm at V IS f in = khz, R L =, C L = pfî db. f in =. MHz, R L =, C L = pfî Feedthrough Noise, Control to Switch V (Figure ) in MHz Square Wave (t r = t f = ns) 4. Adjust R L at Setup so that I S Î mv PP = A. R L =, C L = pfî R L = k, C L = pfî 4.. Crosstalk Between Any Two Switches f (Figure ) in Sine Wave 4. Adjust f in Voltage to Obtain dbm at V IS f in = khz, R L =, C L = pfî db. f in =. MHz, R L =, C L = pfî THD Total Harmonic Distortion (Figure ) f in = khz, R L = k, C L = pf % THD = THD Measured THD Source Î V IS = 4. V PP sine waveî 4.. V IS =. V PP sine wave.. Î *Guaranteed limits not tested. Determined by design and verified by qualification.

6 MC4LVX4 4 Ron (Ohms) I s = 9mA I s = ma I s = ma Ron (Ohms) C C 8 C C. I s = ma..... Vin (Volts) Vin (Volts) Figure a. Typical On Resistance, =. V, T = C Figure b. Typical On Resistance, =. V 3 Ron (Ohms) 3 3 C 8 C C - C 4 Ron (Ohms) C 8 C C - C 3 4 Vin (Volts) Vin (Volts) Figure c. Typical On Resistance, = 3. V Figure d. Typical On Resistance, = 4. V 8 PLOTTER Ron (Ohms) 8 4 C 8 C C - C PROGRAMMABLE POWER SUPPLY - + MINI COMPUTER DEVICE UNDER TEST DC ANALYZER 3 4 Vin (Volts) IN GND COMM OUT Figure e. Typical On Resistance, =. V Figure. On Resistance Test Set Up

7 MC4LVX4 GND A OFF GND A N/C V IL V IH Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set Up Figure 4. Maximum On Channel Leakage Current, Test Set Up V OS V IS V OS f in. F C L * db METER f in OFF. F R L C L * db METER Figure. Maximum On Channel Bandwidth Test Set Up Figure. Off Channel Feedthrough Isolation, Test Set Up / / R L R L V OS OFF/ I S GND V in MHz t r = t f = 3 ns C L * IN t PLH OUT % % t PHL GND Figure. Feedthrough Noise, /OFF Control to Analog Out, Test Set Up Figure 8. Propagation Delays, Analog In to Analog Out

8 MC4LVX4 IN Figure 9. Propagation Delay Test Set Up OUT C L * TEST POINT OUT 9% % % t r t f VCC % % t PZL t PZH t PLZ t PHZ % 9% Figure. Propagation Delay, /OFF Control to Analog Out GND HIGH IMPEDANCE V OL V OH HIGH IMPEDANCE POSITI WHEN TESTING t PHZ AND t PZH POSITI WHEN TESTING t PLZ AND t PZL /OFF k C L * TEST POINT f in. F R L V IS OFF OR GND R L C L * V OS R L C L * R L / / Figure. Propagation Delay Test Set Up / Figure. Crosstalk Between Any Two Switches, Test Set Up A V IS V OS N/C OFF/ N/C f in. F R L C L * TO DISTORTI METER /OFF / Figure 3. Power Dissipation Capacitance Test Set Up Figure. Total Harmonic Distortion, Test Set Up 8

9 MC4LVX4 dbm FUNDAMENTAL FREQUENCY DEVICE SOURCE.. FREQUENCY (khz) Figure. Plot, Harmonic Distortion 3. APPLICATI INFORMATI The /OFF Control pins should be at or GND logic levels, being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages and GND. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between and GND is six volts. Therefore, using the configuration in Figure, a maximum analog signal of six volts peak to peak can be controlled. When voltage transients above and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure. These diodes should be small signal, fast turn on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (Mosorb is an acronym for high current surge protectors). Mosorbs are fast turn on devices ideally suited for precise DC protection with no inherent wear out mechanism. =. V +. V V I/O O/I +. V V D x D x D x D x OTHER S ( OR GND) OTHER S ( OR GND) Figure.. V Application Figure. Transient Suppressor Application 9

10 MC4LVX4 + V + V SIGNALS SIGNALS SIGNALS SIGNALS LSTTL/ NMOS R* R* R* R* LVX4 S LSTTL/ NMOS/ ABT/ ALS LVXT4 S R* = TO k a. Using Pull-Up Resistors b. Using LVXT4 Figure 8. LSTTL/NMOS to CMOS Interface V DD = V =. TO. V SIGNALS MC4 8 4 LVX4 S SIGNALS Figure 9. TTL/NMOS to CMOS Level Converter Analog Signal Peak to Peak Greater than V CHANNEL 4 OF 4 SWITCHES CHANNEL 3 CHANNEL OF 4 SWITCHES OF 4 SWITCHES COMM I/O CHANNEL OF 4 SWITCHES OF 4 SWITCHES - + LF3 OR EQUIVALENT OUTPUT. F 3 4 S Figure. 4 Input Multiplexer Figure. Sample/Hold Amplifier

11 T SEATING PLANE G A 8 D PL B K P PL C. (.) M T B S A S MC4LVX4 PACKAGE DIMENSIS. (.) M B M SOIC D SUFFIX CASE A 3 ISSUE J NOTES:. DIMENSIING AND TOLERANCING PER ANSI Y.M, 98.. LING DIMENSI: MILLIMETER. 3. DIMENSIS A AND B DO NOT INCLUDE MOLD PROTRUSI. 4. MAXIMUM MOLD PROTRUSI. (.) PER SIDE.. DIMENSI D DOES NOT INCLUDE DAMBAR PROTRUSI. ALLOWABLE DAMBAR PROTRUSI SHALL BE. (.) TOTAL IN EXCESS OF THE D DIMENSI AT MAXIMUM MATERIAL CDITI. MILLIMETERS INCHES R X 4 F DIM MIN MAX MIN MAX A B C D M J F G. BSC. BSC J K M P R....9 SOLDERING FOOTPRINT X.8 X.4 X.. PITCH DIMENSIS: MILLIMETERS

12 MC4LVX4 PACKAGE DIMENSIS. (.) T. (.) T L. (.4) T SEATING PLANE U U S X L/ PIN IDENT. S D C G X K REF A V. (.4) M T U S V S 8 B U H TSSOP DT SUFFIX CASE 948G ISSUE B N N J J F DETAIL E DETAIL E. (.) K K M ÇÇÇ ÉÉÉ ÇÇÇ SECTI N N W NOTES:. DIMENSIING AND TOLERANCING PER ANSI Y.M, 98.. LING DIMENSI: MILLIMETER. 3. DIMENSI A DOES NOT INCLUDE MOLD FLASH, PROTRUSIS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED. (.) PER SIDE. 4. DIMENSI B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSI. INTERLEAD FLASH OR PROTRUSI SHALL NOT EXCEED. (.) PER SIDE.. DIMENSI K DOES NOT INCLUDE DAMBAR PROTRUSI. ALLOWABLE DAMBAR PROTRUSI SHALL BE.8 (.3) TOTAL IN EXCESS OF THE K DIMENSI AT MAXIMUM MATERIAL CDITI.. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE LY.. DIMENSI A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C..4 D.... F....3 G. BSC. BSC H....4 J J K K.9... L.4 BSC. BSC M 8 8 SOLDERING FOOTPRINT.. PITCH X.3 X. DIMENSIS: MILLIMETERS

13 MC4LVX4 PACKAGE DIMENSIS SOEIAJ M SUFFIX CASE 9 ISSUE B L E 8 Q E H E M L Z DETAIL P D VIEW P e A c b A.3 (.) M. (.4) NOTES:. DIMENSIING AND TOLERANCING PER ANSI Y.M, 98.. LING DIMENSI: MILLIMETER. 3. DIMENSIS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIS SHALL NOT EXCEED. (.) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE LY.. THE LEAD WIDTH DIMENSI (b) DOES NOT INCLUDE DAMBAR PROTRUSI. ALLOWABLE DAMBAR PROTRUSI SHALL BE.8 (.3) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSI AT MAXIMUM MATERIAL CDITI. DAMBAR CANNOT BE LOCATED THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIS AND ADJACENT LEAD TO BE.4 (.8). MILLIMETERS INCHES DIM MIN MAX MIN MAX A A....8 b.3... c D E..4.. e. BSC. BSC H E L L E M Q Z Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATI ORDERING INFORMATI LITERATURE FULFILLMENT: Literature Distribution Center for Semiconductor P.O. Box 3, Denver, Colorado 8 USA Phone: 33 or Toll Free USA/Canada Fax: 33 or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC4LVX4/D

MC74LVXT4066. Quad Analog Switch/ Multiplexer/Demultiplexer. High Performance Silicon Gate CMOS

MC74LVXT4066. Quad Analog Switch/ Multiplexer/Demultiplexer. High Performance Silicon Gate CMOS MC4LVXT466 Quad Analog Switch/ Multiplexer/Demultiplexer High Performance Silicon Gate CMOS The MC4LVXT466 utilizes silicon gate CMOS technology to achieve fast propagation delays, low resistances, and