MARKING DIAGRAMS ORDERING INFORMATION Figure 1. Representative Schematic Diagram (Each Amplifier) DUAL MC33078P

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1 The MC33078/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts for quality audio and data signal processing applications. This family incorporates the use of high frequency PNP input transistors to produce amplifiers exhibiting low input voltage noise with high gain bandwidth product and slew rate. The all NPN output stage exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source and sink AC frequency performance. The MC33078/9 family offers both dual and quad amplifier versions, tested over the automotive temperature range and available in the plastic DIP and SOIC packages (P and D suffixes). Dual Supply Operation: ±5.0 V to ±8 V Low Voltage Noise: 4.5 nv/ Hz Low Input Offset Voltage: 0.5 mv Low T.C. of Input Offset Voltage: 2.0 µv/ C Low Total Harmonic Distortion: 0.002% High Gain Bandwidth Product: 6 MHz High Slew Rate: 7.0 V/µs High Open Loop AC Gain: 20 khz Excellent Frequency Stability Large Output Voltage Swing: +4. V/ 4.6 V ESD Diodes Provided on the Inputs Figure. Representative Schematic Diagram (Each Amplifier) DUAL QUAD A WL, L YY, Y WW, W PDIP8 P SUFFIX CASE 626 SO8 D SUFFIX CASE 75 PDIP4 P SUFFIX CASE 646 SO4 D SUFFIX CASE 75A MARKING DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package Shipping MC33078D SO8 98 Units/Rail MC33078DR2 SO Tape & Reel MC33078P MC33079D PDIP8 SO4 50 Units/Rail 55 Units/Rail MC33079DR2 SO Tape & Reel 4 MC33079P PDIP4 25 Units/Rail MC33078P AWL YYWW ALYW MC33079P AWLYYWW MC33079D AWLYWW Semiconductor Components Industries, LLC, 2002 January, 2002 Rev. 2 Publication Order Number: MC33078/D

2 DUAL CASE 626/75 PIN CONNECTIONS QUAD CASE 646/75A MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage (V CC to V EE) V S +36 V Input Differential Voltage Range V IDR Note V Input Voltage Range V IR Note V Output Short Circuit Duration (Note 2) t SC Indefinite sec Maximum Junction Temperature T J +50 C Storage Temperature T stg 60 to +50 C Maximum Power Dissipation P D Note 2 mw. Either or both input voltages must not exceed the magnitude of V CC or V EE. 2. Power dissipation must be considered to ensure maximum junction temperature (T J ) is not exceeded (see Figure 2). 2

3 DC ELECTRICAL CHARACTERISTICS (V CC = +5 V, V EE = 5 V, T A = 25 C, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Input Offset Voltage (R S = 0 Ω, V CM = 0 V, V O = 0 V) (MC33078) T A = +25 C T A = 40 to +85 C (MC33079) T A = +25 C T A = 40 to +85 C Average Temperature Coefficient of Input Offset Voltage V IO / T 2.0 µv/ C R S = 0 Ω, V CM = 0 V, V O = 0 V, T A = T low to T high Input Bias Current (V CM = 0 V, V O = 0 V) T A = +25 C T A = 40 to +85 C Input Offset Current (V CM = 0 V, V O = 0 V) T A = +25 C T A = 40 to +85 C V IO I IB I IO Common Mode Input Voltage Range ( V IO = 5.0 mv, V O = 0 V) V ICR ±3 ±4 V Large Signal Voltage Gain (V O = ±0 V, R L = 2.0 kω) T A = +25 C T A = 40 to +85 C Output Voltage Swing (V ID = ±.0V) R L = 600 Ω R L = 600 Ω R L = 2.0 kω R L = 2.0 kω R L = 0 kω R L = 0 kω A VOL V O + V O V O + V O V O + V O Common Mode Rejection (V in = ±3V) CMR db Power Supply Rejection (Note 3) V CC /V EE = +5 V/ 5 V to +5.0 V/ 5.0 V mv na na db PSR db V Output Short Circuit Current (V ID =.0 V, Output to Ground) Source Sink I SC ma Power Supply Current (V O = 0 V, All Amplifiers) (MC33078) T A = +25 C (MC33078) T A = 40 to +85 C (MC33079) T A = +25 C (MC33079) T A = 40 to +85 C I D ma 3. Measured with V CC and V EE differentially varied simultaneously. 3

4 AC ELECTRICAL CHARACTERISTICS (V CC = +5 V, V EE = 5 V, T A = 25 C, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Slew Rate (V in = 0 V to +0 V, R L = 2.0 kω, C L = 00 pf A V = +.0) SR V/µs Gain Bandwidth Product (f = 00 khz) GBW 0 6 MHz Unity Gain Bandwidth (Open Loop) BW 9.0 MHz Gain Margin (R L = 2.0 kω) C L = 0 pf C L = 00 pf Phase Margin (R L = 2.0 kω) C L = 0 pf C L = 00 pf A m φ m Channel Separation (f = 20 Hz to 20 khz) CS 20 db Power Bandwidth (V O = 27 V pp, R L = 2.0 kω, THD.0%) BW p 20 khz Total Harmonic Distortion (R L = 2.0 kω, f = 20 Hz to 20 khz, V O = 3.0 V rms, A V = +.0) THD % Open Loop Output Impedance (V O = 0 V, f = 9.0 MHz) Z O 37 Ω Differential Input Resistance (V CM = 0 V) R in 75 kω Differential Input Capacitance (V CM = 0 V) C in 2 pf Equivalent Input Noise Voltage (R S = 00 Ω, f =.0 khz) e n 4.5 nv/ Hz Equivalent Input Noise Current (f =.0 khz) i n 0.5 pa/ Hz db Deg Figure 2. Maximum Power Dissipation versus Temperature Figure 3. Input Bias Current versus Supply Voltage Figure 4. Input Bias Current versus Temperature Ω Figure 5. Input Offset Voltage versus Temperature 4

5 Figure 6. Input Bias Current versus Common Mode Voltage Figure 7. Input Common Mode Voltage Range versus Temperature Ω Ω Figure 8. Output Saturation Voltage versus Load Resistance to Ground Figure 9. Output Short Circuit Current versus Temperature ± ± ± ± ± ± ± Figure 0. Supply Current versus Temperature Figure. Common Mode Rejection versus Frequency 5

6 Figure 2. Power Supply Rejection versus Frequency Ω Figure 3. Gain Bandwidth Product versus Supply Voltage Ω Figure 4. Gain Bandwidth Product versus Temperature Ω Ω Ω Ω Figure 5. Maximum Output Voltage versus Supply Voltage Ω Ω Figure 6. Output Voltage versus Frequency Figure 7. Open Loop Voltage Gain versus Supply Voltage 6

7 Ω Figure 8. Open Loop Voltage Gain versus Temperature Ω Figure 9. Output Impedance versus Frequency Ω Ω Ω Ω Ω Figure 20. Channel Separation versus Frequency Figure 2. Total Harmonic Distortion versus Frequency Figure 22. Total Harmonic Distortion versus Output Voltage Ω Ω µ Ω Figure 23. Slew Rate versus Supply Voltage 7

8 MC33078, MC33079 µ Ω Figure 24. Slew Rate versus Temperature Ω Figure 25. Voltage Gain and Phase versus Frequency φ Ω Figure 26. Open Loop Gain Margin and Phase Margin versus Load Capacitance φ Figure 27. Overshoot versus Output Load Capacitance nv/ Hz Figure 28. Input Referred Noise Voltage and Current versus Frequency pa/ Hz nv/ Hz Ω Figure 29. Total Input Referred Noise Voltage versus Source Resistance 8

9 Ω Figure 30. Phase Margin and Gain Margin versus Differential Source Resistance φ Ω Ω µ µ Figure 3. Inverting Amplifier Slew Rate Figure 32. Noninverting Amplifier Slew Rate Ω µ Figure 33. Noninverting Amplifier Overshoot Figure 34. Low Frequency Noise Voltage versus Time 9

10 µ Ω Ω Ω µ Ω Ω µ µ Ω Ω µ Ω Note: All capacitors are nonpolarized. Figure 35. Voltage Noise Test Circuit (0. Hz to 0 Hz pp ) 0

11 PACKAGE DIMENSIONS PDIP8 P SUFFIX CASE ISSUE L B NOTE 2 T H F A G C N D K L J M SO8 D SUFFIX CASE 7507 ISSUE W X B Y Z H G A D S C N X 45 M K J

12 PACKAGE DIMENSIONS PDIP4 P SUFFIX CASE ISSUE M B T N A F L C K J H G D 4 PL M SO4 D SUFFIX CASE 75A03 ISSUE F A B P 7 PL T G D 4 PL K C R X 45 F M J 2

13 Notes 3

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15 Notes 5

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