Amplifiers JFET INPUT OPERATIONAL AMPLIFIERS

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Lionel Ryan
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1 Order this document by TLC/D These lowcost JFET input operational amplifiers combine two stateof theart linear technologies on a single monolithic integrated circuit. Each internally compensated operational amplifier has well matched high voltage JFET input devices for low input offset voltage. The BIFET technology provides wide bandwidths and fast slew rates with low input bias currents, input offset currents, and supply currents. These devices are available in single, dual and quad operational amplifiers which are pincompatible with the industry standard MC74, MC45, and the MC343/LM324 bipolar products. Input Offset Voltage Options of 6. mv and 5 mv Max Low Input Bias Current: 3 pa Low Input Offset Current: 5. pa Wide Gain Bandwidth: 4. MHz High Slew Rate: 3 V/µs Low Supply Current:.4 ma per Amplifier High Input Impedance: 2 Ω Op Amp Function Single Dual Device TLCD TLACP TL2CD TL2ACP ORDERING INFORMATION Operating Temperature Range TA = to 7 C TA = to 7 C Package SO Plastic DIP SO Plastic DIP Quad TL4CN, ACN TA = to 7 C Plastic DIP JFET INPUT OPERATIONAL AMPLIFIERS P SUFFIX CASE 626 Offset Null Inv Input Noninvt Input VEE Output A Inputs A SEMICONDUCTOR TECHNICAL DATA PIN CONNECTIONS VEE TL (Top View) TL2 (Top View) D SUFFIX CASE 75 (SO) NC 2 7 VCC 3 6 Output 4 5 Offset Null VCC Output B Inputs B Representative Circuit Schematic (Each Amplifier) Inputs J Q3 J2 Q4 Q5 Q2 Q7 Output Q6 Q 2. k V CC 4 PIN CONNECTIONS N SUFFIX CASE 646 Offset Null (TL only).5 k Q4 Q2 Q Q.5 k Q3 Q5 Q Q6 pf Q9 Q2 Q22 Q2 Q23 24 Q24 Q9 Q J3 Q7 Q25 Bias Circuitry Common to All Amplifiers V EE Output Inputs VCC Inputs 2 Output TL4 (Top View) Output 4 VEE Inputs 4 Inputs 3 Output 3 Motorola, Inc. 997 Rev

2 TLC,AC TL2C,AC TL4C,AC MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage VCC V VEE Differential Input Voltage VID ±3 V Input Voltage Range (Note ) VIDR ±5 V Output Short Circuit Duration (Note 2) tsc Continuous Power Dissipation Plastic Package (N, P) PD 6 mw Derate above TA = 47 C /θja mw/ C Operating Ambient Temperature Range TA to 7 C Storage Temperature Range Tstg 65 to 5 C NOTES:. The magnitude of the input voltage must not exceed the magnitude of the supply voltage or 5 V, whichever is less. 2. The output may be shorted to ground or either supply. Temperature and/or supply voltages must be limited to ensure that power dissipation ratings are not exceeded. 3. ESD data available upon request. ELECTRICAL CHARACTERISTICS (VCC = 5 V, VEE = 5 V, TA = Tlow to Thigh [Note ].) Characteristics Symbol Min Typ Max Unit Input Offset Voltage (RS k, VCM = ) VIO mv TLC, TL2C 2 TL4C 2 TL_AC 7.5 Input Offset Current (VCM = ) (Note 2) IIO na TL_C 5. TL_AC 3. Input Bias Current (VCM = ) (Note 2) IIB na TL_C TL_AC 7. LargeSignal Voltage Gain (VO= ± V,RL 2. k) AVOL V/mV TL_C 5 TL_AC 25 Output Voltage Swing (PeaktoPeak) VO V (RL k) 24 (RL 2. k) 2 NOTES:. T low = C for TLAC,C T high =7 C for TLAC C for TL2AC,C 7 C for TL2AC,C C for TL4AC,C 7 C for TL4AC,C 2. Input Bias currents of JFET input op amps approximately double for every C rise in Junction Temperature as shown in Figure 3. To maintain junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing. Figure. Unity Gain Voltage Follower Figure 2. Inverting Gain of Amplifier k Vin VO Vin. k VO RL = 2. k CL = pf RL CL = pf 2

3 TLC,AC TL2C,AC TL4C,AC ELECTRICAL CHARACTERISTICS (VCC = 5 V, VEE = 5 V,, unless otherwise noted.) Characteristics Symbol Min Typ Max Unit Input Offset Voltage (RS k, VCM = ) VIO mv TLC, TL2C 5. 5 TL4C 5. 5 TL_AC Average Temperature Coefficient of Input Offset Voltage VIO/ T µv/ C RS = 5 Ω, TA = Tlow to Thigh (Note ) Input Offset Current (VCM = ) (Note 2) IIO pa TL_C 5. 2 TL_AC 5. Input Bias Current (VCM = ) (Note 2) IIB pa TL_C 3 4 TL_AC 3 2 Input Resistance ri 2 Ω Common Mode Input Voltage Range VICR V TL_C ± 5, 2 TL_AC ± 5, 2 Large Signal Voltage Gain (VO = ± V, RL 2. k) AVOL V/mV TL_C 25 5 TL_AC 5 5 Output Voltage Swing (PeaktoPeak) VO 24 2 V (RL = k) Common Mode Rejection Ratio (RS k) CMRR db TL_C 7 TL_AC Supply Voltage Rejection Ratio (RS k) PSRR db TL_C 7 TL_AC Supply Current (Each Amplifier) ID.4 2. ma Unity Gain Bandwidth BW 4. MHz Slew Rate (See Figure ) SR 3 V/µs Vin = V, RL = 2. k, CL = pf Rise Time (See Figure ) tr. µs Overshoot (Vin = 2 mv, RL = 2. k, CL = pf) OS % Equivalent Input Noise Voltage en 25 nv/ Hz RS = Ω, f = Hz Channel Separation CS 2 db AV = NOTES:. T low = C for TLAC,C T high =7 C for TLAC C for TL2AC,C 7 C for TL2AC,C C for TL4AC,C 7 C for TL4AC,C 2. Input Bias currents of JFET input op amps approximately double for every C rise in Junction Temperature as shown in Figure 3. To maintain junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing. 3

4 TLC,AC TL2C,AC TL4C,AC I IB, INPUT BIAS CURRENT (na).. Figure 3. Input Bias Current VO, OUTPUT VOLTAGE SWING (Vpp) Figure 4. Output Voltage Swing versus Frequency ± V ±5. V RL = 2. k (See Figure 2) k k k. M M f, FREQUENCY (Hz) VO, OUTPUT VOLTAGE SWING (Vpp) Figure 5. Output Voltage Swing versus Load Resistance (See Figure 2) VO, OUTPUT VOLTAGE SWING (Vpp) RL = 2. k Figure 6. Output Voltage Swing versus Supply Voltage RL, LOAD RESISTANCE (kω) VCC, VEE, SUPPLY VOLTAGE (±V) VO, OUTPUT VOLTAGE SWING (Vpp) Figure 7. Output Voltage Swing (See Figure 2) RL = k RL = 2. k , SUPPLY DRAIN CURRENT (ma) I D Figure. Supply Current per Amplifier

5 TLC,AC TL2C,AC TL4C,AC VOL, OPENLOOP GAIN (V/m/v) A Figure 9. Large Signal Voltage Gain and Phase Shift versus Frequency Gain Phase Shift... k k k. M M f, FREQUENCY (Hz) RL = 2. k PHASE SHIFT (DEGREES) AVOL, OPENLOOP GAIN (V/m/v) Figure. Large Signal Voltage Gain VO = ± V RL = 2. k. M NORMALIZED SLEW RATE Figure. Normalized Slew Rate e n, EQUIVALENT INPUT NOISE VOLTAGE ( nv/ Hz ) Figure 2. Equivalent Input Noise Voltage versus Frequency f, FREQUENCY (Hz) AV = RS = Ω THD, TOTAL HARMONIC DISTORTION (%) Figure 3. Total Harmonic Distortion versus Frequency AV =. VO = 6. V (RMS) f, FREQUENCY (Hz) 5

6 TLC,AC TL2C,AC TL4C,AC Figure 4. Positive Peak Detector Figure 5. Voltage Controlled Current Source R3 Vin Reset /2 TL2 * N94. µf /2 TL2 *Polycarbonate or Polystyrene Capacitor VO Vin R R2 TL R4 R5 If R through R4 > > R5 then Iout = V in R5 IO VR Run Figure 6. Long Interval RC Timer R4 Clear R V R3 R2 C* R5 TL Time (t) = R4 C4n (VR/VRVI), R3 = R4, R5 =. R6 If R = R2: t =.693 R4C 6 R6 *Polycarbonate or Polystyrene Capacitor 2. V 2. V Figure 7. Isolating Large Capacitive Loads R 5. k R2 5. k VO CC 2 pf IO TL R3 RL 5. k CL.5 µf Overshoot % ts = µs When driving large CL, the VO slew rate is determined by CL and IO(max): V O t I O.2 C.5 L V/µs =.4 V/µs (with CL shown) Design Example: Second Timer VR = V C = l. mf R3 = R4 = 44 M R6 = 2 k R5 = 2. k R = R2 =. k 6

7 TLC,AC TL2C,AC TL4C,AC OUTLINE DIMENSIONS P SUFFIX CASE 6265 ISSUE K NOTE 2 T SEATING PLANE H 5 B 4 F A L C J N M D K G.3 (.5) M T A M B M NOTES:. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 92. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 2.54 BSC. BSC H J K L 7.62 BSC.3 BSC M N D SUFFIX CASE 755 (SO) ISSUE S A E B C A e D B 5 4 H A.25 M C B S A S.25 M B M SEATING PLANE. h X 45 C L NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A A..25 B C..25 D E e.27 BSC H h.25.5 L

8 TLC,AC TL2C,AC TL4C,AC OUTLINE DIMENSIONS 4 7 B N SUFFIX CASE 6466 ISSUE M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T SEATING PLANE N A INCHES MILLIMETERS DIM MIN MAX MIN MAX A F L B C D C F G. BSC 2.54 BSC H J K K J L M H G D 4 PL M N (.5) M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 432, P.O. Box 545, Denver, Colorado or NishiGotanda, Shinagawaku, Tokyo 4, Japan Customer Focus Center: Mfax : RMFAX@ .sps.mot.com TOUCHTONE ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; B Tai Ping Industrial Park, Motorola Fax Back System US & Canada ONLY Ting Kok Road, Tai Po, N.T., Hong Kong HOME PAGE: TLC/D

Amplifiers JFET INPUT OPERATIONAL AMPLIFIERS

Amplifiers JFET INPUT OPERATIONAL AMPLIFIERS Order this document by TLC/D These lowcost JFET input operational amplifiers combine two stateof theart linear technologies on a single monolithic integrated circuit. Each internally compensated operational