MC33502/D. 1.0 V, Rail to Rail, Dual Operational Amplifier

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MC3352. V, Rail to Rail, Dual Operational Amplifier The MC3352 operational amplifier provides rail to rail operation on both the input and output. The output can swing within 5 mv of each rail.

1 MC3352. V, Rail to Rail, Dual Operational Amplifier The MC3352 operational amplifier provides rail to rail operation on both the input and output. The output can swing within 5 mv of each rail. This rail to rail operation enables the user to make full use of the entire supply voltage range available. It is designed to work at very low supply voltages (. V and ground), yet can operate with a supply of up to 7. V and ground. Output current boosting techniques provide high output current capability while keeping the drain current of the amplifier to a minimum. Features Low Voltage, Single Supply Operation (. V and Ground to 7. V and Ground) High Input Impedance: Typically 4 fa Input Current Typical Unity Gain 5. V = 5. V = 4. MHz High Output Current (I SC = 4 5. V, 3 V) Output Voltage Swings within 5 mv of Both V Input Voltage Range Includes Both Supply Rails High Voltage Gain: db V No Phase Reversal on the Output for Over Driven Input Signals Input Offset Trimmed to.5 mv Typical Low Supply Current (I D =.2 ma/per Amplifier, Typical) 6 Drive Capability Extended Operating Temperature Range ( 4 to 5 C) Pb Free Packages are Available Applications Single Cell NiCd/Ni MH Powered Systems Interface to DSP Portable Communication Devices Low Voltage Active Filters Telephone Circuits Instrumentation Amplifiers Audio Applications Power Supply Monitor and Control Compatible with VCX Logic Output Inputs V EE PIN CONNECTIONS (Dual, Top View) Output 2 ORDERING INFORMATION Inputs 2 Device Package Shipping MC3352P PDIP 5 Units/Rail MC3352PG PDIP (Pb Free) 5 Units/Rail MC3352D SOIC 9 Units/Rail MC3352DG PDIP P SUFFIX CASE 626 SOIC D SUFFIX CASE 75 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week or G = Pb Free Package SOIC (Pb Free) MARKING DIAGRAMS MC3352P AWL YYWWG 3352 ALYW 9 Units/Rail MC3352DR2 SOIC 25 Tape & Reel MC3352DR2G SOIC (Pb Free) 25 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D. Semiconductor Components Industries, LLC, 26 July, 26 Rev. Publication Order Number: MC3352/D

2 MC3352 Base Current Boost Inputs Input Stage Buffer with V Level Shift Output Stage Outputs Offset Voltage Trim Saturation Detector Base Current Boost This device contains 9 active transistors per amplifier. Figure. Simplified Block Diagram MAXIMUM RATINGS Rating Symbol Value Unit ÁÁ Supply Voltage ( to V EE ) Á V S ÁÁ 7. V ÁÁ ESD Protection Voltage at any Pin Á V ESD ÁÁ 2 V Human Body Model ÁÁ Voltage at Any Device Pin V DP V S ±.3 V ÁÁ Input Differential Voltage Range V IDR to V EE V ÁÁ Common Mode Input Voltage Range V CM to V EE V ÁÁ Output Short Circuit Duration t S Note s ÁÁ Maximum Junction Temperature ÁÁ Storage Temperature Range T stg 65 to 5 C Á ÁÁ Maximum Power Dissipation Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. Power dissipation must be considered to ensure maximum junction temperature (T J ) is not exceeded. 2. ESD data available upon request. T J P D 5 Note C mw 2

3 MC3352 DC ELECTRICAL CHARACTERISTICS ( = 5. V, V EE = V, V CM = V O = /2, R L to /2,, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Input Offset Voltage (V CM = to ) V IO mv =. V T A = 4 to 5 C = 3. V T A = 4 to 5 C = 5. V T A = 4 to 5 C Input Offset Voltage Temperature Coefficient (R S = 5 ) V IO ÁÁ / T. V/ C T A = 4 to 5 C I I IB I.4 ÁÁÁ na Input Bias Current ( =. to 5. V) Common Mode Input Voltage Range V ICR V EE ÁÁÁ V Large Signal Voltage Gain A VOL kv/v =. V () R L = k 25 R L =. k 5. 5 = 3. V () R L = k 5 5 R L =. k 25 = 5. V () R L = k 5 5 R L =. k 25 2 Output Voltage Swing, High (V ID = ±.2 V) ÁÁÁ V V OH =. V () R L = k.9.95 R L = 6.5. =. V (T A = 4 to 5 C) R L = k.5 R L = 6. = 3. V () R L = k R L = = 3. V (T A = 4 to 5 C) R L = k 2.5 R L = = 5. V () R L = k R L = = 5. V (T A = 4 to 5 C) R L = k 4.5 R L =

4 MC3352 DC ELECTRICAL CHARACTERISTICS ( = 5. V, V EE = V, V CM = V O = /2, R L to /2,, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit ÁÁ Output Voltage Swing, Low (V ID = ±.2 V) V OL =. V () R L = k.5.2 R L = 6..5 =. V (T A = 4 to 5 C) R L = k. R L = 6.5 = 3. V () R L = k.5.2 R L = 6.. = 3. V (T A = 4 to 5 C) R L = k. R L = 6.5 = 5. V () R L = k.5.2 R L = 6.5. = 5. V (T A = 4 to 5 C) R L = k. R L = 6.2 Common Mode Rejection (V in = to 5. V) CMR 6 75 db ÁÁÁ ÁÁ Power Supply Rejection PSR 6 75 db /V EE = 5. V/Ground to 3. V/Ground Output Short Circuit Current (V in Diff = ±. V) I SC ma =. V Source Sink 3 26 = 3. V Source Sink = 5. V Source Sink Power Supply Current (Per Amplifier, V O = V) ÁÁÁ ma I D =. V.2.75 = 3. V.5 2. = 5. V =. V (T A = 4 to 5 C) 2. = 3. V (T A = 4 to 5 C) 2.25 = 5. V (T A = 4 to 5 C) 2.5 V 4

5 MC3352 AC ELECTRICAL CHARACTERISTICS ( = 5. V, V EE = V, V CM = V O = /2,, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Slew Rate (V S = ±2.5 V, V O = 2. to 2. V, R L = 2. k, A V =.) SR V/ s Positive Slope Negative Slope ÁÁÁ Gain Bandwidth Product (f = khz) GBW =.5 V, V EE =.5 V =.5 V, V EE =.5 V = 2.5 V, ÁÁÁ ÁÁ Gain Margin (R L = k, C L = pf) Am 6.5 db ÁÁ Phase Margin (R L = k, C L = pf) φ m 6 Deg ÁÁÁ Channel Separation (f =. Hz to 2 khz, R L = 6 ) CS 2 db ÁÁ Power Bandwidth (V O = 4. V pp, R L =. k, THD.%) BW P 2 khz ÁÁÁ Total Harmonic Distortion (V O = 4.5 V pp, R L = 6, A V =.) THD f =. khz.4 f = khz. Differential Input Resistance (V CM = V) R in >. ÁÁÁ terra Differential Input Capacitance (V CM = V) C in 2. ÁÁÁ pf Equivalent Input Noise Voltage ( =. V, V CM = V, V EE = Gnd, e n nv/ Hz R S = ) f =. khz 3 MHz % IN IN+ Offset Voltage Trim Output Voltage Saturation Detector Clamp Out Body Bias Figure 2. Representative Block Diagram 5

6 MC3352 General Information The MC3352 dual operational amplifier is unique in its ability to provide. V rail to rail performance on both the input and output by using a SMARTMOS process. The amplifier output swings within 5 mv of both rails and is able to provide 5 ma of output drive current with a 5. V supply, and ma with a. V supply. A 5. MHz bandwidth and a slew rate of 3. V/ s is achieved with high speed depletion mode NMOS (DNMOS) and vertical PNP transistors. This device is characterized over a temperature range of 4 C to 5 C. Circuit Information Input Stage One volt rail to rail performance is achieved in the MC3352 at the input by using a single pair of depletion mode NMOS devices (DNMOS) to form a differential amplifier with a very low input current of 4 fa. The normal input common mode range of a DNMOS device, with an ion implanted negative threshold, includes ground and relies on the body effect to dynamically shift the threshold to a positive value as the gates are moved from ground towards the positive supply. Because the device is manufactured in a p well process, the body effect coefficient is sufficiently large to ensure that the input stage will remain substantially saturated when the inputs are at the positive rail. This also applies at very low supply voltages. The. V rail to rail input stage consists of a DNMOS differential amplifier, a folded cascode, and a low voltage balanced mirror. The low voltage cascoded balanced mirror provides high st stage gain and base current cancellation without sacrificing signal integrity. Also, the input offset voltage is trimmed to less than. mv because of the limited available supply voltage. The body voltage of the input DNMOS differential pair is internally trimmed to minimize the input offset voltage. A common mode feedback path is also employed to enable the offset voltage to track over the input common mode voltage. The total operational amplifier quiescent current drop is.3 ma/amp. Output Stage An additional feature of this device is an on demand base current cancellation amplifier. This feature provides base drive to the output power devices by making use of a buffer amplifier to perform a voltage to current conversion. This is done in direct proportion to the load conditions. This on demand feature allows these amplifiers to consume only a few micro amps of current when the output stage is in its quiescent mode. Yet it provides high output current when required by the load. The rail to rail output stage current boost circuit provides 5 ma of output current with a 5. V supply (For a. V supply output stage will do ma) enabling the operational amplifier to drive a 6 load. A buffer is necessary to isolate the load current effects in the output stage from the input stage. Because of the low voltage conditions, a DNMOS follower is used to provide an essentially zero voltage level shift. This buffer isolates any load current changes on the output stage from loading the input stage. A high speed vertical PNP transistor provides excellent frequency performance while sourcing current. The operational amplifier is also internally compensated to provide a phase margin of 6 degrees. It has a unity gain of 5. MHz with a 5. V supply and 4. MHz with a. V supply. Low Voltage Operation The MC3352 will operate at supply voltages from.9 to 7. V and ground. When using the MC3352 at supply voltages of less than.2 V, input offset voltage may increase slightly as the input signal swings within approximately 5 mv of the positive supply rail. This effect occurs only for supply voltages below.2 V, due to the input depletion mode MOSFETs starting to transition between the saturated to linear region, and should be considered when designing high side dc sensing applications operating at the positive supply rail. Since the device is rail to rail on both input and output, high dynamic range single battery cell applications are now possible. 6

MC3352 V sat, OUTPUT SATURATION VOLTAGE (mv) 2 4 6 6 4 2. k = 5. V V EE = V R L to /2 k k R L, LOAD RESISTANCE ( ). M V EE M V sat, OUTPUT SATURATION VOLTAGE (V).5. Source Saturation T A = 25 C T A = 55 C I O, OUTPUT CURRENT (ma).

Drive Output Source/Sink Saturation Voltage versus Load Current I IB, INPUT CURRENT (pa).... 25 5 75 25 A VOL, GAIN (db) 6 4 2. = 2.5 V R L = k Phase Gain. k k Phase Margin = 6 k.

7 MC3352 V sat, OUTPUT SATURATION VOLTAGE (mv) k = 5. V V EE = V R L to /2 k k R L, LOAD RESISTANCE ( ). M V EE M V sat, OUTPUT SATURATION VOLTAGE (V).5. Source Saturation T A = 25 C T A = 55 C I O, OUTPUT CURRENT (ma). Sink Saturation T A = 25 C.5 V EE = 5. V T A = 55 C V EE Figure 3. Output Saturation versus Load Resistance Figure 4. Drive Output Source/Sink Saturation Voltage versus Load Current I IB, INPUT CURRENT (pa) A VOL, GAIN (db) = 2.5 V R L = k Phase Gain. k k Phase Margin = 6 k. M M φ m, EXCESS PHASE (DEGREES) Figure 5. Input Current versus Temperature Figure 6. Gain and Phase versus Frequency 2 mv/div =.5 V V EE =.5 V A CL =. C L = pf R L = k. V/DIV (mv) = 2.5 V A CL =. C L = pf R L = 6 t, TIME (5 s/div) t, TIME (. s/div) Figure 7. Transient Response Figure. Slew Rate 7

8 MC3352 PD max, MAXIMUM POWER DISSIPATION (mw) SO Pkg DIP Pkg ΔAVOL, OPEN LOOP GAIN (db) = 2.5 V 4 R L = Figure 9. Maximum Power Dissipation versus Temperature Figure. Open Loop Voltage Gain versus Temperature V O, OUTPUT VOLTAGE (V pp ) = 2.5 V A V =. R L = 6. k k k. M CMR, COMMON MODE REJECTION (db) = 2.5 V. k k k. M Figure. Output Voltage versus Frequency Figure 2. Common Mode Rejection versus Frequency PSR, POWER SUPPLY REJECTION (db) = 2.5 V =.5 V V EE =.5 V 2 Either or V EE. k k k Figure 3. Power Supply Rejection versus Frequency II SC I, OUTPUT SHORT CIRCUIT CURRENT (ma) = 2.5 V Sink Source V S V O (V) Figure 4. Output Short Circuit Current versus Output Voltage

9 MC3352 II SC I, OUTPUT SHORT CIRCUIT CURRENT (ma) Sink = 2.5 V Source I CC, SUPPLY CURRENT PER AMPLIFIER (ma) T A = 25 C T A = 55 C ±.5 ±. ±.5 ±2., V EE, SUPPLY VOLTAGE (V) ±2.5 Figure 5. Output Short Circuit Current versus Temperature Figure 6. Supply Current per Amplifier versus Supply Voltage with No Load 5 5 PERCENTAGE OF AMPLIFIERS (%) = 3. V V O =.5 V V EE = V 6 Amplifiers Tested from 2 Wafer Lots PERCENTAGE OF AMPLIFIERS (%) = 3. V V O =.5 V V EE = V 6 Amplifiers Tested from 2 Wafer Lots TC VIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT ( V/ C) Figure 7. Input Offset Voltage Temperature Coefficient Distribution INPUT OFFSET VOLTAGE (mv) Figure. Input Offset Voltage Distribution THD, TOTAL HARMONIC DISTORTION (%).... A V = A V = A V = A V =. V out =.5 V pp R L = 6 V EE =. V. k k Figure 9. Total Harmonic Distortion versus Frequency with. V Supply k THD, TOTAL HARMONIC DISTORTION (%). A V =... V out = 4. V pp R L = 6 A V = A V = A V =.. k k V EE = 5. V Figure 2. Total Harmonic Distortion versus Frequency with 5. V Supply k 9

10 MC3352 SR, SLEW RATE (V/ μ s) V EE =. V + Slew Rate V EE =. V Slew Rate V EE = 5. V + Slew Rate V EE = 5. V Slew Rate Figure 2. Slew Rate versus Temperature GBW, GAIN BANDWIDTH PRODUCT (MHz) V EE = 5. V f = khz Figure 22. Gain Bandwidth Product versus Temperature A VOL, GAIN (db) R L = 6 2 C L = 4 k k V EE =. V V EE =. V V EE = 5. V V EE = 5. V. M M Figure 23. Voltage Gain and Phase versus Frequency Φ m, PHASE MARGIN ( ) V EE = 5. V R L = 6 C L = pf Phase Margin Gain Margin Figure 24. Gain and Phase Margin versus Temperature AV, GAIN MARGIN (db) Φ m, PHASE MARGIN ( ) V EE = 5. V R L = 6 C L = pf Phase Margin Gain Margin A V GAIN MARGIN (db) Φ m, PHASE MARGIN ( ) Phase Margin Gain Margin V EE = 5. V R L = A V, GAIN MARGIN (db). k k k. M R T, DIFFERENTIAL SOURCE RESISTANCE ( ) Figure 25. Gain and Phase Margin versus Differential Source Resistance C L, CAPACITIVE LOAD (pf) Figure 26. Feedback Loop Gain and Phase versus Capacitive Load

11 MC3352 CS, CHANNEL SEPARATION (db) 2 6 A V = A V = 4 V EE = 5. V R L = 6 2 V O = 4. V pp 3 3 k 3 k k 3 k Figure 27. Channel Separation versus Frequency V O, OUTPUT VOLTAGE (V pp ) R L = 6 ±.5 ±. ±.5 ±2. ±2.5 ±3. ±3.5, V EE, SUPPLY VOLTAGE (V) Figure 2. Output Voltage Swing versus Supply Voltage en, EQUIVALENT INPUT NOISE VOLTAGE (nv/ Hz) V EE = 5. V. k k k Φ m, PHASE MARGIN ( ) R L = 6 C L = Phase Margin Gain Margin V EE, SUPPLY VOLTAGE (V) A V, GAIN MARGIN (db) Figure 29. Equivalent Input Noise Voltage versus Frequency Figure 3. Gain and Phase Margin versus Supply Voltage V EE, USEABLE SUPPLY VOLTAGE (V) A VOL db R L = Figure 3. Useable Supply Voltage versus Temperature A VOL, OPEN LOOP GAIN (db) V EE, SUPPLY VOLTAGE (V) Figure 32. Open Loop Gain versus Supply Voltage R L =

12 MC3352 R T 47 k. V C T. nf R a 47 k R b 47 k + R 2 47 k f O. khz. V pp f O R C T T In 2(R a R b ) R 2 Figure 33.. V Oscillator A f C f 4 pf R f k f L f H R 2 k C nf R k.5 V +.5 V V O f L 2 R C 2 Hz f H 2 R f C f 4. khz A f R f R 2 Figure 34.. V Voiceband Filter 2

13 MC V 5. V V ref FB 22 k 47 pf 5 6 MC Output A Output B k MC k. k From Current Sense Provides current sense amplification and eliminates leading edge spike. Figure 35. Power Supply Application V O I O. V R. k R sense R 3. k + R 4. k R k V L I O I L 435 ma 463 A 22 ma 492 A I O / I L 2 x 6 R L 75 I L For best performance, use low tolerance resistors. R k Figure 36.. V Current Pump 3

14 MC3352 PACKAGE DIMENSIONS SOIC NB CASE 75 7 ISSUE AH Y B X A 5 4 S.25 (.) M Y M K NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU 75 6 ARE OBSOLETE. NEW STANDARD IS Z H G D C.25 (.) M Z Y S X S SEATING PLANE. (.4) N X 45 M J MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.27 BSC.5 BSC H J K M N S SOLDERING FOOTPRINT* SCALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 4

15 MC3352 PACKAGE DIMENSIONS LEAD PDIP CASE ISSUE L 5 B NOTES:. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 92. NOTE 2 T SEATING PLANE H 4 F A C N D K G.3 (.5) M T A M B M L J M MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 2.54 BSC. BSC H J K L 7.62 BSC.3 BSC M N SMARTMOS is a trademark of Motorola, Inc. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 27 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC3352/D

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