NTMD4820NR2G. Power MOSFET 30 V, 8 A, Dual N Channel, SOIC 8
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1 NTMDN Power MOSFET V, A, Dual N Channel, SOIC Features Low R DS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Dual SOIC Surface Mount Package Saves Board Space Applications Disk Drives DC DC Converters Printers MAXIMUM RATINGS ( unless otherwise stated) Rating Symbol Value Unit Drain to Source Voltage V DSS V Gate to Source Voltage V GS ± V T A = C I D 6. A Current R JA (Note ) T A = 7 C. R JA (Note ) Current R JA (Note ) R JA (Note ) Current R JA t < s (Note ) R JA t < s (Note ) Pulsed Drain Current Steady State T A = C P D. W T A = C I D.9 A T A = 7 C.9 T A = C P D.7 W T A = C I D. A T A = 7 C 6. T A = C P D. W T A = C, t p = s I DM A Operating Junction and Storage Temperature T J, T STG to + Source Current (Body Diode) I S. A Single Pulse Drain to Source Avalanche Energy T J = C, V DD = V, V GS = V, I L = A pk, L =. mh, R G = Lead Temperature for Soldering Purposes (/ from case for s) THERMAL RESISTANCE RATINGS C EAS 6. mj T L 6 C Rating Symbol Max Unit Junction to Ambient Steady State (Note ) R JA 97. Junction to Ambient t s (Note ) R JA 6 Junction to FOOT (Drain) R JF Junction to Ambient Steady State (Note ) R JA 67. C/W. Surface mounted on FR board using inch sq pad size, oz Cu.. Surface mounted on FR board using the minimum recommended pad size. V (BR)DSS V G R DS(on) Max V 7 V N Channel ORDERING INFORMATION I D Max A Device Package Shipping NTMDNRG SOIC CASE 7 STYLE N = Device Code A = Assembly Location Y = Year WW = Work Week = Pb Free Package SOIC (Pb Free) MARKING DIAGRAM & PIN ASSIGNMENT D D D D N AYWW S G S G /Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD/D. D S Semiconductor Components Industries, LLC, 9 August, 9 Rev. Publication Order Number: NTMDN/D
2 NTMDN ELECTRICAL CHARACTERISTICS ( unless otherwise noted)jk Characteristic Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage V (BR)DSS V GS = V, I D = A V Drain to Source Breakdown Voltage Temperature Coefficient V (BR)DSS /T J 6 mv/ C Zero Gate Voltage Drain Current I DSS VGS = V,. V DS = V T J = C A Gate to Source Leakage Current I GSS V DS = V, V GS = ± V ± na ON CHARACTERISTICS (Note ) Gate Threshold Voltage V GS(TH) V GS = V DS, I D = A.. V Negative Threshold Temperature Coefficient V GS(TH) /T J. mv/ C Drain to Source On Resistance R DS(on) V GS = V I D = 7. A V GS =. V I D = 6. A 7 m Forward Transconductance g FS V DS =. V, I D = 7. A S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance C ISS 9 Output Capacitance C OSS V GS = V, f =. MHz, V DS = V pf Reverse Transfer Capacitance C RSS Total Gate Charge Q G(TOT) 7.7 Threshold Gate Charge Q G(TH). V GS =. V, V DS = V, I D = 7. A Gate to Source Charge Q GS. nc Gate to Drain Charge Q GD. Total Gate Charge Q G(TOT) V GS = V, V DS = V, I D = 7. A. nc SWITCHING CHARACTERISTICS (Note ) Turn On Delay Time t d(on) 9. Rise Time t r VGS = V, VDD = V,. Turn Off Delay Time t d(off) I D =. A, R G = 6. ns Fall Time t f 6. DRAIN TO SOURCE CHARACTERISTICS Forward Diode Voltage V SD VGS = V.7. V I D =. A.9 Reverse Recovery Time t RR 7. ns Charge Time T a VGS = V, dis/dt = A/ s,. Discharge Time T I S =. A b 9. Reverse Recovery Time Q RR. nc PACKAGE PARASITIC VALUES Source Inductance L S.66 nh Drain Inductance L D. nh T A = C Gate Inductance L G. nh Gate Resistance R G... Pulse Test: pulse width s, duty cycle %.. Switching characteristics are independent of operating junction temperatures.
3 I D, DRAIN CURRENT (AMPS) V V. V V. V V. V NTMDN TYPICAL PERFORMANCE CURVES. V V. V. V I D, DRAIN CURRENT (AMPS) V DS V. V T J = C V GS, GATE TO SOURCE VOLTAGE (VOLTS) R DS(on), DRAIN TO SOURCE RESISTANCE ( ) Figure. On Region Characteristics I D = 7. A V GS, GATE TO SOURCE VOLTAGE (VOLTS) Figure. On Resistance vs. Gate to Source Voltage R DS(on), DRAIN TO SOURCE RESISTANCE ( ) Figure. Transfer Characteristics V GS =. V V GS = V 6 I D, DRAIN CURRENT (AMPS) Figure. On Resistance vs. Drain Current and Gate Voltage R DS(on), DRAIN TO SOURCE RESISTANCE (NORMALIZED) I D = 7. A V GS = V.6 7 T J, JUNCTION TEMPERATURE ( C) I DSS, LEAKAGE (na) V GS = V T J = C T J = C Figure. On Resistance Variation with Temperature Figure 6. Drain to Source Leakage Current vs. Voltage
4 C, CAPACITANCE (pf) C iss C oss C rss DRAIN TO SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation NTMDN TYPICAL PERFORMANCE CURVES V GS = V V GS, GATE-TO-SOURCE VOLTAGE (VOLTS) V DS Q GS Q GD QT V GS I D = 7. A 6 Q G, TOTAL GATE CHARGE (nc) Figure. Gate To Source and Drain To Source Voltage vs. Total Charge 6 6 V DS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) t, TIME (ns) V DD = V I D = A V GS = V t d(off) t f t r t d(on) I S, SOURCE CURRENT (AMPS) V GS = V R G, GATE RESISTANCE (OHMS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance V SD, SOURCE TO DRAIN VOLTAGE (VOLTS) Figure. Diode Forward Voltage vs. Current. ID, DRAIN CURRENT (AMPS) s s ms ms V GS = V SINGLE PULSE. T C = C R DS(on) LIMIT dc THERMAL LIMIT PACKAGE LIMIT.. Figure. Maximum Rated Forward Biased Safe Operating Area EAS, SINGLE PULSE DRAIN TO SOURCE AVALANCHE ENERGY (mj) 7 7 I D = A T J, STARTING JUNCTION TEMPERATURE ( C) Figure. Maximum Avalanche Energy vs. Starting Junction Temperature
5 NTMDN PACKAGE DIMENSIONS X B Y Z H G A D S C. (.) M Z Y S X S. (.) M SEATING PLANE Y. (.) SOIC NB CASE 7 7 ISSUE AJ M N X M K SOLDERING FOOTPRINT*..6 J NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.M, 9.. CONTROLLING DIMENSION: MILLIMETER.. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.. MAXIMUM MOLD PROTRUSION. (.6) PER SIDE.. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.7 (.) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU 7 6 ARE OBSOLETE. NEW STANDARD IS 7 7. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B....7 C D.... G.7 BSC. BSC H.... J K M N.... S STYLE : PIN. SOURCE. GATE. SOURCE. GATE. DRAIN 6. DRAIN 7. DRAIN. DRAIN SCALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 6, Denver, Colorado 7 USA Phone: 67 7 or 6 Toll Free USA/Canada Fax: or 67 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 9 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: 77 ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NTMDN/D
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FDD4685-F085 P-Channel PowerTrench MOSFET -40 V, -32 A, 35 mω Features Typical R DS(on) = 23 m at V GS = -10V, I D = -8.4 A Typical R DS(on) = 30 m at V GS = -4.5V, I D = -7 A Typical Q g(tot) = 19 nc
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More informationPUBLICATION ORDERING INFORMATION. Semiconductor Components Industries, LLC
FDS39 FDS39 V N-Channel Dual PowerTrench MOSFET General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or
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FDG6301N-F085 Dual N-Channel, Digital FET Features 25 V, 0.22 A continuous, 0.65 A peak. R DS(ON) = 4 @ V GS = 4.5 V, R DS(ON) = 5 @ V GS = 2.7 V. Very low level gate drive requirements allowing directoperation
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FDD35H Dual N & P-Channel PowerTrench MOSFET N-Channel: V, 3.9A, mω P-Channel: -V, -9.A, 9mΩ Features Q: N-Channel Max r DS(on) = mω at V GS = V, I D =.3A Max r DS(on) = mω at V GS = V, I D =.A : P-Channel
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